coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

1 participants
877 discussions

Change in coreboot[master]: libpayload/generic_hub: Detect port disconnect after reset
by Julius Werner (Code Review) 13 Jul '18

13 Jul '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/27477 ) Change subject: libpayload/generic_hub: Detect port disconnect after reset ...................................................................... Patch Set 1: I don't understand what this patch is needed for. The general concept for libpayload's USB stack is that the payload keeps calling usb_poll() in regular intervals. So if a device transforms upon reset like this, the new SuperSpeed port should just get enumerated as part of the next usb_poll(). Why do we need to add a bunch of custom code to enumerate it right now? Calling code should generally not be written in a way that relies on all USB devices being enumerated immediately with the first usb_poll(). -- To view, visit https://review.coreboot.org/27477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c Gerrit-Change-Number: 27477 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 13 Jul 2018 22:28:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: libpayload: Add UNKNOWN_SPEED to usb_speed enum
by Julius Werner (Code Review) 13 Jul '18

13 Jul '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/27476 ) Change subject: libpayload: Add UNKNOWN_SPEED to usb_speed enum ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27476/1/payloads/libpayload/drivers/usb/gen… File payloads/libpayload/drivers/usb/generic_hub.c: https://review.coreboot.org/#/c/27476/1/payloads/libpayload/drivers/usb/gen… PS1, Line 174: speed); usb_attach_device() already reports this in a human-readable way, so I don't think you really need it here. -- To view, visit https://review.coreboot.org/27476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919 Gerrit-Change-Number: 27476 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 22:20:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: libpayload/xhci: Document struct offsets on xhci_t
by Julius Werner (Code Review) 13 Jul '18

13 Jul '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/27474 ) Change subject: libpayload/xhci: Document struct offsets on xhci_t ...................................................................... Patch Set 1: Code-Review+2 Not sure this is really necessary since these offsets are in the XHCI spec and people usually know the registers by name anyway... but I guess it doesn't hurt either. -- To view, visit https://review.coreboot.org/27474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6 Gerrit-Change-Number: 27474 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 22:16:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: libpayload/xhci: Check noop return code when debugging
by Raul Rangel (Code Review) 13 Jul '18

13 Jul '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27478 Change subject: libpayload/xhci: Check noop return code when debugging ...................................................................... libpayload/xhci: Check noop return code when debugging We don't want to silently continue when the command ring is broken. BUG=b:76831439 TEST=Verified on grunt Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/drivers/usb/xhci.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/27478/1 diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 2e70316..a3bf182 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -403,9 +403,12 @@ xhci_post_command(xhci); /* Wait for result in event ring */ - xhci_wait_for_command_done(xhci, cmd, 1); - xhci_debug("Command ring is %srunning\n", - (xhci->opreg->crcr_lo & CRCR_CRR) ? "" : "not "); + int cc = xhci_wait_for_command_done(xhci, cmd, 1); + + xhci_debug("Command ring is %srunning: cc: %d\n", + (xhci->opreg->crcr_lo & CRCR_CRR) ? "" : "not ", cc); + if (cc != CC_SUCCESS) + fatal("noop command failed.\n"); } #endif } -- To view, visit https://review.coreboot.org/27478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4 Gerrit-Change-Number: 27478 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

1 0

Change in coreboot[master]: libpayload/generic_hub: Detect port disconnect after reset
by Raul Rangel (Code Review) 13 Jul '18

13 Jul '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27477 Change subject: libpayload/generic_hub: Detect port disconnect after reset ...................................................................... libpayload/generic_hub: Detect port disconnect after reset If a port disconnects after a reset we should abort any initialization on the port. At the same time this might mean the device has re-enumerated as a 3.0 device so we should rescan all the ports. I decided to not add a return status enum since that would require a lot of changes. I opted to just return 2 as the magic reenum value. BUG=b:76831439 TEST=Verified USB-C devices that get detected correctly in depthcharge. Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/drivers/usb/generic_hub.c 1 file changed, 26 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/27477/1 diff --git a/payloads/libpayload/drivers/usb/generic_hub.c b/payloads/libpayload/drivers/usb/generic_hub.c index 89da934..a2aea7c 100644 --- a/payloads/libpayload/drivers/usb/generic_hub.c +++ b/payloads/libpayload/drivers/usb/generic_hub.c @@ -157,6 +157,15 @@ if (hub->ops->reset_port) { if (hub->ops->reset_port(dev, port) < 0) return -1; + + if (!hub->ops->port_connected(dev, port)) { + usb_debug( + "generic_hub: Port %d disconnected after " + "reset. Possibly upgraded, rescan required.\n", + port); + return 2; + } + /* after reset the port will be enabled automatically */ const int ret = generic_hub_wait_for_port( /* time out after 1,000 * 10us = 10ms */ @@ -214,15 +223,24 @@ hub->ops->hub_status_changed(dev) != 1) return; - int port; - for (port = 1; port <= hub->num_ports; ++port) { - const int ret = hub->ops->port_status_changed(dev, port); - if (ret < 0) { - return; - } else if (ret == 1) { - usb_debug("generic_hub: Port change at %d\n", port); - if (generic_hub_scanport(dev, port) < 0) + int reenum_limit = 1; + for (int i = 0; i < reenum_limit && i < 2; ++i) { + for (int port = 1; port <= hub->num_ports; ++port) { + const int ret = + hub->ops->port_status_changed(dev, port); + if (ret < 0) { return; + } else if (ret == 1) { + usb_debug("generic_hub: Port change at %d\n", + port); + int rtn = generic_hub_scanport(dev, port); + if (rtn == 2) { + reenum_limit++; + continue; + } else if (rtn < 0) { + return; + } + } } } } -- To view, visit https://review.coreboot.org/27477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c Gerrit-Change-Number: 27477 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

1 0

Change in coreboot[master]: libpayload: Make libpayload compile using gnu11
by Raul Rangel (Code Review) 13 Jul '18

13 Jul '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27475 Change subject: libpayload: Make libpayload compile using gnu11 ...................................................................... libpayload: Make libpayload compile using gnu11 This matches coreboot. BUG=b:76831439 TEST=emerge-grunt libpayload deptcharge chromeos-bootimage then booted image Change-Id: I3a3baa03e03a31e9e75b201ac4fa642505fc1d3a Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27475/1 diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 429bf05..1a0acf1 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -147,7 +147,7 @@ STRIP := $(STRIP_$(ARCH-y)) AR := $(AR_$(ARCH-y)) -CFLAGS += $(CFLAGS_$(ARCH-y)) +CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y)) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) -- To view, visit https://review.coreboot.org/27475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3a3baa03e03a31e9e75b201ac4fa642505fc1d3a Gerrit-Change-Number: 27475 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

1 0

Change in coreboot[master]: libpayload: Add UNKNOWN_SPEED to usb_speed enum
by Raul Rangel (Code Review) 13 Jul '18

13 Jul '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27476 Change subject: libpayload: Add UNKNOWN_SPEED to usb_speed enum ...................................................................... libpayload: Add UNKNOWN_SPEED to usb_speed enum xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum is unsigned so this results in a positive value which implies success. Adding a -1 to the enum will make it signed so the >= 0 check will work correctly. BUG=b:76831439 TEST=verified on grunt that -1 is returned when port is disabled. Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/drivers/usb/generic_hub.c M payloads/libpayload/drivers/usb/xhci_rh.c M payloads/libpayload/include/usb/usb.h 3 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27476/1 diff --git a/payloads/libpayload/drivers/usb/generic_hub.c b/payloads/libpayload/drivers/usb/generic_hub.c index 9f86705..89da934 100644 --- a/payloads/libpayload/drivers/usb/generic_hub.c +++ b/payloads/libpayload/drivers/usb/generic_hub.c @@ -170,7 +170,8 @@ const usb_speed speed = hub->ops->port_speed(dev, port); if (speed >= 0) { - usb_debug("generic_hub: Success at port %d\n", port); + usb_debug("generic_hub: Success at port %d, speed: %d\n", port, + speed); if (hub->ops->reset_port) mdelay(10); /* Reset recovery time (usb20 spec 7.1.7.5) */ diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index d7ba82c..ddf6ce8 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -95,7 +95,7 @@ >> PORTSC_PORT_SPEED_START) - 1; } else { - return -1; + return UNKNOWN_SPEED; } } diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index ef18926..79c4586 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -187,7 +187,11 @@ } endpoint_t; typedef enum { - FULL_SPEED = 0, LOW_SPEED = 1, HIGH_SPEED = 2, SUPER_SPEED = 3, + UNKNOWN_SPEED = -1, + FULL_SPEED = 0, + LOW_SPEED = 1, + HIGH_SPEED = 2, + SUPER_SPEED = 3, } usb_speed; struct usbdev { -- To view, visit https://review.coreboot.org/27476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919 Gerrit-Change-Number: 27476 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

1 0

Change in coreboot[master]: libpayload/xhci: Document struct offsets on xhci_t
by Raul Rangel (Code Review) 13 Jul '18

13 Jul '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27474 Change subject: libpayload/xhci: Document struct offsets on xhci_t ...................................................................... libpayload/xhci: Document struct offsets on xhci_t This makes it easier to know what offset each register references. BUG=b:76831439 TEST=none Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/drivers/usb/xhci_private.h 1 file changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27474/1 diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 14d0e89..ab1dfa9 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -325,16 +325,16 @@ /* capreg is read-only, so no need for volatile, and thus 32bit accesses can be assumed. */ struct capreg { - u8 caplength; - u8 res1; - union { + u8 caplength; /* 0x00 */ + u8 res1; /* 0x01 */ + union { /* 0x02 */ u16 hciversion; struct { u8 hciver_lo; u8 hciver_hi; } __packed; } __packed; - union { + union { /* 0x04 */ u32 hcsparams1; struct { unsigned long MaxSlots:7; @@ -343,7 +343,7 @@ unsigned long MaxPorts:8; } __packed; } __packed; - union { + union { /* 0x08 */ u32 hcsparams2; struct { unsigned long IST:4; @@ -354,7 +354,7 @@ unsigned long Max_Scratchpad_Bufs_Lo:5; } __packed; } __packed; - union { + union { /* 0x0C */ u32 hcsparams3; struct { unsigned long u1latency:8; @@ -362,7 +362,7 @@ unsigned long u2latency:16; } __packed; } __packed; - union { + union { /* 0x10 */ u32 hccparams; struct { unsigned long ac64:1; @@ -378,42 +378,42 @@ unsigned long xECP:16; } __packed; } __packed; - u32 dboff; - u32 rtsoff; + u32 dboff; /* 0x14 */ + u32 rtsoff; /* 0x18 */ } __packed *capreg; /* opreg is R/W is most places, so volatile access is necessary. volatile means that the compiler seeks byte writes if possible, making bitfields unusable for MMIO register blocks. Yay C :-( */ volatile struct opreg { - u32 usbcmd; + u32 usbcmd; /* 0x00 */ #define USBCMD_RS (1 << 0) #define USBCMD_HCRST (1 << 1) #define USBCMD_INTE (1 << 2) - u32 usbsts; + u32 usbsts; /* 0x04 */ #define USBSTS_HCH (1 << 0) #define USBSTS_HSE (1 << 2) #define USBSTS_EINT (1 << 3) #define USBSTS_PCD (1 << 4) #define USBSTS_CNR (1 << 11) #define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000) - u32 pagesize; - u8 res1[0x13-0x0c+1]; - u32 dnctrl; - u32 crcr_lo; - u32 crcr_hi; + u32 pagesize; /* 0x08 */ + u8 res1[0x13-0x0c+1]; /* 0x0C */ + u32 dnctrl; /* 0x14 */ + u32 crcr_lo; /* 0x18 */ + u32 crcr_hi; /* 0x1C */ #define CRCR_RCS (1 << 0) #define CRCR_CS (1 << 1) #define CRCR_CA (1 << 2) #define CRCR_CRR (1 << 3) - u8 res2[0x2f-0x20+1]; - u32 dcbaap_lo; - u32 dcbaap_hi; - u32 config; + u8 res2[0x2f-0x20+1]; /* 0x20 */ + u32 dcbaap_lo; /* 0x30 */ + u32 dcbaap_hi; /* 0x34 */ + u32 config; /* 0x38 */ #define CONFIG_LP_MASK_MaxSlotsEn 0xff - u8 res3[0x3ff-0x3c+1]; + u8 res3[0x3ff-0x3c+1]; /* 0x3C */ struct { - u32 portsc; + u32 portsc; /* 0x400 + 4 * port */ #define PORTSC_CCS (1 << 0) #define PORTSC_PED (1 << 1) // BIT 2 rsvdZ @@ -443,9 +443,9 @@ #define PORTSC_DR (1 << 30) #define PORTSC_WPR (1 << 31) #define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE) - u32 portpmsc; - u32 portli; - u32 res; + u32 portpmsc; /* 0x404 + 4 * port */ + u32 portli; /* 0x408 + 4 * port */ + u32 res; /* 0x40C + 4 * port */ } __packed prs[]; } __packed *opreg; -- To view, visit https://review.coreboot.org/27474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6 Gerrit-Change-Number: 27474 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

1 0

Change in coreboot[master]: Documentation/mb/sifive: Update TODO list; UART driver has been merged
by Philipp Deppenwiese (Code Review) 13 Jul '18

13 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27398 ) Change subject: Documentation/mb/sifive: Update TODO list; UART driver has been merged ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94 Gerrit-Change-Number: 27398 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Hug <philipp(a)hug.cx> Gerrit-Comment-Date: Fri, 13 Jul 2018 13:35:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.
by build bot (Jenkins) (Code Review) 13 Jul '18

13 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27471 ) Change subject: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??. ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c File src/soc/intel/braswell/ramstage.c: https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@90 PS1, Line 90: if (attrs->revid >= RID_D_STEPPING_START) { please, no spaces at the start of a line https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@90 PS1, Line 90: if (attrs->revid >= RID_D_STEPPING_START) { suspect code indent for conditional statements (4, 16) https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@93 PS1, Line 93: } else if (attrs->revid >= RID_C_STEPPING_START) { please, no spaces at the start of a line https://review.coreboot.org/#/c/27471/1/src/soc/intel/braswell/ramstage.c@93 PS1, Line 93: } else if (attrs->revid >= RID_C_STEPPING_START) { suspect code indent for conditional statements (4, 16) -- To view, visit https://review.coreboot.org/27471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Gerrit-Change-Number: 27471 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 07:54:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

← Newer
1
...
52
53
54
55
56
57
58
...
88
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2018