coreboot-gerrit July 2018

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Change in coreboot[master]: mediatek/mt8183: Add SPI support
by Tristan Hsieh (Code Review) 16 Jul '18

16 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27498 Change subject: mediatek/mt8183: Add SPI support ...................................................................... mediatek/mt8183: Add SPI support This patch implements SOC-specific code of mt8183 and link the common code to support SPI bus. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Signed-off-by: mengqi.zhang <mengqi.zhang(a)mediatek.com> Change-Id: I544e850299c74861313c2425721479fe5b91639e --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h M src/soc/mediatek/mt8183/include/soc/pll.h A src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 5 files changed, 176 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/27498/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 1ae534f..ca59d34 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -4,7 +4,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c mmu_operations.c bootblock-y += ../common/pll.c pll.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c @@ -12,7 +12,7 @@ bootblock-y += ../common/wdt.c verstage-y += ../common/gpio.c gpio.c -verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c verstage-y += ../common/wdt.c @@ -20,7 +20,7 @@ romstage-y += emi.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c -romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-y += ../common/wdt.c @@ -30,7 +30,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c ramstage-y += ../common/wdt.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d6f54cf..de7eb1f 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -31,6 +31,12 @@ GPT_BASE = IO_PHYS + 0x00008000, APMIXED_BASE = IO_PHYS + 0x0000C000, UART0_BASE = IO_PHYS + 0x01002000, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01014000, + SPI5_BASE = IO_PHYS + 0x01015000, IOCFG_RT_BASE = IO_PHYS + 0x01C50000, IOCFG_RM_BASE = IO_PHYS + 0x01D20000, IOCFG_RB_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index d1ceded..8c0d4e3 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -260,6 +260,13 @@ /* top_div rate */ enum { CLK26M_HZ = 26 * MHz, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, + MAINPLL_D5_D2_HZ = MAINPLL_D5_HZ / 2, +}; + +/* top_mux rate */ +enum { + SPI_HZ = MAINPLL_D5_D2_HZ, }; #endif /* SOC_MEDIATEK_MT8183_PLL_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h new file mode 100644 index 0000000..66f46d1 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_MT8183_SPI_H +#define MTK_MT8183_SPI_H + +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 6 + +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); + +/* SPI_CFG0_REG */ +enum { + SPI_CFG0_CS_HOLD_SHIFT = 0, + SPI_CFG0_CS_SETUP_SHIFT = 16, +}; + +/*SPI_CFG2_REG*/ +enum { + SPI_CFG2_SCK_LOW_SHIFT = 0, + SPI_CFG2_SCK_HIGH_SHIFT = 16, +}; + + +#endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index d85138c..9acc4d7 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -13,16 +13,116 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <assert.h> +#include <spi_flash.h> +#include <soc/addressmap.h> #include <soc/flash_controller.h> -#include <spi-generic.h> +#include <soc/gpio.h> +#include <soc/spi.h> -static const struct spi_ctrlr spi_flash_ctrlr = { - .max_xfer_size = 65535, +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + }, + { + .regs = (void *)SPI1_BASE, + }, + { + .regs = (void *)SPI2_BASE, + }, + { + .regs = (void *)SPI3_BASE, + }, + { + .regs = (void *)SPI4_BASE, + }, + { + .regs = (void *)SPI5_BASE, + } }; +void mtk_spi_set_gpio_pinmux(unsigned int bus, + enum spi_pad_mask pad_select) +{ + /* TODO: implement support for other pads when needed */ + if (bus == 0) { + if (pad_select == SPI_PAD0_MASK) { + gpio_set_mode(PAD_SPI_MI, PAD_SPI_MI_FUNC_SPI0_MI); + gpio_set_mode(PAD_SPI_CSB, PAD_SPI_CSB_FUNC_SPI0_CSB); + gpio_set_mode(PAD_SPI_MO, PAD_SPI_MO_FUNC_SPI0_MO); + gpio_set_mode(PAD_SPI_CLK, PAD_SPI_CLK_FUNC_SPI0_CLK); + } + } + if (bus == 1) { + if (pad_select == SPI_PAD0_MASK) { + gpio_set_mode(PAD_SPI1_MI, PAD_SPI1_MI_FUNC_SPI1_A_MI); + gpio_set_mode(PAD_SPI1_CSB, + PAD_SPI1_CSB_FUNC_SPI1_A_CSB); + gpio_set_mode(PAD_SPI1_MO, PAD_SPI1_MO_FUNC_SPI1_A_MO); + gpio_set_mode(PAD_SPI1_CLK, + PAD_SPI1_CLK_FUNC_SPI1_A_CLK); + } + if (pad_select == SPI_PAD1_MASK) { + gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SPI1_B_MI); + gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SPI1_B_CSB); + gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SPI1_B_MO); + gpio_set_mode(PAD_EINT10, PAD_EINT10_FUNC_SPI1_B_CLK); + } + } + if (bus == 2) { + if (pad_select == SPI_PAD0_MASK) { + gpio_set_mode(PAD_KPCOL1, PAD_KPCOL1_FUNC_SPI2_MI); + gpio_set_mode(PAD_EINT0, PAD_EINT0_FUNC_SPI2_CSB); + gpio_set_mode(PAD_EINT1, PAD_EINT1_FUNC_SPI2_MO); + gpio_set_mode(PAD_EINT2, PAD_EINT2_FUNC_SPI2_CLK); + } + } + if (bus == 3) { + if (pad_select == SPI_PAD0_MASK) { + gpio_set_mode(PAD_DPI_D8, PAD_DPI_D8_FUNC_SPI3_MI); + gpio_set_mode(PAD_DPI_D9, PAD_DPI_D9_FUNC_SPI3_CSB); + gpio_set_mode(PAD_DPI_D10, PAD_DPI_D10_FUNC_SPI3_MO); + gpio_set_mode(PAD_DPI_D11, PAD_DPI_D11_FUNC_SPI3_CLK); + } + } + if (bus == 4) { + if (pad_select == SPI_PAD0_MASK) { + gpio_set_mode(PAD_DPI_D4, PAD_DPI_D4_FUNC_SPI4_MI); + gpio_set_mode(PAD_DPI_D5, PAD_DPI_D5_FUNC_SPI4_CSB); + gpio_set_mode(PAD_DPI_D6, PAD_DPI_D6_FUNC_SPI4_MO); + gpio_set_mode(PAD_DPI_D7, PAD_DPI_D7_FUNC_SPI4_CLK); + } + } + if (bus == 5) { + if (pad_select == SPI_PAD0_MASK) { + gpio_set_mode(PAD_DPI_D0, PAD_DPI_D0_FUNC_SPI5_MI); + gpio_set_mode(PAD_DPI_D1, PAD_DPI_D1_FUNC_SPI5_CSB); + gpio_set_mode(PAD_DPI_D2, PAD_DPI_D2_FUNC_SPI5_MO); + gpio_set_mode(PAD_DPI_D3, PAD_DPI_D3_FUNC_SPI5_CLK); + } + } +} + +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +{ + write32(&regs->spi_cfg0_reg, + ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | + ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); + + write32(&regs->spi_cfg2_reg, + ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | + ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); + + clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); +} + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { - .ctrlr = &spi_flash_ctrlr, + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, }, }; -- To view, visit https://review.coreboot.org/27498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I544e850299c74861313c2425721479fe5b91639e Gerrit-Change-Number: 27498 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mediatek: Refactor SPI code among similar SOCs
by Tristan Hsieh (Code Review) 16 Jul '18

16 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27497 Change subject: mediatek: Refactor SPI code among similar SOCs ...................................................................... mediatek: Refactor SPI code among similar SOCs Refactor SPI code which will be reused amon similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: If5a6c554dc8361e729cf5c464325b97b2bfb7098 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/include/soc/spi_common.h A src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c 5 files changed, 381 insertions(+), 333 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27497/1 diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h new file mode 100644 index 0000000..0b0ea1f --- /dev/null +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_COMMON_SPI_H +#define MTK_COMMON_SPI_H + +#include <spi-generic.h> + +/*SPI_CFG1_REG*/ +enum { + SPI_CFG1_CS_IDLE_SHIFT = 0, + SPI_CFG1_PACKET_LOOP_SHIFT = 8, + SPI_CFG1_PACKET_LENGTH_SHIFT = 16, + + SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, + SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, + SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, +}; + +enum { + SPI_CMD_ACT_SHIFT = 0, + SPI_CMD_RESUME_SHIFT = 1, + SPI_CMD_RST_SHIFT = 2, + SPI_CMD_PAUSE_EN_SHIFT = 4, + SPI_CMD_DEASSERT_SHIFT = 5, + SPI_CMD_CPHA_SHIFT = 8, + SPI_CMD_CPOL_SHIFT = 9, + SPI_CMD_RX_DMA_SHIFT = 10, + SPI_CMD_TX_DMA_SHIFT = 11, + SPI_CMD_TXMSBF_SHIFT = 12, + SPI_CMD_RXMSBF_SHIFT = 13, + SPI_CMD_RX_ENDIAN_SHIFT = 14, + SPI_CMD_TX_ENDIAN_SHIFT = 15, + SPI_CMD_FINISH_IE_SHIFT = 16, + SPI_CMD_PAUSE_IE_SHIFT = 17, + + SPI_CMD_ACT_EN = BIT(SPI_CMD_ACT_SHIFT), + SPI_CMD_RESUME_EN = BIT(SPI_CMD_RESUME_SHIFT), + SPI_CMD_RST_EN = BIT(SPI_CMD_RST_SHIFT), + SPI_CMD_PAUSE_EN = BIT(SPI_CMD_PAUSE_EN_SHIFT), + SPI_CMD_DEASSERT_EN = BIT(SPI_CMD_DEASSERT_SHIFT), + SPI_CMD_CPHA_EN = BIT(SPI_CMD_CPHA_SHIFT), + SPI_CMD_CPOL_EN = BIT(SPI_CMD_CPOL_SHIFT), + SPI_CMD_RX_DMA_EN = BIT(SPI_CMD_RX_DMA_SHIFT), + SPI_CMD_TX_DMA_EN = BIT(SPI_CMD_TX_DMA_SHIFT), + SPI_CMD_TXMSBF_EN = BIT(SPI_CMD_TXMSBF_SHIFT), + SPI_CMD_RXMSBF_EN = BIT(SPI_CMD_RXMSBF_SHIFT), + SPI_CMD_RX_ENDIAN_EN = BIT(SPI_CMD_RX_ENDIAN_SHIFT), + SPI_CMD_TX_ENDIAN_EN = BIT(SPI_CMD_TX_ENDIAN_SHIFT), + SPI_CMD_FINISH_IE_EN = BIT(SPI_CMD_FINISH_IE_SHIFT), + SPI_CMD_PAUSE_IE_EN = BIT(SPI_CMD_PAUSE_IE_SHIFT), +}; + +enum spi_pad_mask { + SPI_PAD0_MASK = 0x0, + SPI_PAD1_MASK = 0x1, + SPI_PAD2_MASK = 0x2, + SPI_PAD3_MASK = 0x3, + SPI_PAD_SEL_MASK = 0x3 +}; + +struct mtk_spi_regs; + +struct mtk_spi_bus { + struct spi_slave slave; + struct mtk_spi_regs *regs; + int initialized; + int state; +}; + +extern const struct spi_ctrlr spi_ctrlr; +extern struct mtk_spi_bus spi_bus[]; + +void mtk_spi_set_gpio_pinmux(unsigned int bus, + enum spi_pad_mask pad_select); +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks); +void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, + unsigned int speed_hz); + +#endif diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c new file mode 100644 index 0000000..9eaa376 --- /dev/null +++ b/src/soc/mediatek/common/spi.c @@ -0,0 +1,277 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <endian.h> +#include <stdlib.h> +#include <soc/pll.h> +#include <soc/spi.h> +#include <timer.h> + +enum { + MTK_FIFO_DEPTH = 32, + MTK_TXRX_TIMEOUT_US = 1000 * 1000, + MTK_ARBITRARY_VALUE = 0xdeaddead +}; + +enum { + MTK_SPI_IDLE = 0, + MTK_SPI_PAUSE_IDLE = 1 +}; + +enum { + MTK_SPI_BUSY_STATUS = 1, + MTK_SPI_PAUSE_FINISH_INT_STATUS = 3 +}; + +static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave) +{ + assert(slave->bus < SPI_BUS_NUMBER); + return &spi_bus[slave->bus]; +} + +static void spi_sw_reset(struct mtk_spi_regs *regs) +{ + setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); + clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); +} + +void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, + unsigned int speed_hz) +{ + u32 div, sck_ticks, cs_ticks, reg_val; + + if (bus >= SPI_BUS_NUMBER) + die("Error: Invalid SPI bus.\n"); + + struct mtk_spi_bus *slave = &spi_bus[bus]; + struct mtk_spi_regs *regs = slave->regs; + + if (speed_hz < SPI_HZ / 2) + div = div_round_up(SPI_HZ, speed_hz); + else + div = 1; + + sck_ticks = div_round_up(div, 2); + cs_ticks = sck_ticks * 2; + + printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n", + bus, pad_select, SPI_HZ / (sck_ticks * 2)); + + /* set the timing */ + mtk_spi_set_timing(regs, sck_ticks, cs_ticks); + + reg_val = read32(&regs->spi_cmd_reg); + + reg_val &= ~SPI_CMD_CPHA_EN; + reg_val &= ~SPI_CMD_CPOL_EN; + + /* set the mlsbx and mlsbtx */ + reg_val |= SPI_CMD_TXMSBF_EN; + reg_val |= SPI_CMD_RXMSBF_EN; + + /* set the tx/rx endian */ +#ifdef __LITTLE_ENDIAN + reg_val &= ~SPI_CMD_TX_ENDIAN_EN; + reg_val &= ~SPI_CMD_RX_ENDIAN_EN; +#else + reg_val |= SPI_CMD_TX_ENDIAN_EN; + reg_val |= SPI_CMD_RX_ENDIAN_EN; +#endif + + /* clear pause mode */ + reg_val &= ~SPI_CMD_PAUSE_EN; + + /* set finish interrupt always enable */ + reg_val |= SPI_CMD_FINISH_IE_EN; + + /* set pause interrupt always enable */ + reg_val |= SPI_CMD_PAUSE_IE_EN; + + /* disable dma mode */ + reg_val &= ~(SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN); + + /* set deassert mode */ + reg_val &= ~SPI_CMD_DEASSERT_EN; + + write32(&regs->spi_cmd_reg, reg_val); + + mtk_spi_set_gpio_pinmux(bus, pad_select); + /* pad select */ + clrsetbits_le32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, + pad_select); +} + +static void mtk_spi_dump_data(const char *name, const uint8_t *data, int size) +{ +#ifdef MTK_SPI_DEBUG + int i; + + printk(BIOS_DEBUG, "%s: 0x ", name); + for (i = 0; i < size; i++) + printk(BIOS_INFO, "%#x ", data[i]); + printk(BIOS_DEBUG, "\n"); +#endif +} + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); + struct mtk_spi_regs *regs = mtk_slave->regs; + + setbits_le32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); + mtk_slave->state = MTK_SPI_IDLE; + + return 0; +} + +static int mtk_spi_fifo_transfer(const struct spi_slave *slave, void *in, + const void *out, size_t size) +{ + struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); + struct mtk_spi_regs *regs = mtk_slave->regs; + uint8_t *inb = (uint8_t *)in; + const uint32_t *outb = (const uint32_t *)out; + uint32_t reg_val = 0; + uint32_t i, word_count; + struct stopwatch sw; + + if (!size || size > MTK_FIFO_DEPTH) + return -1; + + clrsetbits_le32(&regs->spi_cfg1_reg, + SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, + ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | + (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + + word_count = div_round_up(size, sizeof(u32)); + + if (outb) { + for (i = 0; i < word_count; i++) + write32(&regs->spi_tx_data_reg, outb[i]); + mtk_spi_dump_data("the outb data is", + (const uint8_t *)outb, size); + } else { + /* The SPI controller will transmit in full-duplex for RX, + * therefore we need arbitrary data on MOSI which the slave + * must ignore. + */ + for (i = 0; i < word_count; i++) + write32(&regs->spi_tx_data_reg, MTK_ARBITRARY_VALUE); + } + + if (mtk_slave->state == MTK_SPI_IDLE) { + setbits_le32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN); + mtk_slave->state = MTK_SPI_PAUSE_IDLE; + } else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) { + setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN); + } + + stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); + while ((read32(&regs->spi_status1_reg) & MTK_SPI_BUSY_STATUS) == 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "Timeout waiting for status1 status.\n"); + goto error; + } + } + stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); + while ((read32(&regs->spi_status0_reg) & + MTK_SPI_PAUSE_FINISH_INT_STATUS) == 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "Timeout waiting for status0 status.\n"); + goto error; + } + } + + if (inb) { + for (i = 0; i < size; i++) { + if (i % 4 == 0) + reg_val = read32(&regs->spi_rx_data_reg); + *(inb + i) = (reg_val >> ((i % 4) * 8)) & 0xff; + } + mtk_spi_dump_data("the inb data is", inb, size); + } + + return 0; +error: + spi_sw_reset(regs); + mtk_slave->state = MTK_SPI_IDLE; + return -1; +} + +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + size_t min_size = 0; + int ret; + + /* Driver implementation does not support full duplex. */ + if ((bytes_in && bytes_out) && (bytes_in != bytes_out)) + return -1; + + while (bytes_out || bytes_in) { + if (bytes_in && bytes_out) + min_size = MIN(bytes_out, MTK_FIFO_DEPTH); + else if (bytes_out) + min_size = MIN(bytes_out, MTK_FIFO_DEPTH); + else if (bytes_in) + min_size = MIN(bytes_in, MTK_FIFO_DEPTH); + + ret = mtk_spi_fifo_transfer(slave, din, dout, min_size); + if (ret != 0) + return ret; + + if (bytes_out) { + bytes_out -= min_size; + dout = (const uint8_t *)dout + min_size; + } + + if (bytes_in) { + bytes_in -= min_size; + din = (uint8_t *)din + min_size; + } + } + + return 0; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); + struct mtk_spi_regs *regs = mtk_slave->regs; + + clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN); + spi_sw_reset(regs); + mtk_slave->state = MTK_SPI_IDLE; +} + +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct mtk_spi_bus *eslave = to_mtk_spi(slave); + assert(read32(&eslave->regs->spi_cfg0_reg) != 0); + spi_sw_reset(eslave->regs); + return 0; +} + +const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .max_xfer_size = 65535, +}; diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 1a5ee80..2aa7b8d 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -19,7 +19,7 @@ bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-y += i2c.c bootblock-y += ../common/pll.c pll.c -bootblock-y += spi.c +bootblock-y += ../common/spi.c spi.c bootblock-y += ../common/timer.c bootblock-y += timer.c @@ -34,7 +34,7 @@ ################################################################################ verstage-y += i2c.c -verstage-y += spi.c +verstage-y += ../common/spi.c spi.c verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c @@ -53,8 +53,8 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-y += ../common/cbmem.c -romstage-y += spi.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/spi.c spi.c romstage-y += pmic_wrap.c mt6391.c romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c @@ -64,7 +64,7 @@ ################################################################################ ramstage-y += ../common/cbmem.c emi.c -ramstage-y += spi.c +ramstage-y += ../common/spi.c spi.c ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c ../common/mtcmos.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index 52f4f4c..eebadb4 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -16,8 +16,9 @@ #ifndef MTK_MT8173_SPI_H #define MTK_MT8173_SPI_H -#include <spi-generic.h> -#include <types.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 1 /* SPI peripheral register map. */ typedef struct mtk_spi_regs { @@ -43,67 +44,4 @@ SPI_CFG0_CS_SETUP_SHIFT = 24, }; -/*SPI_CFG1_REG*/ -enum { - SPI_CFG1_CS_IDLE_SHIFT = 0, - SPI_CFG1_PACKET_LOOP_SHIFT = 8, - SPI_CFG1_PACKET_LENGTH_SHIFT = 16, - - SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, - SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, - SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, -}; - -enum { - SPI_CMD_ACT_SHIFT = 0, - SPI_CMD_RESUME_SHIFT = 1, - SPI_CMD_RST_SHIFT = 2, - SPI_CMD_PAUSE_EN_SHIFT = 4, - SPI_CMD_DEASSERT_SHIFT = 5, - SPI_CMD_CPHA_SHIFT = 8, - SPI_CMD_CPOL_SHIFT = 9, - SPI_CMD_RX_DMA_SHIFT = 10, - SPI_CMD_TX_DMA_SHIFT = 11, - SPI_CMD_TXMSBF_SHIFT = 12, - SPI_CMD_RXMSBF_SHIFT = 13, - SPI_CMD_RX_ENDIAN_SHIFT = 14, - SPI_CMD_TX_ENDIAN_SHIFT = 15, - SPI_CMD_FINISH_IE_SHIFT = 16, - SPI_CMD_PAUSE_IE_SHIFT = 17, - - SPI_CMD_ACT_EN = BIT(SPI_CMD_ACT_SHIFT), - SPI_CMD_RESUME_EN = BIT(SPI_CMD_RESUME_SHIFT), - SPI_CMD_RST_EN = BIT(SPI_CMD_RST_SHIFT), - SPI_CMD_PAUSE_EN = BIT(SPI_CMD_PAUSE_EN_SHIFT), - SPI_CMD_DEASSERT_EN = BIT(SPI_CMD_DEASSERT_SHIFT), - SPI_CMD_CPHA_EN = BIT(SPI_CMD_CPHA_SHIFT), - SPI_CMD_CPOL_EN = BIT(SPI_CMD_CPOL_SHIFT), - SPI_CMD_RX_DMA_EN = BIT(SPI_CMD_RX_DMA_SHIFT), - SPI_CMD_TX_DMA_EN = BIT(SPI_CMD_TX_DMA_SHIFT), - SPI_CMD_TXMSBF_EN = BIT(SPI_CMD_TXMSBF_SHIFT), - SPI_CMD_RXMSBF_EN = BIT(SPI_CMD_RXMSBF_SHIFT), - SPI_CMD_RX_ENDIAN_EN = BIT(SPI_CMD_RX_ENDIAN_SHIFT), - SPI_CMD_TX_ENDIAN_EN = BIT(SPI_CMD_TX_ENDIAN_SHIFT), - SPI_CMD_FINISH_IE_EN = BIT(SPI_CMD_FINISH_IE_SHIFT), - SPI_CMD_PAUSE_IE_EN = BIT(SPI_CMD_PAUSE_IE_SHIFT), -}; - -enum spi_pad_mask { - SPI_PAD0_MASK = 0x0, - SPI_PAD1_MASK = 0x1, - SPI_PAD2_MASK = 0x2, - SPI_PAD3_MASK = 0x3, - SPI_PAD_SEL_MASK = 0x3 -}; - - -struct mtk_spi_bus { - struct spi_slave slave; - struct mtk_spi_regs *regs; - int initialized; - int state; -}; - -void mtk_spi_init(unsigned int bus, unsigned int pad_select, - unsigned int speed_hz); #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 634c46e..669ecf0 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -15,55 +15,20 @@ #include <arch/io.h> #include <assert.h> -#include <console/console.h> -#include <delay.h> -#include <endian.h> #include <spi_flash.h> -#include <stdlib.h> -#include <string.h> -#include <timer.h> #include <soc/addressmap.h> #include <soc/flash_controller.h> #include <soc/gpio.h> -#include <soc/pll.h> #include <soc/spi.h> -enum { - MTK_FIFO_DEPTH = 32, - MTK_TXRX_TIMEOUT_US = 1000 * 1000, - MTK_ARBITRARY_VALUE = 0xdeaddead -}; - -enum { - MTK_SPI_IDLE = 0, - MTK_SPI_PAUSE_IDLE = 1 -}; - -enum { - MTK_SPI_BUSY_STATUS = 1, - MTK_SPI_PAUSE_FINISH_INT_STATUS = 3 -}; - -static struct mtk_spi_bus spi_bus[1] = { +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { { .regs = (void *)SPI_BASE, - .state = MTK_SPI_IDLE, } }; -static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave) -{ - assert(slave->bus < ARRAY_SIZE(spi_bus)); - return &spi_bus[slave->bus]; -} - -static void spi_sw_reset(struct mtk_spi_regs *regs) -{ - setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); - clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); -} - -static void mtk_spi_set_gpio_pinmux(enum spi_pad_mask pad_select) +void mtk_spi_set_gpio_pinmux(unsigned int bus, + enum spi_pad_mask pad_select) { /* TODO: implement support for other pads when needed */ assert(pad_select == SPI_PAD1_MASK); @@ -73,30 +38,8 @@ gpio_set_mode(PAD_MSDC2_CMD, PAD_MSDC2_CMD_FUNC_SPI_CS_1); } -void mtk_spi_init(unsigned int bus, unsigned int pad_select, - unsigned int speed_hz) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) { - u32 div, sck_ticks, cs_ticks, reg_val; - - /* mtk spi HW just supports bus 0 */ - if (bus != 0) - die("Error: Only SPI bus 0 is supported.\n"); - - struct mtk_spi_bus *slave = &spi_bus[bus]; - struct mtk_spi_regs *regs = slave->regs; - - if (speed_hz < SPI_HZ / 2) - div = div_round_up(SPI_HZ, speed_hz); - else - div = 1; - - sck_ticks = div_round_up(div, 2); - cs_ticks = sck_ticks * 2; - - printk(BIOS_DEBUG, "SPI%u initialized at %u Hz", - pad_select, SPI_HZ / (sck_ticks * 2)); - - /* set the timing */ write32(&regs->spi_cfg0_reg, ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | @@ -104,200 +47,6 @@ ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); - - reg_val = read32(&regs->spi_cmd_reg); - - reg_val &= ~SPI_CMD_CPHA_EN; - reg_val &= ~SPI_CMD_CPOL_EN; - - /* set the mlsbx and mlsbtx */ - reg_val |= SPI_CMD_TXMSBF_EN; - reg_val |= SPI_CMD_RXMSBF_EN; - - /* set the tx/rx endian */ -#ifdef __LITTLE_ENDIAN - reg_val &= ~SPI_CMD_TX_ENDIAN_EN; - reg_val &= ~SPI_CMD_RX_ENDIAN_EN; -#else - reg_val |= SPI_CMD_TX_ENDIAN_EN; - reg_val |= SPI_CMD_RX_ENDIAN_EN; -#endif - - /* clear pause mode */ - reg_val &= ~SPI_CMD_PAUSE_EN; - - /* set finish interrupt always enable */ - reg_val |= SPI_CMD_FINISH_IE_EN; - - /* set pause interrupt always enable */ - reg_val |= SPI_CMD_PAUSE_IE_EN; - - /* disable dma mode */ - reg_val &= ~(SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN); - - /* set deassert mode */ - reg_val &= ~SPI_CMD_DEASSERT_EN; - - write32(&regs->spi_cmd_reg, reg_val); - - mtk_spi_set_gpio_pinmux(pad_select); - /* pad select */ - clrsetbits_le32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, - pad_select); -} - -static void mtk_spi_dump_data(const char *name, const uint8_t *data, - int size) -{ -#ifdef MTK_SPI_DEBUG - int i; - - printk(BIOS_DEBUG, "%s: 0x ", name); - for (i = 0; i < size; i++) - printk(BIOS_INFO, "%#x ", data[i]); - printk(BIOS_DEBUG, "\n"); -#endif -} - -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); - struct mtk_spi_regs *regs = mtk_slave->regs; - - setbits_le32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); - mtk_slave->state = MTK_SPI_IDLE; - - return 0; -} - -static int mtk_spi_fifo_transfer(const struct spi_slave *slave, void *in, - const void *out, size_t size) -{ - struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); - struct mtk_spi_regs *regs = mtk_slave->regs; - uint8_t *inb = (uint8_t *)in; - const uint32_t *outb = (const uint32_t *)out; - uint32_t reg_val = 0; - uint32_t i, word_count; - struct stopwatch sw; - - if (!size || size > MTK_FIFO_DEPTH) - return -1; - - clrsetbits_le32(&regs->spi_cfg1_reg, - SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, - ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | - (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); - - word_count = div_round_up(size, sizeof(u32)); - if (inb) { - /* The SPI controller will transmit in full-duplex for RX, - * therefore we need arbitrary data on MOSI which the slave - * must ignore. - */ - for (i = 0; i < word_count; i++) - write32(&regs->spi_tx_data_reg, MTK_ARBITRARY_VALUE); - } - if (outb) { - for (i = 0; i < word_count; i++) - write32(&regs->spi_tx_data_reg, outb[i]); - mtk_spi_dump_data("the outb data is", - (const uint8_t *)outb, size); - } - - if (mtk_slave->state == MTK_SPI_IDLE) { - setbits_le32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN); - mtk_slave->state = MTK_SPI_PAUSE_IDLE; - } else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) { - setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN); - } - - stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); - while ((read32(&regs->spi_status1_reg) & MTK_SPI_BUSY_STATUS) == 0) { - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, - "Timeout waiting for status1 status.\n"); - goto error; - } - } - stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); - while ((read32(&regs->spi_status0_reg) & - MTK_SPI_PAUSE_FINISH_INT_STATUS) == 0) { - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, - "Timeout waiting for status0 status.\n"); - goto error; - } - } - - if (inb) { - for (i = 0; i < size; i++) { - if (i % 4 == 0) - reg_val = read32(&regs->spi_rx_data_reg); - *(inb + i) = (reg_val >> ((i % 4) * 8)) & 0xff; - } - mtk_spi_dump_data("the inb data is", inb, size); - } - - return 0; -error: - spi_sw_reset(regs); - mtk_slave->state = MTK_SPI_IDLE; - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) -{ - size_t min_size = 0; - int ret; - - /* Driver implementation does not support full duplex. */ - if (bytes_in && bytes_out) - return -1; - - while (bytes_out || bytes_in) { - if (bytes_in && bytes_out) - min_size = MIN(MIN(bytes_out, bytes_in), MTK_FIFO_DEPTH); - else if (bytes_out) - min_size = MIN(bytes_out, MTK_FIFO_DEPTH); - else if (bytes_in) - min_size = MIN(bytes_in, MTK_FIFO_DEPTH); - - ret = mtk_spi_fifo_transfer(slave, din, dout, min_size); - if (ret != 0) - return ret; - - if (bytes_out) { - bytes_out -= min_size; - dout = (const uint8_t *)dout + min_size; - } - - if (bytes_in) { - bytes_in -= min_size; - din = (uint8_t *)din + min_size; - } - } - - return 0; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); - struct mtk_spi_regs *regs = mtk_slave->regs; - - clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN); - spi_sw_reset(regs); - mtk_slave->state = MTK_SPI_IDLE; -} - -static int spi_ctrlr_setup(const struct spi_slave *slave) -{ - struct mtk_spi_bus *eslave = to_mtk_spi(slave); - assert(read32(&eslave->regs->spi_cfg0_reg) != 0); - spi_sw_reset(eslave->regs); - return 0; } static const struct spi_ctrlr spi_flash_ctrlr = { @@ -305,19 +54,11 @@ .flash_probe = mtk_spi_flash_probe, }; -static const struct spi_ctrlr spi_ctrlr = { - .setup = spi_ctrlr_setup, - .claim_bus = spi_ctrlr_claim_bus, - .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .max_xfer_size = 65535, -}; - const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, .bus_start = 0, - .bus_end = 0, + .bus_end = SPI_BUS_NUMBER - 1, }, { .ctrlr = &spi_flash_ctrlr, -- To view, visit https://review.coreboot.org/27497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If5a6c554dc8361e729cf5c464325b97b2bfb7098 Gerrit-Change-Number: 27497 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: [WIP]mb/facebook/satima: Add new port
by build bot (Jenkins) (Code Review) 16 Jul '18

16 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27425 ) Change subject: [WIP]mb/facebook/satima: Add new port ...................................................................... Patch Set 5: (174 comments) https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… File src/mainboard/opencellular/satima/cn81xx-linux.dtsi: https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 46: compatible = "cavium,thunder-81xx"; DT compatible string "cavium,thunder-81xx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 46: compatible = "cavium,thunder-81xx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 52: compatible = "arm,psci-0.2"; DT compatible string "arm,psci-0.2" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 52: compatible = "arm,psci-0.2"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 113: compatible = "cache"; DT compatible string "cache" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 118: compatible = "arm,armv8-timer"; DT compatible string "arm,armv8-timer" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 118: compatible = "arm,armv8-timer"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string "cavium,thunder-pmu" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string "arm,armv8-pmuv3" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 131: compatible = "regulator-fixed"; DT compatible string "regulator-fixed" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 141: compatible = "arm,gic-v3"; DT compatible string "arm,gic-v3" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 141: compatible = "arm,gic-v3"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 153: compatible = "arm,gic-v3-its"; DT compatible string "arm,gic-v3-its" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 153: compatible = "arm,gic-v3-its"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 161: compatible = "simple-bus"; DT compatible string "simple-bus" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 168: compatible = "fixed-clock"; DT compatible string "fixed-clock" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 175: compatible = "fixed-clock"; DT compatible string "fixed-clock" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 218: compatible = "arm,sbsa-gwdt"; DT compatible string "arm,sbsa-gwdt" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 218: compatible = "arm,sbsa-gwdt"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 219: reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 224: compatible = "cfi-flash"; DT compatible string "cfi-flash" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 232: compatible = "cavium,smmu-v2"; DT compatible string "cavium,smmu-v2" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 232: compatible = "cavium,smmu-v2"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 235: interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 236: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 237: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 238: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 239: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 240: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 241: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 242: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 243: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 244: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 245: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 255: compatible = "pci-host-ecam-generic"; DT compatible string "pci-host-ecam-generic" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 265: reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 266: ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 267: <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 268: <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 269: <0x03000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x000 0x94000000>, /* PEMs */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 270: <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 271: <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 272: <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; DT compatible string "pci-bridge" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; DT compatible string "cavium,thunder-8890-mrml-bridge" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 278: ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 284: compatible = "cavium,thunder-8890-mdio-nexus"; DT compatible string "cavium,thunder-8890-mdio-nexus" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 284: compatible = "cavium,thunder-8890-mdio-nexus"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 284: compatible = "cavium,thunder-8890-mdio-nexus"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 287: reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 288: assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 289: ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 291: compatible = "cavium,thunder-8890-mdio"; DT compatible string "cavium,thunder-8890-mdio" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 291: compatible = "cavium,thunder-8890-mdio"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 291: compatible = "cavium,thunder-8890-mdio"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 294: reg = <0x87e0 0x05003800 0x0 0x30>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 297: compatible = "cavium,thunder-8890-mdio"; DT compatible string "cavium,thunder-8890-mdio" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 297: compatible = "cavium,thunder-8890-mdio"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 297: compatible = "cavium,thunder-8890-mdio"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 300: reg = <0x87e0 0x05003880 0x0 0x30>; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 305: compatible = "cavium,thunder-8890-mmc"; DT compatible string "cavium,thunder-8890-mmc" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 305: compatible = "cavium,thunder-8890-mmc"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 306: reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 315: compatible = "cavium,thunder-8890-twsi"; DT compatible string "cavium,thunder-8890-twsi" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 315: compatible = "cavium,thunder-8890-twsi"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 316: reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 325: compatible = "cavium,thunder-8890-twsi"; DT compatible string "cavium,thunder-8890-twsi" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 325: compatible = "cavium,thunder-8890-twsi"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 326: reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 335: compatible = "cavium,thunder-8890-bgx"; DT compatible string "cavium,thunder-8890-bgx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 335: compatible = "cavium,thunder-8890-bgx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 336: reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 341: compatible = "cavium,thunder-8890-bgx"; DT compatible string "cavium,thunder-8890-bgx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 341: compatible = "cavium,thunder-8890-bgx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 342: reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 347: compatible = "cavium,thunder-8890-bgx"; DT compatible string "cavium,thunder-8890-bgx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 347: compatible = "cavium,thunder-8890-bgx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 348: reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 353: compatible = "cavium,thunder-8190-spi"; DT compatible string "cavium,thunder-8190-spi" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 353: compatible = "cavium,thunder-8190-spi"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 354: reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 362: compatible = "cavium,thunder-8890-gpio"; DT compatible string "cavium,thunder-8890-gpio" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 362: compatible = "cavium,thunder-8890-gpio"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 364: reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 371: compatible = "cavium,cn8130-nand"; DT compatible string "cavium,cn8130-nand" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 371: compatible = "cavium,cn8130-nand"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 392: compatible = "cavium,pci-host-thunder-pem"; DT compatible string "cavium,pci-host-thunder-pem" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 392: compatible = "cavium,pci-host-thunder-pem"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 401: reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 402: <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 403: ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 404: <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 405: <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 406: <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 417: compatible = "cavium,pci-host-thunder-pem"; DT compatible string "cavium,pci-host-thunder-pem" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 417: compatible = "cavium,pci-host-thunder-pem"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 426: reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 427: <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 428: ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 429: <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 430: <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 431: <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 442: compatible = "cavium,pci-host-thunder-pem"; DT compatible string "cavium,pci-host-thunder-pem" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 442: compatible = "cavium,pci-host-thunder-pem"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 451: reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 452: <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 453: ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 454: <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 455: <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 456: <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 469: compatible = "cavium,thunder-8190-tdm"; DT compatible string "cavium,thunder-8190-tdm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/c… PS5, Line 469: compatible = "cavium,thunder-8190-tdm"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/d… File src/mainboard/opencellular/satima/death.c: https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/d… PS5, Line 31: } while(1); space required before the open parenthesis '(' https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/m… File src/mainboard/opencellular/satima/mainboard.h: https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/m… PS5, Line 18: #define SATIMA_GPIO_SPI_MUX 24 please, no space before tabs https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… File src/mainboard/opencellular/satima/sff8104-linux.dts: https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; DT compatible string "marvell,88e1510" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; DT compatible string vendor "marvell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; DT compatible string "ethernet-phy-ieee802.3-c22" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; DT compatible string "vitesse,vsc8574" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; DT compatible string vendor "vitesse" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; DT compatible string "ethernet-phy-ieee802.3-c22" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; DT compatible string "aquantia,aqr105" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; DT compatible string vendor "aquantia" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; DT compatible string "ethernet-phy-ieee802.3-c45" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 98: compatible = "mmc-slot"; DT compatible string "mmc-slot" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 108: /* There is no card detection available; polling must be used. */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 117: compatible = "mmc-slot"; DT compatible string "mmc-slot" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 128: /* There is no card detection available; polling must be used. */ line over 80 characters https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string "micron,n25q128a13" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string vendor "micron" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string "spi-flash" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string "jedec,spi-nor" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string vendor "jedec" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 149: compatible = "spinand,mt29f", "mt29f"; DT compatible string "spinand,mt29f" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 149: compatible = "spinand,mt29f", "mt29f"; DT compatible string vendor "spinand" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/5/src/mainboard/opencellular/satima/s… PS5, Line 149: compatible = "spinand,mt29f", "mt29f"; DT compatible string "mt29f" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ -- To view, visit https://review.coreboot.org/27425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4f972d59ac2243823a77f614c4f92c1666185705 Gerrit-Change-Number: 27425 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 16 Jul 2018 11:08:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: google/grunt: update ACPI processor object
by Kevin Chiu (Code Review) 16 Jul '18

16 Jul '18

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27495 to look at the new patch set (#2). Change subject: google/grunt: update ACPI processor object ...................................................................... google/grunt: update ACPI processor object update processor object to match declaration in SSDT. BUG=b:111478152 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/soc/amd/stoneyridge/acpi/cpu.asl 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27495/2 -- To view, visit https://review.coreboot.org/27495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Gerrit-Change-Number: 27495 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: google/grunt: update ACPI processor object
by Kevin Chiu (Code Review) 16 Jul '18

16 Jul '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27495 Change subject: google/grunt: update ACPI processor object ...................................................................... google/grunt: update ACPI processor object update processor object to match declaration in SSDT. BUG=None BRANCH=master TEST=emerge-grunt coreboot Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/soc/amd/stoneyridge/acpi/cpu.asl 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27495/1 diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 5d29a55..414326e 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -22,14 +22,14 @@ * Processor Object */ /* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +External (\_PR.P000, DeviceObj) +External (\_PR.P001, DeviceObj) +External (\_PR.P002, DeviceObj) +External (\_PR.P003, DeviceObj) +External (\_PR.P004, DeviceObj) +External (\_PR.P005, DeviceObj) +External (\_PR.P006, DeviceObj) +External (\_PR.P007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) @@ -37,13 +37,13 @@ If (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.CP00, - \_PR.CP01 + \_PR.P000, + \_PR.P001 }) } Else { Return (Package () { - \_PR.CP00 + \_PR.P000 }) } } -- To view, visit https://review.coreboot.org/27495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Gerrit-Change-Number: 27495 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: util/docker: Update Makefile to improve shell access
by Martin Roth (Code Review) 15 Jul '18

15 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27494 Change subject: util/docker: Update Makefile to improve shell access ...................................................................... util/docker: Update Makefile to improve shell access - Create a new target, docker-jenkins-attach, to access the running jenkins server - Update docker-shell target to set term & size. Change-Id: Ifa67afb62d4a216281ebece405e9b26fd4d14622 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/docker/Makefile 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/27494/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index 8bec631..beb2a7e 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -150,11 +150,19 @@ docker-shell: USER=coreboot docker-shell: test-docker $(DOCKER) run -u $(USER) -it \ + -e COLUMNS=$(shell tput cols) -e LINES=$(shell tput lines) -e TERM=$(TERM) \ -w /home/coreboot/coreboot \ -v $(top):/home/coreboot/coreboot \ --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ /bin/bash -l +docker-jenkins-attach: USER=root +docker-jenkins-attach: + docker exec --user $(USER) \ + -e COLUMNS=$(shell tput cols) -e LINES=$(shell tput lines) -e TERM=$(TERM) \ + -it "$$(docker ps | grep coreboot-jenkins-node | cut -f1 -d' ')" \ + /bin/bash -l + help: @echo "Commands for working with docker images:" @echo " coreboot-sdk - Build coreboot-sdk container" @@ -174,6 +182,7 @@ @echo " docker-shell - Bash prompt in coreboot-jenkins-node" @echo " <USER=root or USER=coreboot>" @echo " docker-jenkins-server - Run coreboot-jenkins-node image (for server)" + @echo " docker-jenkins-attach - Open shell in running jenkins server" @echo @echo "Variables:" @echo " COREBOOT_JENKINS_PORT=$(COREBOOT_JENKINS_PORT)" @@ -187,5 +196,5 @@ .PHONY: coreboot-sdk upload-coreboot-sdk .PHONY: clean-coreboot-containers clean-coreboot-images .PHONY: docker-abuild -.PHONY: docker-what-jenkins-does docker-shell docker-jenkins-server +.PHONY: docker-what-jenkins-does docker-shell docker-jenkins-server docker-jenkins-attach .PHONY: help -- To view, visit https://review.coreboot.org/27494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa67afb62d4a216281ebece405e9b26fd4d14622 Gerrit-Change-Number: 27494 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: vendorcode/cavium/include: Make bdk_pop and dpop static
by Martin Roth (Code Review) 15 Jul '18

15 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27493 Change subject: vendorcode/cavium/include: Make bdk_pop and dpop static ...................................................................... vendorcode/cavium/include: Make bdk_pop and dpop static Fix an undefined reference error with GCC 8.1 /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk /libbdk-dram/bdk-dram-size.o: In function `bdk_dram_get_size_mbytes': /home/coreboot/slave-root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk /libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop' /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk /libbdk-dram/bdk-dram-test.o: In function `bdk_get_num_cores': /home/coreboot/slave- root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal /bdk-utils.h:164: undefined reference to `bdk_dpop' /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram /dram-init-ddr3.o: In function `init_octeon3_ddr3_interface': /home/coreboot/slave- root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk/libdram/dram-init- ddr3.c:7550: undefined reference to `bdk_pop' /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram /dram-l2c.o: In function `bdk_get_num_cores': /home/coreboot/slave- root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal /bdk-utils.h:164: undefined reference to `bdk_dpop' make[1]: *** [src/arch/arm64/Makefile.inc:119: /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/cbfs/fallback/romstage.debug] Error 1 Change-Id: Ifcde5476c6f347c0eac7ca44bac88d3fa4017fb7 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M src/vendorcode/cavium/include/bdk/bdk-coreboot.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/27493/1 diff --git a/src/vendorcode/cavium/include/bdk/bdk-coreboot.h b/src/vendorcode/cavium/include/bdk/bdk-coreboot.h index 7b417b6..85cf21a 100644 --- a/src/vendorcode/cavium/include/bdk/bdk-coreboot.h +++ b/src/vendorcode/cavium/include/bdk/bdk-coreboot.h @@ -139,7 +139,7 @@ * * @return Number of bits set */ -inline uint32_t bdk_pop(uint32_t v) +static inline uint32_t bdk_pop(uint32_t v) { /* Use parallel SWAR algorithm */ v = v - ((v >> 1) & 0x55555555); @@ -155,7 +155,7 @@ * * @return Number of bits set */ -inline int bdk_dpop(uint64_t val) +static inline int bdk_dpop(uint64_t val) { return bdk_pop(val & 0xffffffff) + bdk_pop(val >> 32); } -- To view, visit https://review.coreboot.org/27493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifcde5476c6f347c0eac7ca44bac88d3fa4017fb7 Gerrit-Change-Number: 27493 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: what-jenkins-does: Pass V=1 through to abuild
by Martin Roth (Code Review) 15 Jul '18

15 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27492 Change subject: what-jenkins-does: Pass V=1 through to abuild ...................................................................... what-jenkins-does: Pass V=1 through to abuild Even though we were setting V=1 in the build, this wasn't getting passed to abuild, so the builds there didn't have additional debug information. That made it difficult to debug issues on the builder. This sets the verbose flag for abuild if V=1 is set. Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/testing/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/27492/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index 839580e..595e8e3 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -84,8 +84,8 @@ what-jenkins-does: util/lint/lint lint-stable --junit util/lint/lint lint-extended --junit - util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml - util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) + util/abuild/abuild -B -J $(if $(V),-v,) $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml + util/abuild/abuild -B -J $(if $(V),-v,) $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) $(foreach tool, $(TOOLLIST), $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR="util/$(tool)" BLD="$(tool)" MFLAGS= MAKEFLAGS= MAKETARGET= junit.xml; ) unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml -- To view, visit https://review.coreboot.org/27492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549 Gerrit-Change-Number: 27492 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: nb/intel/gm45: Don't run the oprom when using libgfxinit
by Arthur Heymans (Code Review) 14 Jul '18

14 Jul '18

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/27490 ) Change subject: nb/intel/gm45: Don't run the oprom when using libgfxinit ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/27490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Id4bffe50186e5f84d035c2f3dc44fafbc9de6456 Gerrit-Change-Number: 27490 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/kahlee: Don't default backlight on
by Martin Roth (Code Review) 14 Jul '18

14 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27489 ) Change subject: mainboard/google/kahlee: Don't default backlight on ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1aba787734e2976146ecd305dd821f0b326f0db Gerrit-Change-Number: 27489 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 15 Jul 2018 00:49:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit July 2018