coreboot-gerrit July 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Add GPIO functions to SMM
by Marc Jones (Code Review) 14 Jul '18

14 Jul '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/27485 Change subject: soc/amd/stoneyridge: Add GPIO functions to SMM ...................................................................... soc/amd/stoneyridge: Add GPIO functions to SMM GPIO functions are required by the Grunt SMI handler. Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27485/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c2d48d5..5df4889 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -126,6 +126,7 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += nb_util.c +smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include -- To view, visit https://review.coreboot.org/27485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745 Gerrit-Change-Number: 27485 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Fix gpio_set function
by Marc Jones (Code Review) 14 Jul '18

14 Jul '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/27484 Change subject: soc/amd/stoneyridge: Fix gpio_set function ...................................................................... soc/amd/stoneyridge: Fix gpio_set function The gpio_set function was not writing the correct GPIO register address. Change-Id: Ib306773ac72505977b606836bbaf3e2067324894 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27484/1 diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 6513476..88e7d3b 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -162,7 +162,7 @@ reg = read32((void *)gpio_address); reg &= ~GPIO_OUTPUT_MASK; reg |= !!value << GPIO_OUTPUT_SHIFT; - write32((void *)(uintptr_t)gpio_num, reg); + write32((void *)(uintptr_t)gpio_address, reg); } void gpio_input_pulldown(gpio_t gpio_num) -- To view, visit https://review.coreboot.org/27484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib306773ac72505977b606836bbaf3e2067324894 Gerrit-Change-Number: 27484 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: sdm845: Add GPIO API
by build bot (Jenkins) (Code Review) 14 Jul '18

14 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26233 ) Change subject: sdm845: Add GPIO API ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/26233/8/src/soc/qualcomm/sdm845/include/soc… File src/soc/qualcomm/sdm845/include/soc/pinmux.h: https://review.coreboot.org/#/c/26233/8/src/soc/qualcomm/sdm845/include/soc… PS8, Line 24: #define PINMUX_CONSTANTS(index, tlmm, func1, func2, func3, \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/26233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8cef9dae2072da32cb0678efefeb8f0070cdde9c Gerrit-Change-Number: 26233 Gerrit-PatchSet: 8 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: David Dai <daidavid1(a)codeaurora.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 14 Jul 2018 20:28:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: gigabyte/ga-h61m-s2pv: Add VBT data
by Pablo Moyano (Code Review) 14 Jul '18

14 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27482 to look at the new patch set (#2). Change subject: gigabyte/ga-h61m-s2pv: Add VBT data ...................................................................... gigabyte/ga-h61m-s2pv: Add VBT data Extracted from the stock BIOS using UEFItool & intelvbttool. Without it, the kernel complains about the missing VBT table. Additionally, the invalid oprom signature warning given by i915 is also gone. Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844 Signed-off-by: Pablo Moyano <42.pablo.ms(a)gmail.com> --- A src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/27482/2 -- To view, visit https://review.coreboot.org/27482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844 Gerrit-Change-Number: 27482 Gerrit-PatchSet: 2 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Add VBT data for Gigabyte GA-H61-S2PV
by Pablo Moyano (Code Review) 14 Jul '18

14 Jul '18

Pablo Moyano has uploaded this change for review. ( https://review.coreboot.org/27482 Change subject: Add VBT data for Gigabyte GA-H61-S2PV ...................................................................... Add VBT data for Gigabyte GA-H61-S2PV Without it, the kernel complains about the missing VBT table. Extracted from the stock BIOS using UEFItool & intelvbttool. Additionally, the invalid oprom signature warning given by i915 is also gone. Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844 Signed-off-by: Pablo Moyano <42.pablo.ms(a)gmail.com> --- A src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/27482/1 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt b/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt new file mode 100644 index 0000000..3d230d9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/27482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844 Gerrit-Change-Number: 27482 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/x201: Fix EC SSDT
by Matthias Gazzari (Code Review) 14 Jul '18

14 Jul '18

Matthias Gazzari has posted comments on this change. ( https://review.coreboot.org/27481 ) Change subject: mb/lenovo/x201: Fix EC SSDT ...................................................................... Patch Set 1: Code-Review+1 fixed the ACPI issues -- To view, visit https://review.coreboot.org/27481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f Gerrit-Change-Number: 27481 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matthias Gazzari <mail(a)qtux.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Jul 2018 15:49:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/x201: Fix EC SSDT
by Arthur Heymans (Code Review) 14 Jul '18

14 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27481 ) Change subject: mb/lenovo/x201: Fix EC SSDT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f Gerrit-Change-Number: 27481 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matthias Gazzari <mail(a)qtux.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Jul 2018 15:04:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/x201: Fix EC SSDT
by Patrick Rudolph (Code Review) 14 Jul '18

14 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27481 Change subject: mb/lenovo/x201: Fix EC SSDT ...................................................................... mb/lenovo/x201: Fix EC SSDT Move the EC under the LPC PCI device to make sure that the SSDT path matches the DSDT. Matches the behaviour of all other Lenovo devices. Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/x201/devicetree.cb 1 file changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27481/1 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index a1746bd..fa33aeb 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -36,48 +36,6 @@ register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3c" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "48" - register "bdc_gpio_lvl" = "0" - end - device cpu_cluster 0 on chip cpu/intel/model_2065x device lapic 0 on end @@ -159,6 +117,48 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end + + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x01" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x80" + register "event7_enable" = "0x01" + register "event8_enable" = "0x01" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "48" + register "bdc_gpio_lvl" = "0" + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 -- To view, visit https://review.coreboot.org/27481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f Gerrit-Change-Number: 27481 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/google/octopus: Fix unused pins and those with external terminations
by build bot (Jenkins) (Code Review) 14 Jul '18

14 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27183 ) Change subject: mb/google/octopus: Fix unused pins and those with external terminations ...................................................................... Patch Set 4: (45 comments) https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 98: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 135: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 136: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 143: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 149: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 150: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 168: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 169: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 181: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 200: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 204: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 207: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 226: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RXDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 229: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 231: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 239: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 242: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 280: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 307: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 96: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 138: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 140: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 144: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 148: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 154: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 155: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 173: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 174: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 183: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 186: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 206: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 210: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 211: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 214: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 236: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 238: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 246: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 249: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 277: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 287: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27183/4/src/mainboard/google/octopus/varian… PS4, Line 314: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters -- To view, visit https://review.coreboot.org/27183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Gerrit-Change-Number: 27183 Gerrit-PatchSet: 4 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Jul 2018 06:50:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload/xhci: Check noop return code when debugging
by Julius Werner (Code Review) 13 Jul '18

13 Jul '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/27478 ) Change subject: libpayload/xhci: Check noop return code when debugging ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27478/1/payloads/libpayload/drivers/usb/xhc… File payloads/libpayload/drivers/usb/xhci.c: https://review.coreboot.org/#/c/27478/1/payloads/libpayload/drivers/usb/xhc… PS1, Line 411: fatal("noop command failed.\n"); I'm not sure die() is the right move here. This is just a debugging feature anyway, it shouldn't matter for production firmware. For debugging on early bring-up boards, I've seen plenty of cases where there was some kind of error here but the system was still usable afterwards (e.g. in case you didn't want to boot from USB, or if only one of several USB controllers was broken somehow). I'm fine with adding the condition code to the message if you want, but I don't think it should hang. -- To view, visit https://review.coreboot.org/27478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4 Gerrit-Change-Number: 27478 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 22:32:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit July 2018