coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/gma: Default to LVDS for Internal on NEHALEM
by Arthur Heymans (Code Review) 17 Jul '18

17 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27512 Change subject: drivers/intel/gma: Default to LVDS for Internal on NEHALEM ...................................................................... drivers/intel/gma: Default to LVDS for Internal on NEHALEM Devices using NORTHBRIDGE_INTEL_NEHALEM have an ironlake IGD which does not support eDP, therefore default to LVDS. Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/gma/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27512/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 1b9c2a6..10ccf71 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -95,7 +95,7 @@ config GFX_GMA_INTERNAL_IS_LVDS bool - default y if NORTHBRIDGE_INTEL_GM45 + default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM default n config GFX_GMA_INTERNAL_PORT -- To view, visit https://review.coreboot.org/27512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af Gerrit-Change-Number: 27512 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: security/vboot: Add interface for FSP 2.0 mrc caching
by Philipp Deppenwiese (Code Review) 17 Jul '18

17 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Add interface for FSP 2.0 mrc caching ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 11 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 14:40:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek: Share GPIO code among similar SOCs
by build bot (Jenkins) (Code Review) 17 Jul '18

17 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27416 ) Change subject: mediatek: Share GPIO code among similar SOCs ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27416/4/src/soc/mediatek/mt8173/include/soc… File src/soc/mediatek/mt8173/include/soc/gpio.h: https://review.coreboot.org/#/c/27416/4/src/soc/mediatek/mt8173/include/soc… PS4, Line 38: #define PIN(id, name, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/27416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Gerrit-Change-Number: 27416 Gerrit-PatchSet: 4 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ting Shen <phoenixshen(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 14:01:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek/mt8183: Add GPIO support
by build bot (Jenkins) (Code Review) 17 Jul '18

17 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27417 ) Change subject: mediatek/mt8183: Add GPIO support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27417/5/src/soc/mediatek/mt8183/include/soc… File src/soc/mediatek/mt8183/include/soc/gpio.h: https://review.coreboot.org/#/c/27417/5/src/soc/mediatek/mt8183/include/soc… PS5, Line 40: #define PIN(id, name, flag, bit, base, offset, \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/27417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Gerrit-Change-Number: 27417 Gerrit-PatchSet: 5 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ting Shen <phoenixshen(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 14:01:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/hp/compaq_8200_elite_sff: Call NPCD378 sleep/wake handlers
by Patrick Rudolph (Code Review) 17 Jul '18

17 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27511 Change subject: mb/hp/compaq_8200_elite_sff: Call NPCD378 sleep/wake handlers ...................................................................... mb/hp/compaq_8200_elite_sff: Call NPCD378 sleep/wake handlers * Call sleep and wake functions * Add power button * Add GBEs for wake Change-Id: I0cf2cffd06fe2470c2a8f1d8b57de282362ec17e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl M src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl 3 files changed, 51 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/27511/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl index 733c4b1..db7ff22 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl @@ -13,11 +13,14 @@ * GNU General Public License for more details. */ -Method(_WAK,1) +Method(_WAK, 1, NotSerialized) { + \_SB.PCI0.LPCB.SIO0.SIOW (Arg0) + Return(Package(){0,0}) } -Method(_PTS,1) +Method(_PTS, 1, NotSerialized) { -} + \_SB.PCI0.LPCB.SIO0.SIOS (Arg0) +} \ No newline at end of file diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl index 9ec2949..a22be9a 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl @@ -23,3 +23,41 @@ #define SUPERIO_SHOW_KBC #include <superio/nuvoton/npcd378/acpi/superio.asl> + +Scope (\_GPE) +{ + Method (_L08, 0, NotSerialized) + { + \_SB.PCI0.LPCB.SIO0.SIOH () + Notify (\_SB.PWRB, 0x02) + } + + Method (_L0B, 0, NotSerialized) + { + Notify (\_SB.PWRB, 0x02) + } + + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.EHC1, 0x02) + Notify (\_SB.PCI0.EHC2, 0x02) + //FIXME: Add GBE device + //Notify (\_SB.PCI0.GBE, 0x02) + Notify (\_SB.PWRB, 0x02) + } + + Method (_L09, 0, NotSerialized) + { + Notify (\_SB.PCI0.RP01, 0x02) + Notify (\_SB.PCI0.RP02, 0x02) + Notify (\_SB.PCI0.RP03, 0x02) + Notify (\_SB.PCI0.RP04, 0x02) + Notify (\_SB.PCI0.RP05, 0x02) + Notify (\_SB.PCI0.RP06, 0x02) + Notify (\_SB.PCI0.RP07, 0x02) + Notify (\_SB.PCI0.RP08, 0x02) + Notify (\_SB.PCI0.PEGP, 0x02) + + Notify (\_SB.PWRB, 0x02) + } +} \ No newline at end of file diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 555028c..0189e0f 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -40,5 +40,12 @@ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) + } } } -- To view, visit https://review.coreboot.org/27511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0cf2cffd06fe2470c2a8f1d8b57de282362ec17e Gerrit-Change-Number: 27511 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: superio/nuvoton/npcd378: Add ACPI code for S3 resume
by Patrick Rudolph (Code Review) 17 Jul '18

17 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27510 Change subject: superio/nuvoton/npcd378: Add ACPI code for S3 resume ...................................................................... superio/nuvoton/npcd378: Add ACPI code for S3 resume Configure SuperIO on shutdown to keep devices enabled, set green LED to fading on sleep and normal on wake. Add SSDT to write LDN4 IOBASE addresses stored in devicetree.cb. Tested on HP8200: * Wakes from power button or USB keyboard. * LED is fading Change-Id: I2035249a39616aa2d87bd93f9e49c70d231546cc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/superio/nuvoton/npcd378/acpi/superio.asl M src/superio/nuvoton/npcd378/superio.c 2 files changed, 206 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27510/1 diff --git a/src/superio/nuvoton/npcd378/acpi/superio.asl b/src/superio/nuvoton/npcd378/acpi/superio.asl index 963704e..295ac2b 100644 --- a/src/superio/nuvoton/npcd378/acpi/superio.asl +++ b/src/superio/nuvoton/npcd378/acpi/superio.asl @@ -165,4 +165,156 @@ #define SUPERIO_PNP_IO0 0x08, 0x08 #include <superio/acpi/pnp_generic.asl> #endif -} + + // generated by SSDT + External(SWB, IntObj) + External(SWL, IntObj) + OperationRegion (SWCR, SystemIO, SWB, SWL) + Field (SWCR, ByteAcc, NoLock, Preserve) + { + LEDC, 8, + SWCC, 8 + } + + // generated by SSDT + External(RNB, IntObj) + External(RNL, IntObj) + OperationRegion (RNTR, SystemIO, RNB, RNL) + Field (RNTR, ByteAcc, NoLock, Preserve) + { + GPES, 8, + GPEE, 8, + Offset (0x08), + GPS0, 8, + GPS1, 8, + GPS2, 8, + GPS3, 8, + GPE0, 8, + GPE1, 8, + GPE2, 8, + GPE3, 8 + } + + Name (MSFG, One) + Name (KBFG, One) + Name (PMFG, Zero) // Wake event backup + +#ifdef SUPERIO_SHOW_KBC + +#if defined(SUPERIO_KBC_LDN) +#define _PS2_KB SUPERIO_ID(KBD, SUPERIO_KBC_LDN) +#else +#define _PS2_KB PS2K +#endif + Scope (_PS2_KB) + { + Method (_PSW, 1, NotSerialized) + { + KBFG = Arg0 + } + + Method (_PRW, 0, NotSerialized) + { + Return (Package (0x02) {0x08, 0x03}) + } + } + +#if defined(SUPERIO_KBC_PS2M) +#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2M) +#elif defined(SUPERIO_KBC_PS2LDN) +#define _PS2_M SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN) +#else +#define _PS2_M PS2M +#endif + Scope (_PS2_M) + { + Method (_PSW, 1, NotSerialized) + { + MSFG = Arg0 + } + + Method (_PRW, 0, NotSerialized) + { + Return (Package (0x02) {0x08, 0x03}) + } + } + + Method (SIOH, 0, NotSerialized) + { + If ((PMFG & 0xE8)) + { + Notify (_PS2_KB, 0x02) + } + + If ((PMFG & 0x10)) + { + Notify (_PS2_M, 0x02) + } + } +#else + Method (SIOH, 0, NotSerialized) + { + } +#endif + + /* SuperIO sleep method */ + Method (SIOS, 1, NotSerialized) + { + If ((0x05 != Arg0)) + { + /* Set PS/2 powerstate in S3 */ + If (KBFG) + { + GPE2 |= 0xE8 + } + Else + { + GPE2 &= 0x17 + } + + If (MSFG) + { + GPE2 |= 0x10 + } + Else + { + GPE2 &= 0xEF + } + + /* Enable wake on GPE */ + GPEE = One + If ((0x03 == Arg0)) + { + /* green LED fading */ + Local1 = LEDC + Local1 &= 0xE0 + LEDC = (Local1 | 0x1C) + Local1 = SWCC + Local1 &= 0xBF + SWCC = (Local1 | 0x40) + } + } + + GPE0 = 0x10 + GPE1 = 0x20 + } + + /* SuperIO wake method */ + Method (SIOW, 1, NotSerialized) + { + /* Store wake status */ + PMFG = GPS2 + + /* Disable wake on GPE */ + GPEE = Zero + GPE0 = Zero + GPE1 = Zero + + /* green LED normal */ + Local1 = LEDC + Local1 &= 0xE0 + LEDC = (Local1 | 0x1E) + Local1 = SWCC + SWCC = (Local1 & 0xBF) + } +} \ No newline at end of file diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 85b02d3..bed138c 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -25,6 +25,8 @@ #include <pc80/keyboard.h> #include <stdlib.h> #include <superio/conf_mode.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include "npcd378.h" @@ -101,6 +103,53 @@ } } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void npcd378_ssdt(struct device *dev) +{ + struct resource *res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case NPCD378_PWR: { + res = find_resource(dev, PNP_IDX_IO0); + if (!res || !res->base) { + printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n", + NPCD378_PWR); + break; + } + + acpigen_write_scope(scope); + acpigen_write_name_integer("SWB", res->base); + acpigen_write_name_integer("SWL", res->size); + acpigen_pop_len(); /* pop scope */ + + res = find_resource(dev, PNP_IDX_IO1); + if (!res || !res->base) { + printk(BIOS_ERR, "NPCD378: LDN%u IOBASE2 not set.\n", + NPCD378_PWR); + break; + } + + acpigen_write_scope(scope); + acpigen_write_name_integer("RNB", res->base); + acpigen_write_name_integer("RNL", res->size); + acpigen_pop_len(); /* pop scope */ + break; + } + } +} + +static const char *npcd378_acpi_name(const struct device *dev) +{ + return "SIO0"; +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -108,6 +157,10 @@ .enable = pnp_alt_enable, .init = npcd378_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = npcd378_ssdt, + .acpi_name = npcd378_acpi_name, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/27510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2035249a39616aa2d87bd93f9e49c70d231546cc Gerrit-Change-Number: 27510 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: superio/nuvoton/npcd378: Fix resource size
by Patrick Rudolph (Code Review) 17 Jul '18

17 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27509 Change subject: superio/nuvoton/npcd378: Fix resource size ...................................................................... superio/nuvoton/npcd378: Fix resource size Based on vendor ACPI code. Change-Id: I4d6785efb9d18953042775e7164710ef3c041ed5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/superio/nuvoton/npcd378/superio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/27509/1 diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 013225d..85b02d3 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -118,24 +118,24 @@ { &ops, NPCD378_PWR, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0| PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7| PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, - 0x0ff8, 0x0ff8}, + 0x0ff8, 0x0ff0}, { &ops, NPCD378_AUX, PNP_IRQ0, 0x0fff, 0x0fff, }, { &ops, NPCD378_KBC, PNP_IO0|PNP_IO1|PNP_IRQ0, 0x0fff, 0x0fff, }, { &ops, NPCD378_WDT1, PNP_IO0|PNP_MSC8|PNP_MSC9| - PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0ff8}, + PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0f70}, { &ops, NPCD378_HWM, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3| - PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_IRQ0, 0x0ff8}, + PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_IRQ0, 0x0f00}, { &ops, NPCD378_GPIO_PP_OD, PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3| PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_MSC8|PNP_MSC9|PNP_MSCA| PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE}, { &ops, NPCD378_I2C, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_MSC0| PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7| PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, - 0x0ff8, 0x0ff8}, - { &ops, NPCD378_SUSPEND, PNP_IO0, 0x0ff8 }, + 0x0ff0, 0x0ff0}, + { &ops, NPCD378_SUSPEND, PNP_IO0, 0x0f70 }, { &ops, NPCD378_GPIOA, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3| - PNP_MSC4, 0x0ff8}, + PNP_MSC4, 0x0f70}, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/27509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4d6785efb9d18953042775e7164710ef3c041ed5 Gerrit-Change-Number: 27509 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/google/poppy/variant/nami: Fix vbt ssf setting for panel T8/T10
by Arthur Heymans (Code Review) 17 Jul '18

17 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27507 ) Change subject: mb/google/poppy/variant/nami: Fix vbt ssf setting for panel T8/T10 ...................................................................... Patch Set 2: Code-Review-1 Please add this vbt file to the mainboard dir. -- To view, visit https://review.coreboot.org/27507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I642a1aa0b2d13b33e6113f94e73dfc77834766d4 Gerrit-Change-Number: 27507 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 10:43:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/nautilus: Camera module NVM enabling
by Andy Yeh (Code Review) 17 Jul '18

17 Jul '18

Andy Yeh has posted comments on this change. ( https://review.coreboot.org/27508 ) Change subject: mb/google/nautilus: Camera module NVM enabling ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/27508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib83fa1a522402a59566e3f55fa5c1af4490266e4 Gerrit-Change-Number: 27508 Gerrit-PatchSet: 2 Gerrit-Owner: AlanX Chiang <alanx.chiang(a)intel.com> Gerrit-Reviewer: Andy Yeh (1001830) Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 10:10:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/nami: Fix vbt ssf setting for panel T8/T10
by TH Lin (Code Review) 17 Jul '18

17 Jul '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27507 to look at the new patch set (#2). Change subject: mb/google/poppy/variant/nami: Fix vbt ssf setting for panel T8/T10 ...................................................................... mb/google/poppy/variant/nami: Fix vbt ssf setting for panel T8/T10 Akali/Akali360 panel:T8 minimum 33.3 ms & T10 minimun 100ms BUG=b:111530392 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test & measure T8/T10 waveform Change-Id: I642a1aa0b2d13b33e6113f94e73dfc77834766d4 Signed-off-by: T.H. Lin <t.h_lin(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/include/variant/sku.h M src/mainboard/google/poppy/variants/nami/mainboard.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27507/2 -- To view, visit https://review.coreboot.org/27507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I642a1aa0b2d13b33e6113f94e73dfc77834766d4 Gerrit-Change-Number: 27507 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018