coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mediatek: Share GPIO code among similar SOCs
by build bot (Jenkins) (Code Review) 18 Jul '18

18 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27416 ) Change subject: mediatek: Share GPIO code among similar SOCs ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27416/5/src/soc/mediatek/mt8173/include/soc… File src/soc/mediatek/mt8173/include/soc/gpio.h: https://review.coreboot.org/#/c/27416/5/src/soc/mediatek/mt8173/include/soc… PS5, Line 38: #define PIN(id, name, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/27416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Gerrit-Change-Number: 27416 Gerrit-PatchSet: 5 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ting Shen <phoenixshen(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Jul 2018 13:09:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek/mt8183: Separate bootblock from coreboot image
by Tristan Hsieh (Code Review) 18 Jul '18

18 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27528 Change subject: mediatek/mt8183: Separate bootblock from coreboot image ...................................................................... mediatek/mt8183: Separate bootblock from coreboot image We have to separate bootblock from coreboot image since MT8183 must load bootblock from eMMC, and everything else gets loaded from SPI NOR. So, we create a 0 byte bootblock.bin for the generic build system, and pack bootblock.raw.bin to a new file emmc_bootblock.bin. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I2f0725dbf74120a3b0ba09363f6b673b8d20be5d Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27528/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index ca59d34..89bfc94 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -38,7 +38,12 @@ CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin +$(objcbfs)/bootblock.bin: + truncate -s 0 $@ + +$(objcbfs)/emmc_bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8183 emmc $< $@ +coreboot: $(objcbfs)/emmc_bootblock.bin + endif -- To view, visit https://review.coreboot.org/27528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2f0725dbf74120a3b0ba09363f6b673b8d20be5d Gerrit-Change-Number: 27528 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: Documentation: update draft git command
by Patrick Georgi (Code Review) 18 Jul '18

18 Jul '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/27526 ) Change subject: Documentation: update draft git command ...................................................................... Patch Set 1: Code-Review+2 Thanks! -- To view, visit https://review.coreboot.org/27526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9c68e496ecd47fb559dd2ad400406007028cbb24 Gerrit-Change-Number: 27526 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 18 Jul 2018 12:07:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/crossgcc: update IASL to v20180629
by Martin Roth (Code Review) 18 Jul '18

18 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27527 ) Change subject: util/crossgcc: update IASL to v20180629 ...................................................................... Patch Set 1: This is currently more just for testing than for a real plan to update IASL to this version. IASL releases with a monthly cadence, and I don't think we want to update the coreboot toolchain with that frequency. -- To view, visit https://review.coreboot.org/27527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idce2587a87c5e0677a4571b59ef40e5486c22da9 Gerrit-Change-Number: 27527 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 18 Jul 2018 12:06:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation: update draft git command
by Tom Hiller (Code Review) 18 Jul '18

18 Jul '18

Tom Hiller has posted comments on this change. ( https://review.coreboot.org/27526 ) Change subject: Documentation: update draft git command ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/27526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9c68e496ecd47fb559dd2ad400406007028cbb24 Gerrit-Change-Number: 27526 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 18 Jul 2018 12:05:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/crossgcc: update IASL to v20180629
by Martin Roth (Code Review) 18 Jul '18

18 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27527 Change subject: util/crossgcc: update IASL to v20180629 ...................................................................... util/crossgcc: update IASL to v20180629 Change-Id: Idce2587a87c5e0677a4571b59ef40e5486c22da9 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20180629_iasl.patch D util/crossgcc/sum/acpica-unix2-20180531.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20180629.tar.gz.cksum 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/27527/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a9d9057..db8723d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="June 11th, 2018" -CROSSGCC_VERSION="1.52" +CROSSGCC_DATE="July 18th, 2018" +CROSSGCC_VERSION="1.53" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -42,7 +42,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.30 GDB_VERSION=8.0 -IASL_VERSION=20180531 +IASL_VERSION=20180629 PYTHON_VERSION=3.5.1 EXPAT_VERSION=2.2.1 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20180531_iasl.patch b/util/crossgcc/patches/acpica-unix2-20180629_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20180531_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20180629_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20180531.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20180531.tar.gz.cksum deleted file mode 100644 index 7001858..0000000 --- a/util/crossgcc/sum/acpica-unix2-20180531.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -17717140438d506533b4a56e34350749d7b84d6c tarballs/acpica-unix2-20180531.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20180629.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20180629.tar.gz.cksum new file mode 100644 index 0000000..880a404 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20180629.tar.gz.cksum @@ -0,0 +1 @@ +f2467ae9c55ee4b24c21c0b06b402c6bdd444260 tarballs/acpica-unix2-20180629.tar.gz -- To view, visit https://review.coreboot.org/27527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idce2587a87c5e0677a4571b59ef40e5486c22da9 Gerrit-Change-Number: 27527 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/hp/compaq_8200_elite_sff: Add data.vbt
by Arthur Heymans (Code Review) 18 Jul '18

18 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27521 ) Change subject: mb/hp/compaq_8200_elite_sff: Add data.vbt ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb65d6c2ec85f09b8e7e9967ba0a055f876378df Gerrit-Change-Number: 27521 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Jul 2018 09:02:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add entry to identify CFL cpu in report platform
by Maulik V Vaghela (Code Review) 18 Jul '18

18 Jul '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27524 Change subject: soc/intel/cannonlake: Add entry to identify CFL cpu in report platform ...................................................................... soc/intel/cannonlake: Add entry to identify CFL cpu in report platform Add code to identify CFL U platform in report platform. BUG=none BRANCH=none TEST=none Change-Id: I2790340b42c94baf9fec3e728010bbdf0d8486b5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27524/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 9d967ce..6d93b7e 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -36,6 +36,7 @@ { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, + { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, }; static struct { @@ -44,6 +45,7 @@ } mch_table[] = { { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"}, }; static struct { @@ -67,6 +69,7 @@ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" }, { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, + { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT"}, }; static uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/27524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2790340b42c94baf9fec3e728010bbdf0d8486b5 Gerrit-Change-Number: 27524 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Update PMC base address for CNP H and LP
by Maulik V Vaghela (Code Review) 18 Jul '18

18 Jul '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27523 Change subject: soc/intel/cannonlake: Update PMC base address for CNP H and LP ...................................................................... soc/intel/cannonlake: Update PMC base address for CNP H and LP PMC base address is different for CNP LP pch and CNP H pch. Added logic to determine PMC base addrress dynamically based on PCH ID. BUG=none BRANCH=none TEST=none Change-Id: I833395260e8fb631823bd03192a092df323250fa Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/include/soc/lpc.h 2 files changed, 45 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27523/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index eb67012..e5bb8e6 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -27,12 +27,15 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/p2sb.h> +#include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/smbus.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 + #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -51,6 +54,37 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +static uint8_t get_pch_series(void) +{ + uint16_t lpc_did; + uint8_t pch_series; + + lpc_did = (pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID) & 0xFF00); + + if ((lpc_did >> 0x8) == 0x9D) + pch_series = PCH_LP; + else if ((lpc_did >> 0x08) == 0xA2) + pch_series = PCH_H; + else + pch_series = PCH_UNKNOWN_SERIES; + + return pch_series; +} + +static uint32_t get_pmc_reg_base(void) +{ + uint8_t pch_series; + + pch_series = get_pch_series(); + + if (pch_series == PCH_H) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H; + else if (pch_series == PCH_LP) + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; + else + return 0; +} + static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -91,22 +125,27 @@ static void soc_config_acpibase(void) { uint32_t pmc_reg_value; + uint32_t pmc_base_reg; - pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + pmc_base_reg = get_pmc_reg_base(); + if (pmc_base_reg == 0x00) + return; + + pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); if (pmc_reg_value != 0xFFFFFFFF) { /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, ACPI_BASE_ADDRESS); /* Enable IO Space */ - pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); } diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index 3ea9be9..74a731b 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -17,6 +17,7 @@ #ifndef _SOC_CANNONLAKE_LPC_H_ #define _SOC_CANNONLAKE_LPC_H_ +#define PCI_DEVICE_ID 0x02 /* PCI Configuration Space (D31:F0): LPC */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 -- To view, visit https://review.coreboot.org/27523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I833395260e8fb631823bd03192a092df323250fa Gerrit-Change-Number: 27523 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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Change in coreboot[master]: src/soc/intel: Add new device IDs
by Maulik V Vaghela (Code Review) 18 Jul '18

18 Jul '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27522 Change subject: src/soc/intel: Add new device IDs ...................................................................... src/soc/intel: Add new device IDs Added new device IDs for SATA, GT and Northbridge to pci_ids.h Added entry to identify CFL U GT into systemagent.c Added CFL CPU D0 stepping ID to mp_init.h and mp_init.c Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik <maulik.v.vaghela(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/27522/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 40f2ea4..8e0c202 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2774,6 +2774,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5 #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7 #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_CNL_H_SATA 0xa352 +#define PCI_DEVICE_ID_INTEL_CNL_L_SATA 0x9dd3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2881,6 +2883,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A +#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -2898,6 +2901,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 +#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index fd0ac99..8235aaf 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -71,6 +71,10 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_B0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 3057209..9680fbe 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,10 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_WHISKEYLAKE_B0 0x806eb +#define CPUID_COFFEELAKE_A0 0x906ea +#define CPUID_COFFEELAKE_U0 0x906ea +#define CPUID_COFFEELAKE_D0 0x806ea /* * MP Init callback function to Find CPU Topology. This function is common diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 54646c9..3229632 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -301,6 +301,7 @@ PCI_DEVICE_ID_INTEL_KBL_ID_H, PCI_DEVICE_ID_INTEL_KBL_U_R, PCI_DEVICE_ID_INTEL_KBL_ID_DT, + PCI_DEVICE_ID_INTEL_CFL_ID_U, 0 }; -- To view, visit https://review.coreboot.org/27522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Gerrit-Change-Number: 27522 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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coreboot-gerrit July 2018