coreboot-gerrit July 2018

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Change in coreboot[master]: vboot: fix typo
by Martin Roth (Code Review) 17 Jul '18

17 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27517 ) Change subject: vboot: fix typo ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27517/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27517/1//COMMIT_MSG@7 PS1, Line 7: vboot This should probably be "security/vboot:" Typically we want to start with a path. -- To view, visit https://review.coreboot.org/27517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4 Gerrit-Change-Number: 27517 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 20:35:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: vboot: fix typo
by Martin Roth (Code Review) 17 Jul '18

17 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27517 ) Change subject: vboot: fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4 Gerrit-Change-Number: 27517 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 20:34:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vboot: fix typo
by Furquan Shaikh (Code Review) 17 Jul '18

17 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27517 ) Change subject: vboot: fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4 Gerrit-Change-Number: 27517 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 17 Jul 2018 19:32:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vboot: fix typo
by Raul Rangel (Code Review) 17 Jul '18

17 Jul '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27517 Change subject: vboot: fix typo ...................................................................... vboot: fix typo BUG=none TEST=none Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/security/vboot/vboot_logic.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27517/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 9710ae2..a0e6a32 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -357,7 +357,7 @@ return; } - printk(BIOS_INFO, "Reboot reqested (%x)\n", rv); + printk(BIOS_INFO, "Reboot requested (%x)\n", rv); save_if_needed(&ctx); vboot_reboot(); } -- To view, visit https://review.coreboot.org/27517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4 Gerrit-Change-Number: 27517 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: tint: introduce the new tint build system with checksum verification
by build bot (Jenkins) (Code Review) 17 Jul '18

17 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 3: (12 comments) https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… File payloads/external/tint/generate_core.sh: https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 38: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 40: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 54: FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 64: import_from_file $buildgcc $corescript "# Find all the required tools" "# Allow" last_line_disabled || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 70: import_from_file $buildgcc $corescript "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 86: sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 95: # Insert prepare_${package} function call between the unpack and patch operations line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/generate_cor… PS3, Line 99: sed -i -e "/\$TAR \$FLAGS \$(basename \$archive)/a prepare_\${package} || exit \"\$?\"" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/tintify_core… File payloads/external/tint/tintify_core.sh: https://review.coreboot.org/#/c/23856/3/payloads/external/tint/tintify_core… PS3, Line 42: echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ]; then" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/tintify_core… PS3, Line 43: echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/tintify_core… PS3, Line 61: echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters https://review.coreboot.org/#/c/23856/3/payloads/external/tint/tintify_core… PS3, Line 65: echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters -- To view, visit https://review.coreboot.org/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 3 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Jul 2018 19:01:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: security/vboot: Add interface for FSP 2.0 mrc caching
by Philipp Deppenwiese (Code Review) 17 Jul '18

17 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/24904 ) Change subject: security/vboot: Add interface for FSP 2.0 mrc caching ...................................................................... security/vboot: Add interface for FSP 2.0 mrc caching * Move vboot/tpm specific implementation to vboot. * Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set. * Preparation for software hash function support, no logic changed. Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/24904 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/drivers/intel/fsp2_0/include/fsp/memory_init.h M src/drivers/intel/fsp2_0/memory_init.c M src/security/vboot/Makefile.inc A src/security/vboot/mrc_cache_hash_tpm.c 4 files changed, 155 insertions(+), 99 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/include/fsp/memory_init.h b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h new file mode 100644 index 0000000..05ea440 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/memory_init.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FSP2_0_MEMORY_INIT_H_ +#define _FSP2_0_MEMORY_INIT_H_ + +#include <types.h> + +/* + * Updates mrc cache hash if it differs. + */ +void mrc_cache_update_hash(const uint8_t *data, size_t size); + +/* + * Verifies mrc cache hash which is stored somewhere. + * return 1 verification was successful and 0 for error. + */ +int mrc_cache_verify_hash(const uint8_t *data, size_t size); + +#endif /* _FSP2_0_MEMORY_INIT_H_ */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1ca5208..cf033d7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -31,63 +31,10 @@ #include <string.h> #include <symbols.h> #include <timestamp.h> -#include <security/tpm/tspi.h> #include <security/vboot/vboot_common.h> +#include <security/tpm/tspi.h> #include <vb2_api.h> - -static void mrc_cache_update_tpm_hash(const uint8_t *data, size_t size) -{ - uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; - static const uint8_t dead_hash[VB2_SHA256_DIGEST_SIZE] = { - 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ - 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ - 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ - 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ - 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ - 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ - 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ - 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ - }; - const uint8_t *hash_ptr = data_hash; - - /* We do not store normal mode data hash in TPM. */ - if (!vboot_recovery_mode_enabled()) - return; - - /* Bail out early if no mrc hash space is supported in TPM. */ - if (!IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH)) - return; - - /* Initialize TPM driver. */ - if (tlcl_lib_init() != VB2_SUCCESS) { - printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); - return; - } - - /* Calculate hash of data generated by MRC. */ - if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, - sizeof(data_hash))) { - printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data. " - "Not updating TPM hash space.\n"); - /* - * Since data is being updated in recovery cache, the hash - * currently stored in TPM recovery hash space is no longer - * valid. If we are not able to calculate hash of the data being - * updated, reset all the bits in TPM recovery hash space to - * pre-defined hash pattern. - */ - hash_ptr = dead_hash; - } - - /* Write hash of data to TPM space. */ - if (antirollback_write_space_rec_hash(hash_ptr, VB2_SHA256_DIGEST_SIZE) - != TPM_SUCCESS) { - printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n"); - return; - } - - printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n"); -} +#include <fsp/memory_init.h> static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { @@ -113,7 +60,8 @@ mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); - mrc_cache_update_tpm_hash(mrc_data, mrc_data_size); + if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH)) + mrc_cache_update_hash(mrc_data, mrc_data_size); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -156,48 +104,6 @@ tpm_setup(s3wake); } -static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size) -{ - uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; - uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; - - /* We do not store normal mode data hash in TPM. */ - if (!vboot_recovery_mode_enabled()) - return 1; - - if (!IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH)) - return 1; - - /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ - if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, - sizeof(data_hash))) { - printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); - return 0; - } - - /* Initialize TPM driver. */ - if (tlcl_lib_init() != VB2_SUCCESS) { - printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); - return 0; - } - - /* Read hash of MRC data saved in TPM. */ - if (antirollback_read_space_rec_hash(tpm_hash, sizeof(tpm_hash)) - != TPM_SUCCESS) { - printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n"); - return 0; - } - - if (memcmp(tpm_hash, data_hash, sizeof(tpm_hash))) { - printk(BIOS_ERR, "MRC: Hash comparison failed.\n"); - return 0; - } - - printk(BIOS_INFO, "MRC: Hash comparison successful. " - "Using data from RECOVERY_MRC_CACHE\n"); - return 1; -} - static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) { struct region_device rdev; @@ -230,7 +136,8 @@ if (data == NULL) return; - if (!mrc_cache_verify_tpm_hash(data, region_device_sz(&rdev))) + if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH) && + !mrc_cache_verify_hash(data, region_device_sz(&rdev))) return; /* MRC cache found */ diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 75c2a9e..b542425 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -78,6 +78,8 @@ ramstage-y += common.c postcar-y += common.c +romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c + ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) else diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c new file mode 100644 index 0000000..d54f8f4 --- /dev/null +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <security/vboot/antirollback.h> +#include <program_loading.h> +#include <security/vboot/vboot_common.h> +#include <vb2_api.h> +#include <security/tpm/tss.h> +#include <fsp/memory_init.h> +#include <console/console.h> +#include <string.h> + +void mrc_cache_update_hash(const uint8_t *data, size_t size) +{ + uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; + static const uint8_t dead_hash[VB2_SHA256_DIGEST_SIZE] = { + 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ + 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ + 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ + 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ + 0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */ + 0xde, 0xad, 0xde, 0xad, /* DEADDEAD */ + 0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */ + 0xba, 0xad, 0xba, 0xad, /* BAADBAAD */ + }; + const uint8_t *hash_ptr = data_hash; + + /* We do not store normal mode data hash in TPM. */ + if (!vboot_recovery_mode_enabled()) + return; + + /* Initialize TPM driver. */ + if (tlcl_lib_init() != VB2_SUCCESS) { + printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); + return; + } + + /* Calculate hash of data generated by MRC. */ + if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, + sizeof(data_hash))) { + printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data. " + "Not updating TPM hash space.\n"); + /* + * Since data is being updated in recovery cache, the hash + * currently stored in TPM recovery hash space is no longer + * valid. If we are not able to calculate hash of the data being + * updated, reset all the bits in TPM recovery hash space to + * pre-defined hash pattern. + */ + hash_ptr = dead_hash; + } + + /* Write hash of data to TPM space. */ + if (antirollback_write_space_rec_hash(hash_ptr, VB2_SHA256_DIGEST_SIZE) + != TPM_SUCCESS) { + printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n"); + return; + } + + printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n"); +} + +int mrc_cache_verify_hash(const uint8_t *data, size_t size) +{ + uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; + uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; + + /* We do not store normal mode data hash in TPM. */ + if (!vboot_recovery_mode_enabled()) + return 1; + + /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ + if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, + sizeof(data_hash))) { + printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); + return 0; + } + + /* Initialize TPM driver. */ + if (tlcl_lib_init() != VB2_SUCCESS) { + printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); + return 0; + } + + /* Read hash of MRC data saved in TPM. */ + if (antirollback_read_space_rec_hash(tpm_hash, sizeof(tpm_hash)) + != TPM_SUCCESS) { + printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n"); + return 0; + } + + if (memcmp(tpm_hash, data_hash, sizeof(tpm_hash))) { + printk(BIOS_ERR, "MRC: Hash comparison failed.\n"); + return 0; + } + + printk(BIOS_INFO, "MRC: Hash comparison successful. " + "Using data from RECOVERY_MRC_CACHE\n"); + return 1; +} -- To view, visit https://review.coreboot.org/24904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Gerrit-Change-Number: 24904 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/google/octopus: Create meep variant
by Justin TerAvest (Code Review) 17 Jul '18

17 Jul '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/27516 Change subject: mb/google/octopus: Create meep variant ...................................................................... mb/google/octopus: Create meep variant This creates a meep variant for octopus. The devicetree overrides are copied from yorp, otherwise everything just defaults to baseboard settings. BUG=b:111543000 TEST=None Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/meep/include/variant/ec.h A src/mainboard/google/octopus/variants/meep/include/variant/gpio.h A src/mainboard/google/octopus/variants/meep/overridetree.cb 6 files changed, 127 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/27516/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 34ca725..dc58ec8 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -43,6 +43,7 @@ default "phaser" if BOARD_GOOGLE_PHASER default "fleex" if BOARD_GOOGLE_FLEEX default "bobba" if BOARD_GOOGLE_BOBBA + default "meep" if BOARD_GOOGLE_MEEP default "octopus" if BOARD_GOOGLE_OCTOPUS config DEVICETREE @@ -60,6 +61,7 @@ default "Phaser" if BOARD_GOOGLE_PHASER default "Fleex" if BOARD_GOOGLE_FLEEX default "Bobba" if BOARD_GOOGLE_BOBBA + default "Meep" if BOARD_GOOGLE_MEEP default "Octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY @@ -74,6 +76,7 @@ default "PHASER TEST 7167" if BOARD_GOOGLE_PHASER default "FLEEX TEST 7423" if BOARD_GOOGLE_FLEEX default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA + default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS config MAX_CPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index cfe051c..4f6e5a5 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -37,3 +37,10 @@ select BOARD_GOOGLE_BASEBOARD_OCTOPUS select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_MEEP + bool "-> Meep" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/ec.h b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb new file mode 100644 index 0000000..d29e6c1 --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -0,0 +1,59 @@ +chip soc/intel/apollolake + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW2_02" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 7 + end +end -- To view, visit https://review.coreboot.org/27516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac Gerrit-Change-Number: 27516 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: nb/intel/nehalem: Remove the C native graphic init
by Arthur Heymans (Code Review) 17 Jul '18

17 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27515 Change subject: nb/intel/nehalem: Remove the C native graphic init ...................................................................... nb/intel/nehalem: Remove the C native graphic init Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/gma.c 1 file changed, 4 insertions(+), 459 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27515/1 diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index aeff69a..6e2d404 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -571,441 +571,6 @@ } } -static void train_link(u8 *mmio) -{ - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - - write32(mmio + 0x000f0018, 0x000000ff); - write32(mmio + 0x000f1018, 0x000000ff); - write32(mmio + 0x000f000c, 0x001a2050); - write32(mmio + 0x00060100, 0x001c4000); - write32(mmio + 0x00060100, 0x801c4000); - write32(mmio + 0x000f000c, 0x801a2050); - write32(mmio + 0x00060100, 0x801c4000); - write32(mmio + 0x000f000c, 0x801a2050); - mdelay(1); - - read32(mmio + 0x000f0014); // = 0x00000100 - write32(mmio + 0x000f0014, 0x00000100); - write32(mmio + 0x00060100, 0x901c4000); - write32(mmio + 0x000f000c, 0x901a2050); - mdelay(1); - read32(mmio + 0x000f0014); // = 0x00000600 -} - -static void power_port(u8 *mmio) -{ - read32(mmio + 0x000e1100); // = 0x00000000 - write32(mmio + 0x000e1100, 0x00000000); - write32(mmio + 0x000e1100, 0x00010000); - read32(mmio + 0x000e1100); // = 0x00010000 - read32(mmio + 0x000e1100); // = 0x00010000 - read32(mmio + 0x000e1100); // = 0x00000000 - write32(mmio + 0x000e1100, 0x00000000); - read32(mmio + 0x000e1100); // = 0x00000000 - read32(mmio + 0x000e4200); // = 0x0000001c - write32(mmio + 0x000e4210, 0x8004003e); - write32(mmio + 0x000e4214, 0x80060002); - write32(mmio + 0x000e4218, 0x01000000); - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - read32(mmio + 0x000e4210); // = 0x0144003e - write32(mmio + 0x000e4210, 0x8074003e); - read32(mmio + 0x000e4210); // = 0x5144003e - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - read32(mmio + 0x000e4210); // = 0x0144003e - write32(mmio + 0x000e4210, 0x8074003e); - read32(mmio + 0x000e4210); // = 0x5144003e - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - read32(mmio + 0x000e4210); // = 0x0144003e - write32(mmio + 0x000e4210, 0x8074003e); - read32(mmio + 0x000e4210); // = 0x5144003e - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - write32(mmio + 0x000e4f00, 0x0100030c); - write32(mmio + 0x000e4f04, 0x00b8230c); - write32(mmio + 0x000e4f08, 0x06f8930c); - write32(mmio + 0x000e4f0c, 0x09f8e38e); - write32(mmio + 0x000e4f10, 0x00b8030c); - write32(mmio + 0x000e4f14, 0x0b78830c); - write32(mmio + 0x000e4f18, 0x0ff8d3cf); - write32(mmio + 0x000e4f1c, 0x01e8030c); - write32(mmio + 0x000e4f20, 0x0ff863cf); - write32(mmio + 0x000e4f24, 0x0ff803cf); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x000c4000); // = 0x00000000 - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x000e1150); // = 0x0000001c - write32(mmio + 0x000e1150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x000c4000); // = 0x00000000 - read32(mmio + 0x000e1180); // = 0x40000002 -} - -static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) -{ - int i; - u8 edid_data[128]; - struct edid edid; - struct edid_mode *mode; - u32 hactive, vactive, right_border, bottom_border; - int hpolarity, vpolarity; - u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; - u32 candp1, candn; - u32 best_delta = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; - - write32(mmio + 0x00070080, 0x00000000); - write32(mmio + DSPCNTR(0), 0x00000000); - write32(mmio + 0x00071180, 0x00000000); - write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); - write32(mmio + 0x0007019c, 0x00000000); - write32(mmio + 0x0007119c, 0x00000000); - write32(mmio + 0x000fc008, 0x2c010000); - write32(mmio + 0x000fc020, 0x2c010000); - write32(mmio + 0x000fc038, 0x2c010000); - write32(mmio + 0x000fc050, 0x2c010000); - write32(mmio + 0x000fc408, 0x2c010000); - write32(mmio + 0x000fc420, 0x2c010000); - write32(mmio + 0x000fc438, 0x2c010000); - write32(mmio + 0x000fc450, 0x2c010000); - vga_gr_write(0x18, 0); - write32(mmio + 0x00042004, 0x02000000); - write32(mmio + 0x000fd034, 0x8421ffe0); - - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } - - vga_misc_write(0x67); - - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - power_port(mmio); - - intel_gmbus_read_edid(mmio + PCH_GMBUS0, GMBUS_PORT_PANEL, 0x50, - edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + PCH_GMBUS0); - decode_edid(edid_data, - sizeof(edid_data), &edid); - mode = &edid.mode; - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; - vactive = edid.y_resolution; - right_border = mode->hborder; - bottom_border = mode->vborder; - hpolarity = (mode->phsync == '-'); - vpolarity = (mode->pvsync == '-'); - vsync = mode->vspw; - hsync = mode->hspw; - vblank = mode->vbl; - hblank = mode->hbl; - hfront_porch = mode->hso; - vfront_porch = mode->vso; - - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - vga_textmode_init(); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); - } - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesn't overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom + 60000) / 120000; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (120000 * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; - } - } - } - - if (best_delta == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return; - } - - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_DEBUG, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_DEBUG, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_DEBUG, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_DEBUG, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, - mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); - printk(BIOS_DEBUG, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); - - write32(mmio + PCH_LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock - ? 0x1002 : 0x400)); - mdelay(1); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(mmio + _PCH_FP0(0), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); - write32(mmio + _PCH_DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - mdelay(1); - write32(mmio + _PCH_DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - /* Re-lock the registers. */ - write32(mmio + PCH_PP_CONTROL, - (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - - write32(mmio + PCH_LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + PIPESRC(0), (hactive - 1) << 16 | (vactive - 1)); - write32(mmio + PF_CTL(0), 0); - write32(mmio + PF_WIN_SZ(0), 0); - } else { - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - } - - mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f0008, 0x00000040); - write32(mmio + 0x000f000c, 0x00022050); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) - write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE); - else - write32(mmio + CPU_VGACNTRL, 0x20298e); - - train_link(mmio); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + DSPCNTR(0), - DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); - } - - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0xb01a2050); - mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC | - (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? TRANS_STATE_MASK : 0)); - write32(mmio + PCH_LVDS, - LVDS_PORT_ENABLE - | (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); - mdelay(1); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | PANEL_POWER_ON | PANEL_POWER_RESET); - - printk (BIOS_DEBUG, "waiting for panel powerup\n"); - while (1) { - u32 reg32; - reg32 = read32(mmio + PCH_PP_STATUS); - if (((reg32 >> 28) & 3) == 0) - break; - } - printk (BIOS_DEBUG, "panel powered up\n"); - - write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); - - /* Doesn't change any hw behaviour but vga oprom expects it there. */ - write32(mmio + 0x0004f040, 0x01000008); - write32(mmio + 0x0004f04c, 0x7f7f0000); - write32(mmio + 0x0004f054, 0x0000020d); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - memset((void *)lfb, 0, - edid.x_resolution * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); - } -} - /* Enable SCI to ACPI _GPE._L06 */ static void gma_enable_swsci(void) { @@ -1037,32 +602,12 @@ /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || - IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - u32 physbase; + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; - struct resource *lfb_res; - struct resource *pio_res; + int lightup_ok; + printk(BIOS_SPEW, "Initializing VGA without OPROM."); - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && - pio_res && pio_res->base && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - } else { - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); - } - } - + gma_gfxinit(&lightup_ok); /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); -- To view, visit https://review.coreboot.org/27515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121 Gerrit-Change-Number: 27515 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/packardbell/ms2290: Allow use of libgfxinit
by Arthur Heymans (Code Review) 17 Jul '18

17 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27514 Change subject: mb/packardbell/ms2290: Allow use of libgfxinit ...................................................................... mb/packardbell/ms2290: Allow use of libgfxinit Untested but expected to work. Change-Id: I5a77b7a4343f108f46cf1f97a94e61e88eecb417 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/packardbell/ms2290/Kconfig M src/mainboard/packardbell/ms2290/Makefile.inc A src/mainboard/packardbell/ms2290/gma-mainboard.ads 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27514/1 diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index ca25a14..4fcb8e0 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -14,6 +14,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_LIBGFXINIT select INTEL_INT15 select EC_ACPI diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index 3196fa6..b8681b9 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -14,3 +14,5 @@ ## smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file diff --git a/src/mainboard/packardbell/ms2290/gma-mainboard.ads b/src/mainboard/packardbell/ms2290/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/packardbell/ms2290/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/27514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a77b7a4343f108f46cf1f97a94e61e88eecb417 Gerrit-Change-Number: 27514 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/lenovo/x201: Allow use of libgfxinit
by Arthur Heymans (Code Review) 17 Jul '18

17 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27513 Change subject: mb/lenovo/x201: Allow use of libgfxinit ...................................................................... mb/lenovo/x201: Allow use of libgfxinit Tested on LVDS(internal),VGA and HDMI output with both native resolution and textmode. Change-Id: Ibfcb586d7b4cac7f1d22540bb96c288704a277a0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/Makefile.inc A src/mainboard/lenovo/x201/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/27513/1 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 398677e..3165ce1 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -15,6 +15,7 @@ select INTEL_INT15 select HAVE_ACPI_RESUME select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_LIBGFXINIT select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index b0e116f..f7ff93b 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -18,3 +18,5 @@ romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x201/gma-mainboard.ads b/src/mainboard/lenovo/x201/gma-mainboard.ads new file mode 100644 index 0000000..92702b2 --- /dev/null +++ b/src/mainboard/lenovo/x201/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/27513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibfcb586d7b4cac7f1d22540bb96c288704a277a0 Gerrit-Change-Number: 27513 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit July 2018