coreboot-gerrit July 2018

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Change in coreboot[master]: This fix issus(202e7d4f3c)
by Xiang Wang (Code Review) 19 Jul '18

19 Jul '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Martin Roth, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27543 to look at the new patch set (#3). Change subject: This fix issus(202e7d4f3c) ...................................................................... This fix issus(202e7d4f3c) When I tried to compile the RISC-V code, I found some errors: `PRIu64` is undefined src/arch/riscv/timestamp.c does not exist Currently RISC-V does not have the implementation and use of timestamp, so I temporarily deleted the code related to timestamp in the Makefile. And defined PRIu64. Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/stdint.h 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27543/3 -- To view, visit https://review.coreboot.org/27543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Gerrit-Change-Number: 27543 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: This fix issus(202e7d4f3c)
by Xiang Wang (Code Review) 19 Jul '18

19 Jul '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27543 ) Change subject: This fix issus(202e7d4f3c) ...................................................................... This fix issus(202e7d4f3c) When I tried to compile the RISC-V code, I found some errors: is undefined src/arch/riscv/timestamp.c does not exist Currently RISC-V does not have the implementation and use of timestamp, so I temporarily deleted the code related to timestamp in the Makefile. And defined PRIu64. Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/stdint.h 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27543/2 -- To view, visit https://review.coreboot.org/27543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Gerrit-Change-Number: 27543 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: This fix issus(202e7d4f3c)
by Xiang Wang (Code Review) 19 Jul '18

19 Jul '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27543 Change subject: This fix issus(202e7d4f3c) ...................................................................... This fix issus(202e7d4f3c) When I tried to compile the RISC-V code, I found some errors: is undefined src/arch/riscv/timestamp.c does not exist Currently RISC-V does not have the implementation and use of timestamp, so I temporarily deleted the code related to timestamp in the makefile.And defined PRIu64. Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/stdint.h 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27543/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index dab661e..e00469b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -82,8 +82,6 @@ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c - # Build the romstage $(objcbfs)/romstage.debug: $$(romstage-objs) @@ -116,8 +114,6 @@ $(eval $(call create_class_compiler,rmodules,riscv)) -ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c - ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c # Build the ramstage diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h index 446a136..f8d1736 100644 --- a/src/arch/riscv/include/stdint.h +++ b/src/arch/riscv/include/stdint.h @@ -70,7 +70,9 @@ #define false 0 /* Types for `void *' pointers. */ -typedef s64 intptr_t; -typedef u64 uintptr_t; +typedef s64 intptr_t; +typedef u64 uintptr_t; + +#define PRIu64 "llu" #endif /* RISCV_STDINT_H */ -- To view, visit https://review.coreboot.org/27543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Gerrit-Change-Number: 27543 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2#
by Furquan Shaikh (Code Review) 19 Jul '18

19 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27542 ) Change subject: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2# ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/27542/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nautilus/gpio.c: https://review.coreboot.org/#/c/27542/1/src/mainboard/google/poppy/variants… PS1, Line 223: > They have 10k external pull-up. Components R672 and R642 in schematics. Ah yes.. Thanks! -- To view, visit https://review.coreboot.org/27542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066 Gerrit-Change-Number: 27542 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Jul 2018 06:39:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2#
by Seunghwan Kim (Code Review) 19 Jul '18

19 Jul '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/27542 ) Change subject: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2# ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27542/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nautilus/gpio.c: https://review.coreboot.org/#/c/27542/1/src/mainboard/google/poppy/variants… PS1, Line 223: > OC0 and OC1 also don't have external pulls. […] They have 10k external pull-up. Components R672 and R642 in schematics. -- To view, visit https://review.coreboot.org/27542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066 Gerrit-Change-Number: 27542 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Jul 2018 06:21:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2#
by Furquan Shaikh (Code Review) 19 Jul '18

19 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27542 ) Change subject: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2# ...................................................................... Patch Set 1: (1 comment) Can you please upload this change to poppy branch as well? https://review.coreboot.org/#/c/27542/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nautilus/gpio.c: https://review.coreboot.org/#/c/27542/1/src/mainboard/google/poppy/variants… PS1, Line 223: OC0 and OC1 also don't have external pulls. Don't you need internal pulls on those lines? -- To view, visit https://review.coreboot.org/27542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066 Gerrit-Change-Number: 27542 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Jul 2018 06:13:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2#
by Seunghwan Kim (Code Review) 19 Jul '18

19 Jul '18

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/27542 Change subject: mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2# ...................................................................... mb/google/poppy/variants/nautilus: Add internal pull-up for USB2_OC2# Nautilus-WiFi board doesn't have external pull-up on USB2_OC2# route, then abnormal over-current is asserted on USB type-A port. It causes USB type-A port to be blocked, so we need this internal pull-up. BUG=b:111578984 BRANCH=poppy TEST=Verified over-current not triggered abnormally on basic sku board Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/gpio.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27542/1 diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index b496651..8b129d1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -224,8 +224,6 @@ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ PAD_CFG_NC(GPP_E12), /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */ @@ -385,6 +383,8 @@ PAD_CFG_NC(GPP_D16), /* D21 : SPI1_IO2 ==> NC */ PAD_CFG_NC(GPP_D21), + /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ + PAD_CFG_NF(GPP_E11, 5K_PU, DEEP, NF1), }; static const struct pad_config lte_sku_gpio_table[] = { @@ -396,6 +396,8 @@ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D21 : SPI1_IO2 ==> LTE3_BODY_SAR */ PAD_CFG_GPO(GPP_D21, 0, DEEP), + /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), }; const struct pad_config *variant_sku_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/27542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066 Gerrit-Change-Number: 27542 Gerrit-PatchSet: 1 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: mainboard/google/kahlee: Create Liara variant
by Martin Roth (Code Review) 19 Jul '18

19 Jul '18

Martin Roth has removed a vote on this change. Change subject: mainboard/google/kahlee: Create Liara variant ...................................................................... Removed Code-Review+2 by Martin Roth <martinroth(a)google.com> -- To view, visit https://review.coreboot.org/27539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteVote Gerrit-Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Gerrit-Change-Number: 27539 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/kahlee: Create Liara variant
by Martin Roth (Code Review) 19 Jul '18

19 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27539 ) Change subject: mainboard/google/kahlee: Create Liara variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Gerrit-Change-Number: 27539 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Jul 2018 04:00:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cbfstool/add-payload: initialize segment headers to 0
by Joel Kitching (Code Review) 18 Jul '18

18 Jul '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/27540 Change subject: cbfstool/add-payload: initialize segment headers to 0 ...................................................................... cbfstool/add-payload: initialize segment headers to 0 Some types of payload segment headers do not use all fields. If these unused fields are not initialized to 0, they can cause problems in other software which consumes payloads. For example, PAYLOAD_SEGMENT_ENTRY does not use the compression field. If it happens to be a non-existent compression type, the 'cbfstool extract' command fails. BUG=https://ticket.coreboot.org/issues/170 TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86 cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v xxd tianocore.cbfs | head # visually inspect compression field for 0 Change-Id: I359ed117ab4154438bac7172aebf608f7a022552 Signed-off-by: kitching(a)google.com --- M util/cbfstool/cbfs-mkpayload.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27540/1 diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index e26c530..40ee06b 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -130,8 +130,9 @@ segments++; } - /* allocate the segment header array */ + /* Allocate and initialize the segment header array */ segs = calloc(segments, sizeof(*segs)); + memset(segs, 0, segments * sizeof(*segs)); if (segs == NULL) { ret = -1; goto out; @@ -253,6 +254,9 @@ struct cbfs_payload_segment segs[2]; int doffset, len = 0; + /* Initialize the segment header array */ + memset(&segs, 0, sizeof(segs)); + compress = compression_function(algo); if (!compress) return -1; @@ -307,6 +311,9 @@ uint32_t loadaddress = 0; uint32_t entrypoint = 0; + /* Initialize the segment header array */ + memset(&segs, 0, sizeof(segs)); + compress = compression_function(algo); if (!compress) return -1; -- To view, visit https://review.coreboot.org/27540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I359ed117ab4154438bac7172aebf608f7a022552 Gerrit-Change-Number: 27540 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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coreboot-gerrit July 2018