coreboot-gerrit July 2018

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Change in coreboot[master]: google/glados: use level trigger for touchpad interrupt
by Matt DeVillier (Code Review) 19 Jul '18

19 Jul '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27550 Change subject: google/glados: use level trigger for touchpad interrupt ...................................................................... google/glados: use level trigger for touchpad interrupt Coolstar's custom touchpad drivers for Windows require level triggering, and the Linux drivers don't care/perform identically either way. Set touchpad interrupt to level trigger, matching change made to other Chromebooks. Test: boot Windows 10 on google/chell, verify touchpad functional Change-Id: Id5f145b8b24c04f9c6661710a0cda95f135293e9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27550/1 diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index b014025..b9e87a8 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -203,7 +203,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index e6bf073..9ada5c5 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -211,7 +211,7 @@ chip drivers/i2c/generic register "hid" = ""ATML0000"" register "desc" = ""Atmel Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 4a on end end diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 91c7b71..f512f9b 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -218,7 +218,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index b363ad8..3343aa0 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -207,7 +207,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 2c210fe..2472dde 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -212,7 +212,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index daf886c..d552010 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -200,7 +200,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 7ff110e..7a89194 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -209,7 +209,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end -- To view, visit https://review.coreboot.org/27550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id5f145b8b24c04f9c6661710a0cda95f135293e9 Gerrit-Change-Number: 27550 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/glados: enable VMX for all variants
by Matt DeVillier (Code Review) 19 Jul '18

19 Jul '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27549 Change subject: google/glados: enable VMX for all variants ...................................................................... google/glados: enable VMX for all variants Explicitly enable VMX, as some OSes (eg, Windows) need VMX feature enabled and locked in order to fully support virtualization Test: boot Windows 10 on google/chell, verify OS reports virtualization enabled Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb 7 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27549/1 diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index cbd8b01..b014025 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -44,6 +44,7 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index f892187..e6bf073 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -54,6 +54,7 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" # TCC offset register "tcc_offset" = "10" diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 02667a4..91c7b71 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -54,6 +54,7 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index b9d072f..b363ad8 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -54,6 +54,7 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 75e116c..2c210fe 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -54,6 +54,7 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 2eda59b..daf886c 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -42,6 +42,7 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 8af8940..7ff110e 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -44,6 +44,7 @@ register "PmConfigSlpSusMinAssert" = "3" # 4s register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "VmxEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" -- To view, visit https://review.coreboot.org/27549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f Gerrit-Change-Number: 27549 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: cbfstool/extract: ignore compression field for some payload segments
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27520 ) Change subject: cbfstool/extract: ignore compression field for some payload segments ...................................................................... Patch Set 3: Please abandon the CL if not needed anymore -- To view, visit https://review.coreboot.org/27520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8c5c40205d648799ea577ad0c5bee6ec2dd7d05f Gerrit-Change-Number: 27520 Gerrit-PatchSet: 3 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Jul 2018 13:59:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: Add PCI support
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25750 ) Change subject: soc/cavium: Add PCI support ...................................................................... soc/cavium: Add PCI support * Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/cavium/cn8100_sff_evb/devicetree.cb M src/soc/cavium/cn81xx/Kconfig M src/soc/cavium/cn81xx/Makefile.inc A src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/include/soc/addressmap.h A src/soc/cavium/cn81xx/include/soc/ecam0.h M src/soc/cavium/cn81xx/soc.c A src/soc/cavium/common/pci/chip.h 8 files changed, 633 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb index cd495e1..3398e9a 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb +++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb @@ -15,4 +15,196 @@ chip soc/cavium/cn81xx device cpu_cluster 0 on end + + device domain 0 on + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.0 on # PCI bridge + chip soc/cavium/common/pci + register "secure" = "0" + device pci 00.0 on end # MRML + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 00.1 on end # RESET + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 00.2 on end # DAP + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 00.3 on end # MDIO + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 00.4 on end # FUSE + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.2 on end # SGPIO + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.3 on end # SMI + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.4 on end # MMC + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 01.5 on end # KEY + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 01.6 on end # BOOT BUS + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.7 on end # PBUS + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 02.0 on end # XCV + end + device pci 04.0 on end + + chip soc/cavium/common/pci + register "secure" = "0" + device pci 06.0 on end # L2C-TAD + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 07.0 on end # L2C-CBC + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 07.4 on end # L2C-MCI + end + + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.0 on end # UUA0 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.1 on end # UUA1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.2 on end # UUA2 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.3 on end # UUA3 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.4 on end # VRM + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 09.0 on end # I2C0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 09.1 on end # I2C1 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 0a.0 on end # PCC Bridge + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0b.0 on end # IOBN + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 0c.0 on end # OCLA0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 0c.1 on end # OCLA1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0d.0 on end + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0e.0 on end # PCIe0 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0e.1 on end # PCIe1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0e.2 on end # PCIe2 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 10.0 on end # bgx0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 10.1 on end # bgx1 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 11.0 on end # rgx0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 12.0 on end # MAC + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.0 on end # GSER0 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.1 on end # GSER1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.2 on end # GSER2 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.3 on end # GSER3 + end + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 02.0 on end #SMMU + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 03.0 on end #GIC + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 04.0 on end #GTI + end + + device pci 05.0 on end # NIC + device pci 06.0 on end # GPIO + device pci 07.0 on end # SPI + device pci 08.0 on end # MIO + device pci 09.0 on end # PCI bridge + device pci 0a.0 on end # PCI bridge + device pci 0b.0 on end # NFC + device pci 0c.0 on end # PCI bridge + device pci 0d.0 on end # PCM + device pci 0e.0 on end # VRM + device pci 0f.0 on end # PCI bridge + + device pci 10.0 on end # USB0 + device pci 11.0 on end # USB1 + device pci 16.0 on end # SATA0 + device pci 17.0 on end # SATA1 + end + end end diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 9cc7b48..3191ef3 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -12,6 +12,8 @@ select UART_OVERRIDE_REFCLK select SOC_CAVIUM_COMMON select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS + select MMCONF_SUPPORT + select PCI if SOC_CAVIUM_CN81XX @@ -25,4 +27,7 @@ config STACK_SIZE default 0x2000 +config MMCONF_BASE_ADDRESS + default 0x848000000000 + endif diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 16aa4ff..b2de484 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -63,6 +63,7 @@ ramstage-y += soc.c ramstage-y += cpu.c ramstage-y += cpu_secondary.S +ramstage-y += ecam0.c # BDK coreboot interface ramstage-y += ../common/bdk-coreboot.c diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c new file mode 100644 index 0000000..cff2507 --- /dev/null +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -0,0 +1,374 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. <support(a)cavium.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <soc/addressmap.h> +#include <soc/cavium/common/pci/chip.h> +#include <assert.h> + +#define CAVM_PCCPF_XXX_VSEC_CTL 0x108 +#define CAVM_PCCPF_XXX_VSEC_SCTL 0x10c + +/* + * Hide PCI device function on BUS 1 in non secure world. + */ +static void disable_func(unsigned int devfn) +{ + u64 *addr; + printk(BIOS_DEBUG, "PCI: 01:%02x.%x is secure\n", devfn >> 3, + devfn & 7); + + /* disable function */ + addr = (void *)ECAM0_RSLX_SDIS; + u64 reg = read64(&addr[devfn]); + reg &= ~3; + reg |= 2; + write64(&addr[devfn], reg); +} + +/* + * Show PCI device function on BUS 1 in non secure world. + */ +static void enable_func(unsigned int devfn) +{ + u64 *addr; + + printk(BIOS_DEBUG, "PCI: 01:%02x.%x is insecure\n", devfn >> 3, + devfn & 7); + + /* enable function */ + addr = (void *)ECAM0_RSLX_SDIS; + u64 reg = read64(&addr[devfn]); + reg &= ~3; + write64(&addr[devfn], reg); + + addr = (void *)ECAM0_RSLX_NSDIS; + reg = read64(&addr[devfn]); + reg &= ~1; + write64(&addr[devfn], reg); +} + +/* + * Hide PCI device on BUS 0 in non secure world. + */ +static void disable_device(unsigned int dev) +{ + u64 *addr; + + printk(BIOS_DEBUG, "PCI: 00:%02x.0 is secure\n", dev); + + /* disable function */ + addr = (void *)ECAM0_DEVX_SDIS; + u64 reg = read64(&addr[dev]); + reg &= ~3; + write64(&addr[dev], reg); + + addr = (void *)ECAM0_DEVX_NSDIS; + reg = read64(&addr[dev]); + reg |= 1; + write64(&addr[dev], reg); +} + +/* + * Show PCI device on BUS 0 in non secure world. + */ +static void enable_device(unsigned int dev) +{ + u64 *addr; + + printk(BIOS_DEBUG, "PCI: 00:%02x.0 is insecure\n", dev); + + /* enable function */ + addr = (void *)ECAM0_DEVX_SDIS; + u64 reg = read64(&addr[dev]); + reg &= ~3; + write64(&addr[dev], reg); + + addr = (void *)ECAM0_DEVX_NSDIS; + reg = read64(&addr[dev]); + reg &= ~1; + write64(&addr[dev], reg); +} + +static void ecam0_read_resources(struct device *dev) +{ + /* There are no dynamic PCI resources on Cavium SoC */ +} + +static void ecam0_fix_missing_devices(struct bus *link) +{ + size_t i; + + /** + * Cavium thinks it's a good idea to violate the PCI spec. + * Disabled multi-function PCI devices might have active functions. + * Add devices here manually, as coreboot's PCI allocator won't find + * them otherwise... + */ + for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { + struct device_path pci_path; + struct device *child; + + pci_path.type = DEVICE_PATH_PCI; + pci_path.pci.devfn = i; + + child = find_dev_path(link, &pci_path); + if (!child) + pci_probe_dev(NULL, link, i); + } +} + +/** + * Get PCI BAR address from cavium specific extended capability. + * Use regular BAR if not found in extended capability space. + * + * @return The pyhsical address of the BAR, zero on error + */ +static uint64_t get_bar_val(struct device *dev, u8 bar) +{ + size_t cap_offset = pci_find_capability(dev, 0x14); + uint64_t h, l, ret = 0; + if (cap_offset) { + /* Found EA */ + u8 es, bei; + u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f; + + cap_offset += 4; + while (ne) { + uint32_t dw0 = pci_read_config32(dev, cap_offset); + + es = dw0 & 7; + bei = (dw0 >> 4) & 0xf; + if (bei == bar) { + h = 0; + l = pci_read_config32(dev, cap_offset + 4); + if (l & 2) + h = pci_read_config32(dev, + cap_offset + 12); + ret = (h << 32) | (l & ~0xfull); + break; + } + cap_offset += (es + 1) * 4; + ne--; + } + } else { + h = 0; + l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0); + if (l & 4) + h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0 + + 4); + ret = (h << 32) | (l & ~0xfull); + } + return ret; +} + +/** + * pci_enable_msix - configure device's MSI-X capability structure + * @dev: pointer to the pci_dev data structure of MSI-X device function + * @entries: pointer to an array of MSI-X entries + * @nvec: number of MSI-X irqs requested for allocation by device driver + * + * Setup the MSI-X capability structure of device function with the number + * of requested irqs upon its software driver call to request for + * MSI-X mode enabled on its hardware device function. A return of zero + * indicates the successful configuration of MSI-X capability structure. + * A return of < 0 indicates a failure. + * Or a return of > 0 indicates that driver request is exceeding the number + * of irqs or MSI-X vectors available. Driver should use the returned value to + * re-send its request. + **/ +static size_t ecam0_pci_enable_msix(struct device *dev, + struct msix_entry *entries, size_t nvec) +{ + struct msix_entry *msixtable; + u32 offset; + u8 bar_idx; + u64 bar; + size_t nr_entries; + size_t i; + u16 control; + + if (!entries) { + printk(BIOS_ERR, "%s: No entries specified\n", __func__); + return -1; + } + + const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); + if (!pos) { + printk(BIOS_ERR, "%s: Device not MSI-X capable\n", + dev_path(dev)); + return -1; + } + nr_entries = pci_msix_table_size(dev); + if (nvec > nr_entries) { + printk(BIOS_ERR, "ERROR: %s: Specified to many table entries\n", + dev_path(dev)); + return nr_entries; + } + + /* Ensure MSI-X is disabled while it is set up */ + control = pci_read_config16(dev, pos + PCI_MSIX_FLAGS); + control &= ~PCI_MSIX_FLAGS_ENABLE; + pci_write_config16(dev, pos + PCI_MSIX_FLAGS, control); + + /* Find MSI-X table region */ + offset = 0; + bar_idx = 0; + if (pci_msix_table_bar(dev, &offset, &bar_idx)) { + printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X entry\n", + dev_path(dev)); + return -1; + } + bar = get_bar_val(dev, bar_idx); + if (!bar) { + printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X bar\n", + dev_path(dev)); + return -1; + } + msixtable = (struct msix_entry *)((void *)bar + offset); + + /* + * Some devices require MSI-X to be enabled before we can touch the + * MSI-X registers. We need to mask all the vectors to prevent + * interrupts coming in before they're fully set up. + */ + control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; + pci_write_config16(dev, pos + PCI_MSIX_FLAGS, control); + + for (i = 0; i < nvec; i++) { + write64(&msixtable[i].addr, entries[i].addr); + write32(&msixtable[i].data, entries[i].data); + write32(&msixtable[i].vec_control, entries[i].vec_control); + } + + control &= ~PCI_MSIX_FLAGS_MASKALL; + pci_write_config16(dev, pos + PCI_MSIX_FLAGS, control); + + return 0; +} + +static void ecam0_init(struct device *dev) +{ + struct soc_cavium_common_pci_config *config; + struct device *child, *child_last; + size_t i; + u32 reg32; + + printk(BIOS_INFO, "ECAM0: init\n"); + const struct device *bridge = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (!bridge) { + printk(BIOS_INFO, "ECAM0: ERROR: PCI 00:01.0 not found.\n"); + return; + } + /** + * Search for missing devices on BUS 1. + * Only required for ARI capability programming. + */ + ecam0_fix_missing_devices(bridge->link_list); + + /* Program secure ARI capability on bus 1 */ + child_last = NULL; + for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { + child = dev_find_slot(bridge->link_list->secondary, i); + if (!child || !child->enabled) + continue; + + if (child_last) { + /* Program ARI capability of the previous device */ + reg32 = pci_read_config32(child_last, + CAVM_PCCPF_XXX_VSEC_SCTL); + reg32 &= ~(0xffU << 24); + reg32 |= child->path.pci.devfn << 24; + pci_write_config32(child_last, CAVM_PCCPF_XXX_VSEC_SCTL, + reg32); + } + child_last = child; + } + + /* Program insecure ARI capability on bus 1 */ + child_last = NULL; + for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { + child = dev_find_slot(bridge->link_list->secondary, i); + if (!child) + continue; + config = child->chip_info; + if (!child->enabled || (config && config->secure)) + continue; + + if (child_last) { + /* Program ARI capability of the previous device */ + reg32 = pci_read_config32(child_last, + CAVM_PCCPF_XXX_VSEC_CTL); + reg32 &= ~(0xffU << 24); + reg32 |= child->path.pci.devfn << 24; + pci_write_config32(child_last, CAVM_PCCPF_XXX_VSEC_CTL, + reg32); + } + child_last = child; + } + + /* Enable / disable devices on bus 0 */ + for (i = 0; i <= 0x1f; i++) { + child = dev_find_slot(0, PCI_DEVFN(i, 0)); + config = child ? child->chip_info : NULL; + if (child && child->enabled && config && !config->secure) + enable_device(i); + else + disable_device(i); + } + + /* Enable / disable devices and functions on bus 1 */ + for (i = 0; i <= PCI_DEVFN(0x1f, 7); i++) { + child = dev_find_slot(bridge->link_list->secondary, i); + config = child ? child->chip_info : NULL; + if (child && child->enabled && + ((config && !config->secure) || !config)) + enable_func(i); + else + disable_func(i); + } + + /* Apply IRQ on PCI devices */ + /* UUA */ + for (i = 0; i < 4; i++) { + child = dev_find_slot(bridge->link_list->secondary, + PCI_DEVFN(8, i)); + if (!child) + continue; + + struct msix_entry entry[2] = { + {.addr = CAVM_GICD_SETSPI_NSR, .data = 37 + i}, + {.addr = CAVM_GICD_CLRSPI_NSR, .data = 37 + i}, + }; + + ecam0_pci_enable_msix(child, entry, 2); + } + + printk(BIOS_INFO, "ECAM0: done\n"); +} + +struct device_operations pci_domain_ops_ecam0 = { + .set_resources = NULL, + .enable_resources = NULL, + .read_resources = ecam0_read_resources, + .init = ecam0_init, + .scan_bus = pci_domain_scan_bus, +}; diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index 938dd32..392c93f 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -52,6 +52,10 @@ /* PCC */ #define ECAM_PF_BAR2 0x848000000000ULL +#define ECAM0_DEVX_NSDIS 0x87e048070000ULL +#define ECAM0_DEVX_SDIS 0x87e048060000ULL +#define ECAM0_RSLX_NSDIS 0x87e048050000ULL +#define ECAM0_RSLX_SDIS 0x87e048040000ULL /* CPT */ /* SLI */ @@ -102,6 +106,8 @@ ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \ (0x87E028000000ULL + ((x) << 24)) : 0) +#define CAVM_GICD_SETSPI_NSR 0x801000000040ULL +#define CAVM_GICD_CLRSPI_NSR 0x801000000048ULL /* TWSI */ #define MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24)) diff --git a/src/soc/cavium/cn81xx/include/soc/ecam0.h b/src/soc/cavium/cn81xx/include/soc/ecam0.h new file mode 100644 index 0000000..1cc249d --- /dev/null +++ b/src/soc/cavium/cn81xx/include/soc/ecam0.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM0_H +#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM0_H + +extern struct device_operations pci_domain_ops_ecam0; + +#endif diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 6c68bb2..5e540a6 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -29,6 +29,7 @@ #include <string.h> #include <symbols.h> #include <libbdk-boot/bdk-boot.h> +#include <soc/ecam0.h> static void soc_read_resources(device_t dev) { @@ -59,7 +60,12 @@ static void enable_soc_dev(device_t dev) { - dev->ops = &soc_ops; + if (dev->path.type == DEVICE_PATH_DOMAIN && + dev->path.domain.domain == 0) { + dev->ops = &pci_domain_ops_ecam0; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &soc_ops; + } } struct chip_operations soc_cavium_cn81xx_ops = { diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h new file mode 100644 index 0000000..0d0d33f --- /dev/null +++ b/src/soc/cavium/common/pci/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H +#define __SOC_CAVIUM_COMMON_PCI_CHIP_H + +struct soc_cavium_common_pci_config { + /** + * Mark the PCI device as secure. + * It will be visible from EL3, but hidden in EL2-0. + */ + u8 secure; +}; + +#endif /* __SOC_CAVIUM_COMMON_PCI_CHIP_H */ -- To view, visit https://review.coreboot.org/25750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Gerrit-Change-Number: 25750 Gerrit-PatchSet: 29 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: soc/cavium: Add PCI support
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25750 ) Change subject: soc/cavium: Add PCI support ...................................................................... Patch Set 28: Code-Review+2 -- To view, visit https://review.coreboot.org/25750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Gerrit-Change-Number: 25750 Gerrit-PatchSet: 28 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 19 Jul 2018 13:57:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: payloads/LinuxBoot: Add ARM64 support
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25152 ) Change subject: payloads/LinuxBoot: Add ARM64 support ...................................................................... payloads/LinuxBoot: Add ARM64 support Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures. * Always compress kernel Image using xz * Create FIT uImage containing the kernel, initramfs and DTB * Add ARM64 defconfig for all SoCs Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/25152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile A payloads/external/LinuxBoot/arm64/defconfig A payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.inc 7 files changed, 547 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 74e6c94..24d44cf 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -20,19 +20,30 @@ config LINUXBOOT_X86_64 bool "x86_64" + depends on ARCH_X86 help AMD64 kernel and initramfs config LINUXBOOT_X86 bool "x86" + depends on ARCH_X86 help X86 kernel and initramfs + +config LINUXBOOT_ARM64 + bool "arm64" + depends on ARCH_ARM64 + select PAYLOAD_FIT_SUPPORT + help + AARCH64 kernel and initramfs + endchoice config LINUXBOOT_ARCH string default "amd64" if LINUXBOOT_X86_64 default "386" if LINUXBOOT_X86 + default "arm64" if LINUXBOOT_ARM64 choice prompt "Kernel version" @@ -61,6 +72,11 @@ help Add your own kernel command-line arguments. +config LINUXBOOT_DTB_FILE + string "Compiled devicetree file" + depends on LINUXBOOT_ARM64 + default "" + config PAYLOAD_FILE default "payloads/external/LinuxBoot/linuxboot/kernel-image" @@ -106,8 +122,11 @@ initramfs. config PAYLOAD_USERSPACE - string "" + string "LinuxBoot initramfs" default "payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz" + help + The initramfs to use with the compiled kernel. + Useful for debugging or custom initramfs. endif endif diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name index b7b1085..18438c7 100644 --- a/payloads/external/LinuxBoot/Kconfig.name +++ b/payloads/external/LinuxBoot/Kconfig.name @@ -14,7 +14,7 @@ config PAYLOAD_LINUXBOOT bool "LinuxBoot" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_ARM64 help Select this option if you want to build a coreboot image with a LinuxBoot payload. If you don't know what this is diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 10ad0c3..651e982 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -17,9 +17,30 @@ kernel_dir=$(project_dir)/kernel unexport $(COREBOOT_EXPORTS) +unexport MAKEFLAGS + +XGCCPATH?=$(PWD)/util/crossgcc/xgcc/bin +ifeq ($(CONFIG_LINUXBOOT_ARCH),386) +CROSS_COMPILE?=$(XGCCPATH)/i386-linux- +ARCH?=x86 +else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) +CROSS_COMPILE?=$(XGCCPATH)/x86_64-linux- +ARCH?=x86_64 +else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) +CROSS_COMPILE?=$(XGCCPATH)/aarch64-linux- +ARCH?=arm64 +endif + +OBJCOPY:=$(CROSS_COMPILE)objcopy all: payload +toolchain: + if [[ ! -x "$(CROSS_COMPILE)gcc" ]]; then \ + echo "Toolchain '$(CROSS_COMPILE)*' is missing."; \ + exit 1; \ + fi + $(kernel_dir)/.config: echo " WWW Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)" mkdir -p $(kernel_dir) @@ -36,23 +57,47 @@ cp x86/defconfig $(kernel_dir)/.config else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) cp x86_64/defconfig $(kernel_dir)/.config +else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) + cp arm64/defconfig $(kernel_dir)/.config endif -$(project_dir)/kernel-image: config +ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64)) +$(kernel_dir)/arch/x86/boot/bzImage: config toolchain +else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) +$(kernel_dir)/vmlinux: config toolchain +endif echo " MAKE Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)" - $(MAKE) -C $(kernel_dir) olddefconfig - $(MAKE) -C $(kernel_dir) -j $(CPUS) -ifeq ($(CONFIG_LINUXBOOT_ARCH),386) - cp $(kernel_dir)/arch/x86/boot/bzImage $(project_dir)/kernel-image -else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) - cp $(kernel_dir)/arch/x86/boot/bzImage $(project_dir)/kernel-image + $(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) + $(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) + +ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64)) +$(project_dir)/kernel-image: $(kernel_dir)/arch/x86/boot/bzImage + cp $< $@ +else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) +$(project_dir)/vmlinux.bin: $(kernel_dir)/vmlinux + $(OBJCOPY) -O binary $< $@ + +$(project_dir)/target.dtb: $(CONFIG_LINUXBOOT_DTB_FILE) + cp $< $@ + +$(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin + xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@ + +$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(project_dir)/initramfs.cpio.xz + cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir) + mkimage -f $(project_dir)/kernel_fdt_lzma.its $@ endif -payload: $(project_dir)/kernel-image ifeq ($(CONFIG_LINUXBOOT_UROOT),y) +$(project_dir)/initramfs.cpio.xz: $(MAKE) -f targets/u-root.mk +else +$(project_dir)/initramfs.cpio.xz: + echo "Building without u-root support" endif +payload: $(project_dir)/kernel-image $(project_dir)/initramfs.cpio.xz + clean: if [ -d "$(kernel_dir)" ]; then make -C $(kernel_dir) clean; fi rm -f $(project_dir)/initramfs.cpio.xz @@ -60,4 +105,4 @@ distclean: rm -rf $(project_dir) -.PHONY: config patch payload clean distclean clone fetch all +.PHONY: config patch payload clean distclean clone fetch all toolchain diff --git a/payloads/external/LinuxBoot/arm64/defconfig b/payloads/external/LinuxBoot/arm64/defconfig new file mode 100644 index 0000000..6f68019 --- /dev/null +++ b/payloads/external/LinuxBoot/arm64/defconfig @@ -0,0 +1,383 @@ +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_NUMA_BALANCING=y +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_DEBUG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_JUMP_LABEL=y +CONFIG_CC_STACKPROTECTOR_NONE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEBUG_FS is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_ARCH_ACTIONS=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_ALPINE=y +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_IPROC=y +CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_EXYNOS=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_LG1K=y +CONFIG_ARCH_HISI=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MESON=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_REALTEK=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SEATTLE=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_R8A7795=y +CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_R8A77970=y +CONFIG_ARCH_R8A77995=y +CONFIG_ARCH_STRATIX10=y +CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_SPRD=y +CONFIG_ARCH_THUNDER=y +CONFIG_ARCH_THUNDER2=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_XGENE=y +CONFIG_ARCH_ZX=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_PCI=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_NUMA=y +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_KSM=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_KEXEC=y +# CONFIG_EFI is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_BINFMT_SCRIPT is not set +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_TLS=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_SYN_COOKIES=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_DEVLINK=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EXTRA_FIRMWARE="cpt8x-mc-ae.out cpt8x-mc-se.out" +CONFIG_DMA_CMA=y +CONFIG_MTD=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_FC=y +CONFIG_SRAM=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SCSI_VIRTIO=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_ATA_BMDMA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_THUNDER_NIC_PF=y +CONFIG_THUNDER_NIC_VF=y +CONFIG_LIQUIDIO=y +CONFIG_LIQUIDIO_VF=y +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +CONFIG_MDIO_OCTEON=y +CONFIG_AQUANTIA_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_VITESSE_PHY=y +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_WLAN is not set +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_MISC=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_UNIPHIER=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_UNIPHIER_F=y +CONFIG_I2C_THUNDERX=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_SLAVE=y +CONFIG_SPI=y +CONFIG_SPI_THUNDERX=y +# CONFIG_PINCTRL_UNIPHIER is not set +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_THUNDERX=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_MAX77620=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_BQ27XXX=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SOFT_WATCHDOG=y +CONFIG_XILINX_WATCHDOG=y +CONFIG_ZIIRAVE_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_CADENCE_WATCHDOG=y +CONFIG_MAX77620_WATCHDOG=y +CONFIG_UNIPHIER_WATCHDOG=y +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_RK808=y +CONFIG_MFD_SEC_CORE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_VGA_ARB is not set +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_SERIAL=y +CONFIG_MMC=y +CONFIG_SDIO_UART=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_CAVIUM_THUNDERX=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_ISL12022=y +CONFIG_SYNC_FILE=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_CLK_QORIQ=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_PHY_XGENE=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_GOOGLE_FIRMWARE=y +CONFIG_GOOGLE_COREBOOT_TABLE_OF=y +CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y +CONFIG_GOOGLE_VPD=y +CONFIG_EXT3_FS=y +CONFIG_XFS_FS=y +CONFIG_BTRFS_FS=y +CONFIG_F2FS_FS=y +CONFIG_FS_DAX=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_ISO9660_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=5 +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_MEMTEST=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_KEYS=y +CONFIG_SECURITY=y +# CONFIG_INTEGRITY is not set +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_ANSI_CPRNG=y +# CONFIG_CRYPTO_DEV_VIRTIO is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS7_MESSAGE_PARSER=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA512_ARM64=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRC32_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y diff --git a/payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its b/payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its new file mode 100644 index 0000000..50f6a2f --- /dev/null +++ b/payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its @@ -0,0 +1,74 @@ +/* + * Simple U-Boot uImage source file containing a single kernel and FDT blob + */ + +/dts-v1/; + +/ { + description = "Simple image with single Linux kernel and FDT blob"; + #address-cells = <1>; + + images { + kernel { + description = "Vanilla Linux kernel"; + data = /incbin/("vmlinux.bin.lzma"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "lzma"; + load = <0x80000>; + entry = <0x80000>; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha1"; + }; + hash-3 { + algo = "sha256"; + }; + }; + fdt-1 { + description = "Flattened Device Tree blob"; + data = /incbin/("target.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha1"; + }; + hash-3 { + algo = "sha256"; + }; + }; + ramdisk-1 { + description = "Compressed Initramfs"; + data = /incbin/("initramfs.cpio.xz"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "none"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "sha1"; + }; + hash-2 { + algo = "sha256"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Boot Linux kernel with FDT blob"; + kernel = "kernel"; + fdt = "fdt-1"; + ramdisk = "ramdisk-1"; + }; + }; +}; diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index 9b0e568..4c2994c 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -52,8 +52,11 @@ done;,true;) \ fi -$(project_dir)/initramfs.cpio.xz: checkout - cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) go build u-root.go +$(uroot_dir)/u-root: $(uroot_dir)/u-root.go + echo " GO u-root" + cd $(uroot_dir); GOPATH=$(go_path_dir) go build u-root.go + +$(project_dir)/initramfs.cpio.xz: checkout $(uroot_dir)/u-root echo " MAKE u-root $(CONFIG_LINUXBOOT_UROOT_VERSION)" ifneq ($(CONFIG_LINUXBOOT_UROOT_COMMANDS),) ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 1d3e7a1..973bdfb 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -33,10 +33,14 @@ endif ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y) -ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE))),) + ifeq ($(CONFIG_ARCH_X86),y) + ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE))),) ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE) -endif -ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_PAYLOAD_USERSPACE) + endif + ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_USERSPACE))),) + ADDITIONAL_PAYLOAD_CONFIG+=-I $(strip $(call strip_quotes,$(CONFIG_PAYLOAD_USERSPACE))) + endif + endif endif ifeq ($(CONFIG_PAYLOAD_LINUX),y) @@ -259,16 +263,6 @@ linuxboot: $(MAKE) -C payloads/external/LinuxBoot \ - HOSTCC="$(HOSTCC)" \ - CC="$(HOSTCC)" \ - GCC_CC_x86_32=$(GCC_CC_x86_32) \ - GCC_CC_x86_64=$(GCC_CC_x86_64) \ - GCC_CC_arm=$(GCC_CC_arm) \ - GCC_CC_arm64=$(GCC_CC_arm64) \ - OBJCOPY_x86_32=$(OBJCOPY_x86_32) \ - OBJCOPY_x86_64=$(OBJCOPY_x86_64) \ - OBJCOPY_arm=$(OBJCOPY_arm) \ - OBJCOPY_arm64=$(OBJCOPY_arm64) \ CPUS=$(CPUS) \ CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \ CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \ @@ -277,7 +271,9 @@ CONFIG_LINUXBOOT_UROOT_COMMANDS="$(CONFIG_LINUXBOOT_UROOT_COMMANDS)" \ CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \ CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \ - CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) + CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \ + CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE) + payloads/external/LinuxBoot/linuxboot/kernel-image: linuxboot payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot -- To view, visit https://review.coreboot.org/25152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c Gerrit-Change-Number: 25152 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: payloads/LinuxBoot: Add ARM64 support
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25152 ) Change subject: payloads/LinuxBoot: Add ARM64 support ...................................................................... Patch Set 7: Code-Review+2 If needed we can do follow ups. -- To view, visit https://review.coreboot.org/25152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c Gerrit-Change-Number: 25152 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Jul 2018 13:54:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: device/pci: Add MSI-X helper functions
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/26329 ) Change subject: device/pci: Add MSI-X helper functions ...................................................................... device/pci: Add MSI-X helper functions Basic PCI MSI-X table helper functions. Imported from GNU/Linux kernel PCI subsystem. To be used on Cavium to configure MSI-X tables. Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/26329 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/pci_device.c M src/include/device/pci.h M src/include/device/pci_def.h 3 files changed, 98 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/device/pci_device.c b/src/device/pci_device.c index c18f529..5938389 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -338,6 +338,74 @@ } /** + * Given a device, read the size of the MSI-X table. + * + * @param dev Pointer to the device structure. + * @return MSI-X table size or 0 if not MSI-X capable device + */ +size_t pci_msix_table_size(struct device *dev) +{ + const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); + if (!pos) + return 0; + + const u16 control = pci_read_config16(dev, pos + PCI_MSIX_FLAGS); + return (control & PCI_MSIX_FLAGS_QSIZE) + 1; +} + +/** + * Given a device, return the table offset and bar the MSI-X tables resides in. + * + * @param dev Pointer to the device structure. + * @param offset Returned value gives the offset in bytes inside the PCI BAR. + * @param idx The returned value is the index of the PCI_BASE_ADDRESS register + * the MSI-X table is located in. + * @return Zero on success + */ +int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx) +{ + const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); + if (!pos || !offset || !idx) + return 1; + + *offset = pci_read_config32(dev, pos + PCI_MSIX_TABLE); + *idx = (u8)(*offset & PCI_MSIX_PBA_BIR); + *offset &= PCI_MSIX_PBA_OFFSET; + + return 0; +} + +/** + * Given a device, return a msix_entry pointer or NULL if no table was found. + * + * @param dev Pointer to the device structure. + * + * @return NULL on error + */ +struct msix_entry *pci_msix_get_table(struct device *dev) +{ + struct resource *res; + u32 offset; + u8 idx; + + if (pci_msix_table_bar(dev, &offset, &idx)) + return NULL; + + if (idx > 5) + return NULL; + + res = probe_resource(dev, idx * 4 + PCI_BASE_ADDRESS_0); + if (!res || !res->base || offset >= res->size) + return NULL; + + if ((res->flags & IORESOURCE_PCI64) && + (uintptr_t)res->base != res->base) + return NULL; + + return (struct msix_entry *)((uintptr_t)res->base + offset); +} + +/** * Read the base address registers for a given device. * * @param dev Pointer to the dev structure. diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 3cc2c64..f1ab91b 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -56,6 +56,20 @@ const unsigned short *devices; }; +struct msix_entry { + union { + struct { + u32 lower_addr; + u32 upper_addr; + }; + struct { + u64 addr; + }; + }; + u32 data; + u32 vec_control; +}; + #ifdef __SIMPLE_DEVICE__ #define __pci_driver __attribute__((unused)) #else @@ -104,6 +118,10 @@ const char *get_pci_class_name(struct device *dev); const char *get_pci_subclass_name(struct device *dev); +size_t pci_msix_table_size(struct device *dev); +int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); +struct msix_entry *pci_msix_get_table(struct device *dev); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 60d9132..f9ce1a6 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -292,6 +292,18 @@ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ #define PCI_MSI_MASK_BIT 16 /* Mask bits register */ +/* MSI-X registers */ +#define PCI_MSIX_FLAGS 2 +#define PCI_MSIX_FLAGS_QSIZE 0x7FF /* table size */ +#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ +#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ +#define PCI_MSIX_TABLE 4 /* Table offset */ +#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ +#define PCI_MSIX_PBA_BIR 0x7 /* BAR index */ +#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */ +#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ + + /* CompactPCI Hotswap Register */ #define PCI_CHSWP_CSR 2 /* Control and Status Register */ -- To view, visit https://review.coreboot.org/26329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Gerrit-Change-Number: 26329 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: device/pci: Add MSI-X helper functions
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/26329 ) Change subject: device/pci: Add MSI-X helper functions ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/26329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Gerrit-Change-Number: 26329 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 19 Jul 2018 13:52:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/smbios: Add support for table 38
by Philipp Deppenwiese (Code Review) 19 Jul '18

19 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25386 ) Change subject: arch/x86/smbios: Add support for table 38 ...................................................................... arch/x86/smbios: Add support for table 38 Add support for SMBIOS table 'IPMI Device Information' and use it on HP Compaq 8200 Elite SFF. Tested on HP Compaq 8200. dmidecode prints the table and sensors-detect scans for IPMI compatible devices. Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/25386 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/hp/compaq_8200_elite_sff/mainboard.c 3 files changed, 67 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index da1b711..582ae8d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, * Raptor Engineering * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -629,6 +630,33 @@ return len; } +int smbios_write_type38(unsigned long *current, int *handle, + const enum smbios_bmc_interface_type interface_type, + const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr, + const u64 base_addr, const u8 base_modifier, + const u8 irq) +{ + struct smbios_type38 *t = (struct smbios_type38 *)*current; + int len = sizeof(struct smbios_type38); + + memset(t, 0, sizeof(struct smbios_type38)); + t->type = SMBIOS_IPMI_DEVICE_INFORMATION; + t->handle = *handle; + t->length = len - 2; + t->interface_type = interface_type; + t->ipmi_rev = ipmi_rev; + t->i2c_slave_addr = i2c_addr; + t->nv_storage_addr = nv_addr; + t->base_address = base_addr; + t->base_address_modifier = base_modifier; + t->irq = irq; + + *current += len; + *handle += 1; + + return len; +} + int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, u8 bus, u8 device, u8 function) diff --git a/src/include/smbios.h b/src/include/smbios.h index 8fe507e..631a1a5 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -26,6 +26,12 @@ int smbios_string_table_len(u8 *start); /* Used by mainboard to add an on-board device */ +enum smbios_bmc_interface_type; +int smbios_write_type38(unsigned long *current, int *handle, + const enum smbios_bmc_interface_type interface_type, + const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr, + const u64 base_addr, const u8 base_modifier, + const u8 irq); int smbios_write_type41(unsigned long *current, int *handle, const char *name, u8 instance, u16 segment, u8 bus, u8 device, u8 function); @@ -216,6 +222,7 @@ SMBIOS_MEMORY_DEVICE = 17, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19, SMBIOS_SYSTEM_BOOT_INFORMATION = 32, + SMBIOS_IPMI_DEVICE_INFORMATION = 38, SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, SMBIOS_END_OF_TABLE = 127, } smbios_struct_type_t; @@ -497,6 +504,13 @@ u8 irq; } __packed; +enum smbios_bmc_interface_type { + SMBIOS_BMC_INTERFACE_UNKNOWN = 0, + SMBIOS_BMC_INTERFACE_KCS, + SMBIOS_BMC_INTERFACE_SMIC, + SMBIOS_BMC_INTERFACE_BLOCK, +}; + typedef enum { SMBIOS_DEVICE_TYPE_OTHER = 0x01, SMBIOS_DEVICE_TYPE_UNKNOWN, diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c index 527b0d1..a1b5a09 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c @@ -17,12 +17,37 @@ #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + 0, // IO port interface address + 0, + 0); // no IRQ + + return len; +} +#endif static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/25386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e Gerrit-Change-Number: 25386 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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