coreboot-gerrit July 2018

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Change in coreboot[master]: soc/cavium: Enable DRAM test
by build bot (Jenkins) (Code Review) 20 Jul '18

20 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27103 ) Change subject: soc/cavium: Enable DRAM test ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/27103/7/src/soc/cavium/cn81xx/sdram.c File src/soc/cavium/cn81xx/sdram.c: https://review.coreboot.org/#/c/27103/7/src/soc/cavium/cn81xx/sdram.c@93 PS7, Line 93: if (0 != bdk_numa_master()) Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27103/7/src/soc/cavium/cn81xx/sdram.c@97 PS7, Line 97: if (0 == bdk_numa_master()) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Gerrit-Change-Number: 27103 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Jul 2018 09:06:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by build bot (Jenkins) (Code Review) 20 Jul '18

20 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25382 ) Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... Patch Set 40: (4 comments) https://review.coreboot.org/#/c/25382/40/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25382/40/src/soc/cavium/cn81xx/soc.c@78 PS40, Line 78: Remove 'phy-handle' if this option is not availble */ 'availble' may be misspelled - perhaps 'available'? https://review.coreboot.org/#/c/25382/40/src/soc/cavium/cn81xx/soc.c@136 PS40, Line 136: /* Extract our MAC address info so we can assign them in the device tree */ line over 80 characters https://review.coreboot.org/#/c/25382/40/src/soc/cavium/cn81xx/soc.c@168 PS40, Line 168: if (!strcmp(name, prop->prop.name)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25382/40/src/soc/cavium/cn81xx/soc.c@264 PS40, Line 264: BDK_BGXX_CMRX_RX_DMAC_CTL(bgx_interface, bgx_index)); line over 80 characters -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 40 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Jul 2018 09:06:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 20 Jul '18

20 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep/acpi.c: Add Netburst CPUs ...................................................................... Patch Set 14: (13 comments) https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/acpi.c@68 PS14, Line 68: if ( c.x86_model ==2) spaces required around that '==' (ctx:WxV) https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/acpi.c@68 PS14, Line 68: if ( c.x86_model ==2) space prohibited after that open parenthesis '(' https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/acpi.c@92 PS14, Line 92: else else is not generally useful after a break or return https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 45: if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and line over 80 characters https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 46: enabled bits */ line over 80 characters https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 48: params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); line over 80 characters https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 52: } code indent should use tabs where possible https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 52: } please, no spaces at the start of a line https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 73: if (!(((cpuid_eax(1) >> 8) & 0xf) == 0xf)) { suspect code indent for conditional statements (8, 8) https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 77: !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { line over 80 characters https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 79: params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); line over 80 characters https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 82: } code indent should use tabs where possible https://review.coreboot.org/#/c/22604/14/src/cpu/intel/speedstep/speedstep.… PS14, Line 82: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Jul 2018 09:06:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arch/arm64: Add Kconfig to include BL31 as blob
by Patrick Rudolph (Code Review) 20 Jul '18

20 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27559 Change subject: arch/arm64: Add Kconfig to include BL31 as blob ...................................................................... arch/arm64: Add Kconfig to include BL31 as blob Add Kconfig options to not build the ATF, but use a precompiled binary instead. To be used on platforms that do not have upstream ATF support. Change-Id: I17954247029df627a3f4db8b73993bd549e55967 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/arm64/Kconfig M src/arch/arm64/Makefile.inc 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/27559/1 diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index cae558b..2ce9f68 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -31,6 +31,20 @@ default n depends on ARCH_RAMSTAGE_ARM64 +config ARM64_BUILD_ARM_TRUSTED_FIRMWARE + bool + default y + depends on ARM64_USE_ARM_TRUSTED_FIRMWARE + help + If false include bl31.elf from blobs repo. + +config ARM64_BL31_BLOB + string "Precompiled BL31.ELF to use as ATF" + depends on ARM64_USE_ARM_TRUSTED_FIRMWARE + depends on !ARM64_BUILD_ARM_TRUSTED_FIRMWARE + help + The blob to use if not building the ATF in tree. + config ARM64_USE_SECURE_OS bool default n diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 3c3cd20..12c7392 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -156,6 +156,8 @@ ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifeq ($(CONFIG_ARM64_BUILD_ARM_TRUSTED_FIRMWARE), y) + BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware BL31_BUILD := $(abspath $(obj)/3rdparty/arm-trusted-firmware) BL31_TARGET := $(BL31_BUILD)/bl31/bl31.elf @@ -205,6 +207,13 @@ .PHONY: $(BL31) +else + +BL31 := $(call strip_quotes,$(CONFIG_ARM64_BL31_BLOB)) + +endif # CONFIG_ARM64_BUILD_ARM_TRUSTED_FIRMWARE + + BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 $(BL31_CBFS)-file := $(BL31) $(BL31_CBFS)-type := payload -- To view, visit https://review.coreboot.org/27559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I17954247029df627a3f4db8b73993bd549e55967 Gerrit-Change-Number: 27559 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init
by Elyes HAOUAS (Code Review) 20 Jul '18

20 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27558 Change subject: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init ...................................................................... cpu/intel/model_f6x: Add model F6x for i945 parallel MP init Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/model_f6x/Makefile.inc M src/cpu/intel/model_f6x/model_f6x_init.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27558/1 diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc index 855fc9e..8f4a282 100644 --- a/src/cpu/intel/model_f6x/Makefile.inc +++ b/src/cpu/intel/model_f6x/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_f6x_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c index 496f563..194a528 100644 --- a/src/cpu/intel/model_f6x/model_f6x_init.c +++ b/src/cpu/intel/model_f6x/model_f6x_init.c @@ -27,7 +27,7 @@ /* Turn on caching if we haven't already */ x86_enable_cache(); - if (!intel_ht_sibling()) { + if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -40,7 +40,8 @@ setup_lapic(); /* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/27558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef Gerrit-Change-Number: 27558 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: riscv: clean up redundancy in Makefile
by Xiang Wang (Code Review) 20 Jul '18

20 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27557 to look at the new patch set (#3). Change subject: riscv: clean up redundancy in Makefile ...................................................................... riscv: clean up redundancy in Makefile src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not need in bootblock. src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some compile/board/time information, which is repeated with src/lib/version.c Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc D src/arch/riscv/id.S D src/arch/riscv/id.ld 3 files changed, 1 insertion(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/3 -- To view, visit https://review.coreboot.org/27557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Gerrit-Change-Number: 27557 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: clean up redundancy in Makefile
by Xiang Wang (Code Review) 20 Jul '18

20 Jul '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27557 ) Change subject: riscv: clean up redundancy in Makefile ...................................................................... riscv: clean up redundancy in Makefile src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not need in bootblock. Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/2 -- To view, visit https://review.coreboot.org/27557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Gerrit-Change-Number: 27557 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: riscv: clean up redundancy in Makefile
by Xiang Wang (Code Review) 20 Jul '18

20 Jul '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27557 Change subject: riscv: clean up redundancy in Makefile ...................................................................... riscv: clean up redundancy in Makefile src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not need in bootblock. Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e00469b..44a5eae 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -42,7 +42,7 @@ bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -bootblock-y = bootblock.S stages.c +bootblock-y = bootblock.S bootblock-y += trap_util.S bootblock-y += trap_handler.c bootblock-y += mcall.c -- To view, visit https://review.coreboot.org/27557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Gerrit-Change-Number: 27557 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: mb/google/octopus: Use unused space in RO_SECTION for COREBOOT region
by Furquan Shaikh (Code Review) 20 Jul '18

20 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27555 Change subject: mb/google/octopus: Use unused space in RO_SECTION for COREBOOT region ...................................................................... mb/google/octopus: Use unused space in RO_SECTION for COREBOOT region This change increases COREBOOT region size by the amount of unused space left in RO_SECTION. This extra space is useful when building images with debug enabled. BUG=b:111661025 Change-Id: Icbd88c3350f96707f37b69fe01f8ae9c7838ab82 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/chromeos.fmd 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/27555/1 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 3c4ed4a..5572930 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -7,9 +7,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x1b3000 - GBB@0x1b4000 0x40000 - RO_UNUSED@0x1f4000 0x8000 + COREBOOT(CBFS)@0x1000 0x1bb000 + GBB@0x1bc000 0x40000 } } MISC_RW@0x400000 0x30000 { -- To view, visit https://review.coreboot.org/27555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icbd88c3350f96707f37b69fe01f8ae9c7838ab82 Gerrit-Change-Number: 27555 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/kahlee: Update i2c timings
by Martin Roth (Code Review) 19 Jul '18

19 Jul '18

Martin Roth has abandoned this change. ( https://review.coreboot.org/25942 ) Change subject: mb/google/kahlee: Update i2c timings ...................................................................... Abandoned replaced by https://review.coreboot.org/#/c/coreboot/+/27553/ -- To view, visit https://review.coreboot.org/25942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ib961ec7c2b0a677d9cacdb7d91e5c78173d42017 Gerrit-Change-Number: 25942 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018