coreboot-gerrit July 2018

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Change in coreboot[master]: mainboard/google/kahlee: Create Liara variant
by Martin Roth (Code Review) 18 Jul '18

18 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27539 Change subject: mainboard/google/kahlee: Create Liara variant ...................................................................... mainboard/google/kahlee: Create Liara variant This is based on the Grunt variant. BUG=b:111607004 TEST=Build Liara Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Kconfig.name A src/mainboard/google/kahlee/variants/liara/Makefile.inc A src/mainboard/google/kahlee/variants/liara/devicetree.cb A src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl A src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl A src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl A src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl A src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl A src/mainboard/google/kahlee/variants/liara/include/variant/ec.h A src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h A src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h 12 files changed, 331 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27539/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index d908c19..11cb891 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -56,6 +56,7 @@ default "aleena" if BOARD_GOOGLE_ALEENA default "careena" if BOARD_GOOGLE_CAREENA default "grunt" if BOARD_GOOGLE_GRUNT + default "liara" if BOARD_GOOGLE_LIARA config MAINBOARD_PART_NUMBER string @@ -107,6 +108,7 @@ default "ALEENA TEST 7281" if BOARD_GOOGLE_ALEENA default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT + default "LIARA TEST 0464" if BOARD_GOOGLE_LIARA config AMD_FWM_POSITION_INDEX int diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index 3f5d1f5..c9401be 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -9,3 +9,6 @@ config BOARD_GOOGLE_GRUNT bool "-> Grunt" select BOARD_GOOGLE_BASEBOARD_KAHLEE +config BOARD_GOOGLE_LIARA + bool "-> Liara" + select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc new file mode 100644 index 0000000..0579e18 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ../baseboard/spd + +romstage-y += ../baseboard/romstage.c + +ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb new file mode 100644 index 0000000..3863100 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -0,0 +1,164 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "32 * MiB" + + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 84, + .fall_time_ns = 4, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 117, + .fall_time_ns = 113, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 82, + .fall_time_ns = 67, + }" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain + device mmio 0xfedc2000 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device mmio 0xfedc3000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + device i2c 15 on end + end + end + device mmio 0xfedc5000 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl new file mode 100644 index 0000000..05cd0b9 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/gpe.asl> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..d026e9a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/mainboard.asl> +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl new file mode 100644 index 0000000..c1896c3 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/routing.asl> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl new file mode 100644 index 0000000..a401b3a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..a7e511c --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h b/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h new file mode 100644 index 0000000..e90724e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/ec.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/ec.h> + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h new file mode 100644 index 0000000..5a6b540 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h new file mode 100644 index 0000000..1bb78ef --- /dev/null +++ b/src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Stoney Ridge Thermal Requirements 12 (6W) + * TDP (W) 6 + * T die,max (°C) 95 + * T ctl,max 85 + * T die,lmt (default) 90 + * T ctl,lmt (default) 80 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 94 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 85 + +#endif -- To view, visit https://review.coreboot.org/27539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Gerrit-Change-Number: 27539 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mainboard/google/kahlee: Create Aleena variant
by Martin Roth (Code Review) 18 Jul '18

18 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27538 Change subject: mainboard/google/kahlee: Create Aleena variant ...................................................................... mainboard/google/kahlee: Create Aleena variant This is based on the Grunt variant. BUG=b:111606874 TEST=Build Aleena Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Kconfig.name A src/mainboard/google/kahlee/variants/aleena/Makefile.inc A src/mainboard/google/kahlee/variants/aleena/devicetree.cb A src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl A src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl A src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl A src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl A src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl A src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h A src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h A src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h 12 files changed, 331 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/27538/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index d16838f..d908c19 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -53,6 +53,7 @@ config VARIANT_DIR string + default "aleena" if BOARD_GOOGLE_ALEENA default "careena" if BOARD_GOOGLE_CAREENA default "grunt" if BOARD_GOOGLE_GRUNT @@ -103,6 +104,7 @@ config GBB_HWID string depends on CHROMEOS + default "ALEENA TEST 7281" if BOARD_GOOGLE_ALEENA default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index 4f58a01..3f5d1f5 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -1,5 +1,8 @@ comment "Kahlee" +config BOARD_GOOGLE_ALEENA + bool "-> Aleena" + select BOARD_GOOGLE_BASEBOARD_KAHLEE config BOARD_GOOGLE_CAREENA bool "-> Careena" select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc new file mode 100644 index 0000000..0579e18 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ../baseboard/spd + +romstage-y += ../baseboard/romstage.c + +ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb new file mode 100644 index 0000000..3863100 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -0,0 +1,164 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "32 * MiB" + + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 84, + .fall_time_ns = 4, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 117, + .fall_time_ns = 113, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 82, + .fall_time_ns = 67, + }" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain + device mmio 0xfedc2000 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device mmio 0xfedc3000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + device i2c 15 on end + end + end + device mmio 0xfedc5000 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl new file mode 100644 index 0000000..05cd0b9 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/gpe.asl> diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..d026e9a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/mainboard.asl> +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl new file mode 100644 index 0000000..c1896c3 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/routing.asl> diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl new file mode 100644 index 0000000..a401b3a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..a7e511c --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h new file mode 100644 index 0000000..e90724e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/ec.h> + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h new file mode 100644 index 0000000..5a6b540 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h new file mode 100644 index 0000000..1bb78ef --- /dev/null +++ b/src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Stoney Ridge Thermal Requirements 12 (6W) + * TDP (W) 6 + * T die,max (°C) 95 + * T ctl,max 85 + * T die,lmt (default) 90 + * T ctl,lmt (default) 80 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 94 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 85 + +#endif -- To view, visit https://review.coreboot.org/27538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Gerrit-Change-Number: 27538 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: google/asuka: Add as a variant of glados
by build bot (Jenkins) (Code Review) 18 Jul '18

18 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27421 ) Change subject: google/asuka: Add as a variant of glados ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27421/3/src/mainboard/google/glados/variant… File src/mainboard/google/glados/variants/asuka/include/variant/gpio.h: https://review.coreboot.org/#/c/27421/3/src/mainboard/google/glados/variant… PS3, Line 93: /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ line over 80 characters -- To view, visit https://review.coreboot.org/27421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I591578fea2514a28c75177835807c3f250904577 Gerrit-Change-Number: 27421 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Jul 2018 20:27:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: google/caroline: Add as a variant of glados
by build bot (Jenkins) (Code Review) 18 Jul '18

18 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27419 ) Change subject: google/caroline: Add as a variant of glados ...................................................................... Patch Set 4: (15 comments) https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… File src/mainboard/google/glados/variants/caroline/include/variant/gpio.h: https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 79: /* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 101: /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 111: /* GSPI0_CS# */ PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 112: /* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 115: /* GSPI1_CS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 126: /* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 132: /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 133: /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 134: /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 135: /* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 143: /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 175: /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 183: /* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 184: /* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ line over 80 characters https://review.coreboot.org/#/c/27419/4/src/mainboard/google/glados/variant… PS4, Line 249: /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ line over 80 characters -- To view, visit https://review.coreboot.org/27419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I611a4e76581ba2e5b42e1bc48b0a5b8c70f3598e Gerrit-Change-Number: 27419 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Jul 2018 20:27:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: google/cave: Add as a variant of glados
by build bot (Jenkins) (Code Review) 18 Jul '18

18 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27420 ) Change subject: google/cave: Add as a variant of glados ...................................................................... Patch Set 3: (13 comments) https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… File src/mainboard/google/glados/variants/cave/include/variant/gpio.h: https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 97: /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 108: /* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 122: /* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 128: /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 129: /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 130: /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 131: /* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 139: /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 167: /* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 171: /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 179: /* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 180: /* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ line over 80 characters https://review.coreboot.org/#/c/27420/3/src/mainboard/google/glados/variant… PS3, Line 241: /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ line over 80 characters -- To view, visit https://review.coreboot.org/27420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a Gerrit-Change-Number: 27420 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Jul 2018 20:27:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: set nvme to use clk src 3
by Furquan Shaikh (Code Review) 18 Jul '18

18 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27536 ) Change subject: mb/google/poppy/variants/nocturne: set nvme to use clk src 3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Gerrit-Change-Number: 27536 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 18 Jul 2018 18:28:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: set nvme to use clk src 3
by Lijian Zhao (Code Review) 18 Jul '18

18 Jul '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/27536 ) Change subject: mb/google/poppy/variants/nocturne: set nvme to use clk src 3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Gerrit-Change-Number: 27536 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Wed, 18 Jul 2018 18:25:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: set nvme to use clk src 3
by Nick Vaccaro (Code Review) 18 Jul '18

18 Jul '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/27536 Change subject: mb/google/poppy/variants/nocturne: set nvme to use clk src 3 ...................................................................... mb/google/poppy/variants/nocturne: set nvme to use clk src 3 Latest nocturne architecture uses clk src 3 for nvme. BUG=b:111514174 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme nocturne devices are able to recognize the nvme controller. Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/27536/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5e1b7aa..1d00bc2 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -164,13 +164,13 @@ # PcieRpEnable: Enable root port # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 2 + # PcieRpClkSrcNumber: Uses 3 # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1" -- To view, visit https://review.coreboot.org/27536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Gerrit-Change-Number: 27536 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: arch/riscv: Fix makefile to only set flags for riscv
by Martin Roth (Code Review) 18 Jul '18

18 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27535 Change subject: arch/riscv: Fix makefile to only set flags for riscv ...................................................................... arch/riscv: Fix makefile to only set flags for riscv This was updating flags for ALL architectures, not just riscv. That was bad. Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27 Signed-off-by: Martin Roth <martin(a)coreboot.org> --- M src/arch/riscv/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27535/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 90e4240..a797076 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -21,7 +21,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) check-ramstage-overlap-regions += stack -endif riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) @@ -32,6 +31,7 @@ COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name) COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name) +endif ################################################################################ ## bootblock -- To view, visit https://review.coreboot.org/27535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27 Gerrit-Change-Number: 27535 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: util/gitconfig: Make checkpatch non fatal in pre-commit hook
by Martin Roth (Code Review) 18 Jul '18

18 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27534 Change subject: util/gitconfig: Make checkpatch non fatal in pre-commit hook ...................................................................... util/gitconfig: Make checkpatch non fatal in pre-commit hook We don't block commits for failing checkpatch in gerrit, and we shouldn't block them here. This allows checkpatch to still run, so users can see the issues, but won't prevent the commit. Adds a delay if checkpatch fails so that the issues can be seen. Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50 Signed-off-by: Martin Roth <martin(a)coreboot.org> --- M util/gitconfig/pre-commit 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/27534/1 diff --git a/util/gitconfig/pre-commit b/util/gitconfig/pre-commit index 027eec0..0644b7f 100755 --- a/util/gitconfig/pre-commit +++ b/util/gitconfig/pre-commit @@ -24,5 +24,6 @@ if printf "%s\n" "$PATCHDIFF" | grep -q "@@"; then echo echo "Running checkpatch" - printf "%s\n" "$PATCHDIFF" | util/lint/lint-007-checkpatch diff + printf "%s\n" "$PATCHDIFF" | util/lint/lint-007-checkpatch diff \ + || (echo "Please consider fixing these issues." ;sleep 5) ; true fi -- To view, visit https://review.coreboot.org/27534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50 Gerrit-Change-Number: 27534 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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