coreboot-gerrit July 2018

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Change in coreboot[master]: Coverity: Fix CID1393978
by Philipp Deppenwiese (Code Review) 12 Jul '18

12 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27446 ) Change subject: Coverity: Fix CID1393978 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83 Gerrit-Change-Number: 27446 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 15:21:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Coverity: Fix CID1393979
by Philipp Deppenwiese (Code Review) 12 Jul '18

12 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27445 ) Change subject: Coverity: Fix CID1393979 ...................................................................... Coverity: Fix CID1393979 Fix resource leak in dt_set_bin_prop_by_path(). Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/27445 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/lib/device_tree.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 3d44f39..00b36fd 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -944,6 +944,7 @@ prop_name = strrchr(path_copy, '/'); if (!prop_name) { + free(path_copy); printk(BIOS_ERR, "Path %s does not include '/'\n", path); return 1; } @@ -956,10 +957,12 @@ if (!dt_node) { printk(BIOS_ERR, "Failed to %s %s in the device tree\n", create ? "create" : "find", path_copy); + free(path_copy); return 1; } dt_add_bin_prop(dt_node, prop_name, data, data_size); + free(path_copy); return 0; } -- To view, visit https://review.coreboot.org/27445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Gerrit-Change-Number: 27445 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Coverity: Fix CID1393979
by Philipp Deppenwiese (Code Review) 12 Jul '18

12 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27445 ) Change subject: Coverity: Fix CID1393979 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Gerrit-Change-Number: 27445 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 15:21:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium: Enable DRAM test
by build bot (Jenkins) (Code Review) 12 Jul '18

12 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27103 ) Change subject: soc/cavium: Enable DRAM test ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/27103/5/src/soc/cavium/cn81xx/sdram.c File src/soc/cavium/cn81xx/sdram.c: https://review.coreboot.org/#/c/27103/5/src/soc/cavium/cn81xx/sdram.c@93 PS5, Line 93: if (0 != bdk_numa_master()) Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27103/5/src/soc/cavium/cn81xx/sdram.c@97 PS5, Line 97: if (0 == bdk_numa_master()) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Gerrit-Change-Number: 27103 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 14:03:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by build bot (Jenkins) (Code Review) 12 Jul '18

12 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25382 ) Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... Patch Set 38: (4 comments) https://review.coreboot.org/#/c/25382/38/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25382/38/src/soc/cavium/cn81xx/soc.c@82 PS38, Line 82: Remove 'phy-handle' if this option is not availble */ 'availble' may be misspelled - perhaps 'available'? https://review.coreboot.org/#/c/25382/38/src/soc/cavium/cn81xx/soc.c@140 PS38, Line 140: /* Extract our MAC address info so we can assign them in the device tree */ line over 80 characters https://review.coreboot.org/#/c/25382/38/src/soc/cavium/cn81xx/soc.c@172 PS38, Line 172: if (!strcmp(name, prop->prop.name)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25382/38/src/soc/cavium/cn81xx/soc.c@268 PS38, Line 268: BDK_BGXX_CMRX_RX_DMAC_CTL(bgx_interface, bgx_index)); line over 80 characters -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 38 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 14:02:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [HACK]cavium/arm-trusted-firmware: Use 9elements ATF
by build bot (Jenkins) (Code Review) 12 Jul '18

12 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25751 ) Change subject: [HACK]cavium/arm-trusted-firmware: Use 9elements ATF ...................................................................... Patch Set 27: (2 comments) https://review.coreboot.org/#/c/25751/27/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25751/27/src/soc/cavium/cn81xx/soc.c@73 PS27, Line 73: void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb", CBFS_TYPE_RAW, &size); line over 80 characters https://review.coreboot.org/#/c/25751/27/src/soc/cavium/common/include/soc/… File src/soc/cavium/common/include/soc/bl31_plat_params.h: https://review.coreboot.org/#/c/25751/27/src/soc/cavium/common/include/soc/… PS27, Line 21: #include <soc/cavium/common/arm-trusted-firmware/plat/cavium/common/include/plat_params.h> line over 80 characters -- To view, visit https://review.coreboot.org/25751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Gerrit-Change-Number: 25751 Gerrit-PatchSet: 27 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 14:02:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cavium/bdk: Poke the watchdog while PCIe init
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27455 Change subject: cavium/bdk: Poke the watchdog while PCIe init ...................................................................... cavium/bdk: Poke the watchdog while PCIe init Prevent a reboot loop due to slow PCIe init. Poke the watchdog a few times. Change-Id: I03739d7dbad3072ccf77364fa4caba42c66ac643 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-pcie.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-pcie-cn8xxx.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/27455/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-pcie.c b/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-pcie.c index b03c2e0..d52d6e9 100644 --- a/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-pcie.c +++ b/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-pcie.c @@ -61,6 +61,7 @@ { BDK_TRACE(INIT, "Initializing PCIe%d on Node %d\n", p, n); bdk_pcie_rc_initialize(n, p); + bdk_watchdog_poke(); } } } diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-pcie-cn8xxx.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-pcie-cn8xxx.c index 16034d2..6675fd5 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-pcie-cn8xxx.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-pcie-cn8xxx.c @@ -549,6 +549,7 @@ return val; /* Failed, wait a little and try again */ bdk_wait_usec(10000); + bdk_watchdog_poke(); } while (bdk_clock_get_count(BDK_CLOCK_TIME) < timeout); BDK_TRACE(PCIE, "N%d.PCIe%d: Config read failed, can't communicate with device\n", @@ -1123,6 +1124,7 @@ return -1; } retry_count++; + bdk_watchdog_poke(); } /* Errata PCIE-28816: Link retrain initiated at GEN1 can cause PCIE -- To view, visit https://review.coreboot.org/27455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I03739d7dbad3072ccf77364fa4caba42c66ac643 Gerrit-Change-Number: 27455 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: cavium/bdk: Fix reference clock
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27454 Change subject: cavium/bdk: Fix reference clock ...................................................................... cavium/bdk: Fix reference clock Swap 100Mhz and 156Mhz reference clock. Correct values are taken from __bdk_qlm_sff81xx_set_reference(). Tested on Cavium's cn8100_sff_evb. Change-Id: I312ce7379b361594249f9f26f4e561ebf57347df Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-common.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27454/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-common.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-common.c index 2b33902..de9dcde 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-common.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-common.c @@ -832,11 +832,11 @@ { switch (ref_clk) { - case REF_100MHZ: + case REF_156MHZ: use_clock = 0; /* Common clock 0 */ BDK_TRACE(QLM, "Setting N%d.QLM%d to use common clock 0\n", node, qlm); break; - case REF_156MHZ: + case REF_100MHZ: use_clock = 1; /* Common clock 1 */ BDK_TRACE(QLM, "Setting N%d.QLM%d to use common clock 1\n", node, qlm); break; -- To view, visit https://review.coreboot.org/27454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I312ce7379b361594249f9f26f4e561ebf57347df Gerrit-Change-Number: 27454 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: Coverity: Fix CID1393970
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27453 Change subject: Coverity: Fix CID1393970 ...................................................................... Coverity: Fix CID1393970 Fix possible DIVIDE_BY_ZERO. Change-Id: I5db6866b8e51eaea201a4c03e59d7d00f4f826e7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-usb.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/27453/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-usb.c b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-usb.c index eb2a85f..83ce563 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/bdk-usb.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/bdk-usb.c @@ -369,7 +369,9 @@ uint64_t fr_div; if (divider < 5) fr_div = divider * 2; else fr_div = 8 * (divider - 3); - uint64_t freq = (typeof(freq)) (sclk_rate / fr_div); + uint64_t freq = 0; + if (fr_div > 0) + freq = (typeof(freq)) (sclk_rate / fr_div); const char *token; if (freq < 62500000ULL) token = "???Low"; else if (freq < 90000000ULL) token = "USB2"; -- To view, visit https://review.coreboot.org/27453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5db6866b8e51eaea201a4c03e59d7d00f4f826e7 Gerrit-Change-Number: 27453 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: cavium/bdk: Fix coverity and remove hardcoded DRAM speed
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27452 Change subject: cavium/bdk: Fix coverity and remove hardcoded DRAM speed ...................................................................... cavium/bdk: Fix coverity and remove hardcoded DRAM speed * Fix CID1393963 (Uninitialized variables) * Comment in working code * Remove workaround to limit DDR speed Change-Id: I96289da43c1018c2fdf9d013ce7f21d7511ba595 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c M src/vendorcode/cavium/bdk/libdram/dram-spd.c 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/27452/1 diff --git a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c index 7bc04ce..8775886 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c +++ b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c @@ -90,7 +90,6 @@ {"MULTI-NODE", "0"}, {"QLM-AUTO-CONFIG", "0"}, {"QLM-DIP-AUTO-CONFIG", "1"}, -{"DDR-SPEED.N0", "1333"}, {"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"}, {"USB-PWR-GPIO.N0.PORT0", "12"}, {"USB-PWR-GPIO-POLARITY.N0.PORT0", "0"}, diff --git a/src/vendorcode/cavium/bdk/libdram/dram-spd.c b/src/vendorcode/cavium/bdk/libdram/dram-spd.c index 6498b85..329ae98 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-spd.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-spd.c @@ -549,15 +549,17 @@ int dimm_speed[8], dimm_count = 0; int dimms_per_lmc = 0; + memset (dimm_speed, 0, sizeof(dimm_speed)); + for (lmc = 0; lmc < 4; lmc++) { for (dimm = 0; dimm < DDR_CFG_T_MAX_DIMMS; dimm++) { const dimm_config_t *dimm_config = &ddr_config[lmc].dimm_config_table[dimm]; - if (/*dimm_config->spd_addr ||*/ dimm_config->spd_ptr) + if (dimm_config->spd_addr || dimm_config->spd_ptr) { speed = (ddr_type == DDR4_DRAM) ? get_ddr4_spd_speed(node, dimm_config) : get_ddr3_spd_speed(node, dimm_config); - //printf("N%d.LMC%d.DIMM%d: SPD speed %d\n", node, lmc, dimm, speed); + printf("N%d.LMC%d.DIMM%d: SPD speed %d\n", node, lmc, dimm, speed); dimm_speed[dimm_count] = speed; dimm_count++; if (lmc == 0) @@ -596,6 +598,6 @@ ret_speed = mts_to_hertz(speed); finish_up: - //printf("N%d: Returning default SPD speed %d\n", node, ret_speed); + printf("N%d: Returning default SPD speed %d\n", node, ret_speed); return ret_speed; } -- To view, visit https://review.coreboot.org/27452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I96289da43c1018c2fdf9d013ce7f21d7511ba595 Gerrit-Change-Number: 27452 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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coreboot-gerrit July 2018