coreboot-gerrit July 2018

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Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Ricky Liang (Code Review) 12 Jul '18

12 Jul '18

Ricky Liang has posted comments on this change. ( https://review.coreboot.org/27433 ) Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... Patch Set 2: Silly question: How do I merge the CL? Will it happen automatically? -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 2 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 06:39:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Nick Vaccaro (Code Review) 12 Jul '18

12 Jul '18

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Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Tomasz Figa (Code Review) 12 Jul '18

12 Jul '18

Tomasz Figa has posted comments on this change. ( https://review.coreboot.org/27433 ) Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/27433/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/27433/2/src/mainboard/google/poppy/variants… PS2, Line 181: PAD_CFG_NC(GPP_D8), > There's a a fix going into EVT2 firmware that is needed for EVT2 to fix a hang bug, but that same fi […] Okay, let's go with 1) then, which is this CL. -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 2 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 04:31:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by build bot (Jenkins) (Code Review) 12 Jul '18

12 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27358 ) Change subject: riscv: temporarily block multiple-threads ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/27358/8/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/27358/8/src/arch/riscv/smp.c@39 PS8, Line 39: trailing whitespace -- To view, visit https://review.coreboot.org/27358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0eeed51e0952c66a9a9f25a90105fe471ffa70e Gerrit-Change-Number: 27358 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 12 Jul 2018 04:25:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Nick Vaccaro (Code Review) 12 Jul '18

12 Jul '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/27433 ) Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27433/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/27433/2/src/mainboard/google/poppy/variants… PS2, Line 181: PAD_CFG_NC(GPP_D8), > However, just keeping GPP_D8 configured here, without the relevant ACPI code configuring the pin cor […] There's a a fix going into EVT2 firmware that is needed for EVT2 to fix a hang bug, but that same fix will cause preEVT2 units to potentially exhibit the hang bug, which means we will need to obsolete the preEVT2 units once EVT2 units arrive. Given the short-lived nature of preEVT2, I'm ok with this change. -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 2 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 03:52:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Tomasz Figa (Code Review) 12 Jul '18

12 Jul '18

Tomasz Figa has posted comments on this change. ( https://review.coreboot.org/27433 ) Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27433/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/27433/2/src/mainboard/google/poppy/variants… PS2, Line 181: PAD_CFG_NC(GPP_D8), > I left GPP_D8 configured in gpio. […] However, just keeping GPP_D8 configured here, without the relevant ACPI code configuring the pin correctly for kernel PM requests, doesn't actually allow camera development. Given that, we can either 1) just clean it up now or 2) try to make the ACPI code handle both variants. 2) could actually make some sense, if it doesn't introduce any side effects, since it may take quite a while until all the camera people get the new revision. -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 2 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Jul 2018 03:47:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: exception handle support SMP
by Xiang Wang (Code Review) 12 Jul '18

12 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27441 to look at the new patch set (#2). Change subject: riscv: exception handle support SMP ...................................................................... riscv: exception handle support SMP fix exception handle not support SMP for RISC-V. Change-Id: I053138c6d778413d125e91689da330b1ac857027 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/trap_util.S 1 file changed, 97 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27441/2 -- To view, visit https://review.coreboot.org/27441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I053138c6d778413d125e91689da330b1ac857027 Gerrit-Change-Number: 27441 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: exception handle support SMP
by Xiang Wang (Code Review) 12 Jul '18

12 Jul '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27441 Change subject: riscv: exception handle support SMP ...................................................................... riscv: exception handle support SMP fix exception handle not support SMP for RISC-V. Change-Id: I053138c6d778413d125e91689da330b1ac857027 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/trap_util.S 1 file changed, 98 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27441/1 diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..5e4b0e5 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -18,124 +18,114 @@ #include <mcall.h> .macro restore_regs - # restore x registers - LOAD x1,1*REGBYTES(a0) - LOAD x2,2*REGBYTES(a0) - LOAD x3,3*REGBYTES(a0) - LOAD x4,4*REGBYTES(a0) - LOAD x5,5*REGBYTES(a0) - LOAD x6,6*REGBYTES(a0) - LOAD x7,7*REGBYTES(a0) - LOAD x8,8*REGBYTES(a0) - LOAD x9,9*REGBYTES(a0) - LOAD x11,11*REGBYTES(a0) - LOAD x12,12*REGBYTES(a0) - LOAD x13,13*REGBYTES(a0) - LOAD x14,14*REGBYTES(a0) - LOAD x15,15*REGBYTES(a0) - LOAD x16,16*REGBYTES(a0) - LOAD x17,17*REGBYTES(a0) - LOAD x18,18*REGBYTES(a0) - LOAD x19,19*REGBYTES(a0) - LOAD x20,20*REGBYTES(a0) - LOAD x21,21*REGBYTES(a0) - LOAD x22,22*REGBYTES(a0) - LOAD x23,23*REGBYTES(a0) - LOAD x24,24*REGBYTES(a0) - LOAD x25,25*REGBYTES(a0) - LOAD x26,26*REGBYTES(a0) - LOAD x27,27*REGBYTES(a0) - LOAD x28,28*REGBYTES(a0) - LOAD x29,29*REGBYTES(a0) - LOAD x30,30*REGBYTES(a0) - LOAD x31,31*REGBYTES(a0) - # restore a0 last - LOAD x10,10*REGBYTES(a0) + # restore x registers + LOAD x1,1*REGBYTES(sp) + LOAD x3,3*REGBYTES(sp) + LOAD x4,4*REGBYTES(sp) + LOAD x5,5*REGBYTES(sp) + LOAD x6,6*REGBYTES(sp) + LOAD x7,7*REGBYTES(sp) + LOAD x8,8*REGBYTES(sp) + LOAD x9,9*REGBYTES(sp) + LOAD x10,10*REGBYTES(sp) + LOAD x11,11*REGBYTES(sp) + LOAD x12,12*REGBYTES(sp) + LOAD x13,13*REGBYTES(sp) + LOAD x14,14*REGBYTES(sp) + LOAD x15,15*REGBYTES(sp) + LOAD x16,16*REGBYTES(sp) + LOAD x17,17*REGBYTES(sp) + LOAD x18,18*REGBYTES(sp) + LOAD x19,19*REGBYTES(sp) + LOAD x20,20*REGBYTES(sp) + LOAD x21,21*REGBYTES(sp) + LOAD x22,22*REGBYTES(sp) + LOAD x23,23*REGBYTES(sp) + LOAD x24,24*REGBYTES(sp) + LOAD x25,25*REGBYTES(sp) + LOAD x26,26*REGBYTES(sp) + LOAD x27,27*REGBYTES(sp) + LOAD x28,28*REGBYTES(sp) + LOAD x29,29*REGBYTES(sp) + LOAD x30,30*REGBYTES(sp) + LOAD x31,31*REGBYTES(sp) + .endm - - .endm .macro save_tf - # save gprs - STORE x1,1*REGBYTES(x2) - STORE x3,3*REGBYTES(x2) - STORE x4,4*REGBYTES(x2) - STORE x5,5*REGBYTES(x2) - STORE x6,6*REGBYTES(x2) - STORE x7,7*REGBYTES(x2) - STORE x8,8*REGBYTES(x2) - STORE x9,9*REGBYTES(x2) - STORE x10,10*REGBYTES(x2) - STORE x11,11*REGBYTES(x2) - STORE x12,12*REGBYTES(x2) - STORE x13,13*REGBYTES(x2) - STORE x14,14*REGBYTES(x2) - STORE x15,15*REGBYTES(x2) - STORE x16,16*REGBYTES(x2) - STORE x17,17*REGBYTES(x2) - STORE x18,18*REGBYTES(x2) - STORE x19,19*REGBYTES(x2) - STORE x20,20*REGBYTES(x2) - STORE x21,21*REGBYTES(x2) - STORE x22,22*REGBYTES(x2) - STORE x23,23*REGBYTES(x2) - STORE x24,24*REGBYTES(x2) - STORE x25,25*REGBYTES(x2) - STORE x26,26*REGBYTES(x2) - STORE x27,27*REGBYTES(x2) - STORE x28,28*REGBYTES(x2) - STORE x29,29*REGBYTES(x2) - STORE x30,30*REGBYTES(x2) - STORE x31,31*REGBYTES(x2) + # save gprs + STORE x1,1*REGBYTES(sp) + STORE x3,3*REGBYTES(sp) + STORE x4,4*REGBYTES(sp) + STORE x5,5*REGBYTES(sp) + STORE x6,6*REGBYTES(sp) + STORE x7,7*REGBYTES(sp) + STORE x8,8*REGBYTES(sp) + STORE x9,9*REGBYTES(sp) + STORE x10,10*REGBYTES(sp) + STORE x11,11*REGBYTES(sp) + STORE x12,12*REGBYTES(sp) + STORE x13,13*REGBYTES(sp) + STORE x14,14*REGBYTES(sp) + STORE x15,15*REGBYTES(sp) + STORE x16,16*REGBYTES(sp) + STORE x17,17*REGBYTES(sp) + STORE x18,18*REGBYTES(sp) + STORE x19,19*REGBYTES(sp) + STORE x20,20*REGBYTES(sp) + STORE x21,21*REGBYTES(sp) + STORE x22,22*REGBYTES(sp) + STORE x23,23*REGBYTES(sp) + STORE x24,24*REGBYTES(sp) + STORE x25,25*REGBYTES(sp) + STORE x26,26*REGBYTES(sp) + STORE x27,27*REGBYTES(sp) + STORE x28,28*REGBYTES(sp) + STORE x29,29*REGBYTES(sp) + STORE x30,30*REGBYTES(sp) + STORE x31,31*REGBYTES(sp) - # get sr, epc, badvaddr, cause - csrrw t0,mscratch,x0 - csrr s0,mstatus - csrr t1,mepc - csrr t2,mbadaddr - csrr t3,mcause - STORE t0,2*REGBYTES(x2) - STORE s0,32*REGBYTES(x2) - STORE t1,33*REGBYTES(x2) - STORE t2,34*REGBYTES(x2) - STORE t3,35*REGBYTES(x2) + # get sr, epc, badvaddr, cause + csrrw t0,mscratch,x0 + csrr s0,mstatus + csrr t1,mepc + csrr t2,mbadaddr + csrr t3,mcause + STORE t0,2*REGBYTES(sp) + STORE s0,32*REGBYTES(sp) + STORE t1,33*REGBYTES(sp) + STORE t2,34*REGBYTES(sp) + STORE t3,35*REGBYTES(sp) - # get faulting insn, if it wasn't a fetch-related trap - li x5,-1 - STORE x5,36*REGBYTES(x2) + # get faulting insn, if it wasn't a fetch-related trap + li x5,-1 + STORE x5,36*REGBYTES(sp) + .endm - .endm + .globl estack + .text -.globl estack - .text - - .global trap_entry - .align 2 # four byte alignment, as required by mtvec + .global trap_entry + .align 2 # four byte alignment, as required by mtvec trap_entry: - csrw mscratch, sp + # switch stack pointer between m-mode and other mode + csrrw sp, mscratch, sp + bnez sp, 1f + # trap come from m-mode (mscratch initialize to zero) + csrr sp, mscratch +1: + addi sp, sp, -MENTRY_FRAME_SIZE - # SMP isn't supported yet, to avoid overwriting the same stack with different - # harts that handle traps at the same time. - # someday this gets fixed. - //csrr sp, mhartid - csrr sp, 0xf14 -.Lsmp_hang: - bnez sp, .Lsmp_hang - - # Use a different stack than in the main context, to to avoid overwriting - # stack data. - # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if - # the previous mode was M, because it would be a very bad idea to use a stack - # pointer provided by unprivileged code! - la sp, _estack - addi sp, sp, -2048 # 2 KiB is half of the stack space - addi sp, sp, -MENTRY_FRAME_SIZE - - save_tf - move a0,sp - jal trap_handler + save_tf + move a0, sp + call trap_handler trap_return: - csrr a0, mscratch restore_regs + addi sp, sp, MENTRY_FRAME_SIZE + csrrw sp, mscratch, sp + bnez sp, 1f + csrrw sp, mscratch, x0 +1: # go back to the previous mode mret + -- To view, visit https://review.coreboot.org/27441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I053138c6d778413d125e91689da330b1ac857027 Gerrit-Change-Number: 27441 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: uart/sifive: make divisor configurable
by Philipp Hug (Code Review) 11 Jul '18

11 Jul '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/27440 Change subject: uart/sifive: make divisor configurable ...................................................................... uart/sifive: make divisor configurable The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 --- M src/drivers/uart/sifive.c M src/soc/sifive/fu540/Kconfig M src/soc/sifive/fu540/uart.c 3 files changed, 20 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27440/1 diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index dd47caf..ce8ead0 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -46,11 +46,10 @@ #define IP_TXWM BIT(0) #define IP_RXWM BIT(1) -void uart_init(int idx) +static void sifive_uart_init(struct sifive_uart_registers *regs, int div) { - struct sifive_uart_registers *regs = uart_platform_baseptr(idx); - - /* TODO: Configure the divisor */ + /* Configure the divisor */ + write32(&regs->div, div); /* Enable transmission, one stop bit, transmit watermark at 1 */ write32(&regs->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1)); @@ -59,6 +58,14 @@ write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0)); } +void uart_init(int idx) +{ + unsigned int div; + div = uart_baudrate_divisor(get_uart_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); + sifive_uart_init(uart_platform_baseptr(idx), div); +} + static bool uart_can_tx(struct sifive_uart_registers *regs) { return !(read32(&regs->txdata) & TXDATA_FULL); diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index d247c28..df9a278 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -20,7 +20,7 @@ select ARCH_RAMSTAGE_RISCV select BOOTBLOCK_CONSOLE select DRIVERS_UART_SIFIVE - + select UART_OVERRIDE_REFCLK if SOC_SIFIVE_FU540 endif diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index 940dc97..b9dc7df 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -23,3 +23,11 @@ else return 0; } + +unsigned int uart_platform_refclk(void) +{ + /* + * The SiFive UART uses tlclk, which is coreclk/2 as input + */ + return 33330000 / 2; +} -- To view, visit https://review.coreboot.org/27440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Gerrit-Change-Number: 27440 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: sifive/fu540: PLL + clock initialization
by Philipp Hug (Code Review) 11 Jul '18

11 Jul '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/27439 Change subject: sifive/fu540: PLL + clock initialization ...................................................................... sifive/fu540: PLL + clock initialization Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52 --- A src/soc/sifive/fu540/clock.c A src/soc/sifive/fu540/include/soc/clock.h 2 files changed, 198 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27439/1 diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c new file mode 100644 index 0000000..1fa850c --- /dev/null +++ b/src/soc/sifive/fu540/clock.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Philipp Hug <philipp(a)hug.cx> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/clock.h> +#include <soc/addressmap.h> +#include <stdlib.h> +#include <stdint.h> + +struct prci_ctlr { + u32 hfxosccfg; /* offset 0x00 */ + u32 corepllcfg0; /* offset 0x04 */ + u32 reserved08; /* offset 0x08 */ + u32 ddrpllcfg0; /* offset 0x0c */ + u32 ddrpllcfg1; /* offset 0x10 */ + u32 reserved14; /* offset 0x14 */ + u32 reserved18; /* offset 0x18 */ + u32 gemgxlpllcfg0; /* offset 0x1c */ + u32 gemgxlpllcfg1; /* offset 0x20 */ + u32 coreclksel; /* offset 0x24 */ + u32 devicesresetreg; /* offset 0x28 */ +}; + +static struct prci_ctlr *prci = (void *)FU540_PRCI; + +#define PRCI_CORECLK_MASK 1 +#define PRCI_CORECLK_CORE_PLL 0 +#define PRCI_CORECLK_HFCLK 1 + +#define PRCI_COREPLLCFG0_LOCK (1u << 31) +#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 +#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 +#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 +#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 +#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT) +#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) +#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT) +#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT) +#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) + +#define PRCI_DDRPLLCFG0_LOCK (1u << 31) +#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 +#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 +#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 +#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 +#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT) +#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) +#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) +#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT) +#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) +#define PRCI_DDRPLLCFG1_MASK (1u << 31) + +#define PRCI_CORECLK_DIVR 0 +#define PRCI_CORECLK_DIVF 59 +#define PRCI_CORECLK_DIVQ 2 +#define PRCI_CORECLK_RANGE 4 + +#define PRCI_DDRCLK_DIVR 0 +#define PRCI_DDRCLK_DIVF 59 +#define PRCI_DDRCLK_DIVQ 5 +#define PRCI_DDRCLK_RANGE 4 + +#define PRCI_RESET_DDR_CTRL_RST_N (1 << 0) +#define PRCI_RESET_DDR_AXI_RST_N (1 << 1) +#define PRCI_RESET_DDR_AHB_RST_N (1 << 2) +#define PRCI_RESET_DDR_PHY_RST_N (1 << 3) +#define PRCI_RESET_GEMGXL_RST_N (1 << 5) + +// 33.33 Mhz after reset +#define FU540_BASE_FQY 33330 + +static void init_pll_core(void) +{ + clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_HFCLK); + + u32 c = read32(&prci->corepllcfg0); + clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK + | PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK + | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK, + (PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT) + & (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT) + & (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT) + & (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT)); + write32(&prci->corepllcfg0, c); + + // wait for PLL lock + while (!(read32(&prci->corepllcfg0) & PRCI_COREPLLCFG0_LOCK)) + ; /* TODO: implement a timeout */ + + clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_CORE_PLL); +} + +static void init_pll_ddr(void) +{ + u32 cfg1 = read32(&prci->ddrpllcfg1); + clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); + write32(&prci->ddrpllcfg1, cfg1); + + u32 c = read32(&prci->ddrpllcfg0); + clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK + | PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK + | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK, + (PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT) + & (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT) + & (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT) + & (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT)); + write32(&prci->ddrpllcfg0, c); + + // wait for PLL lock + while (!(read32(&prci->ddrpllcfg0) & PRCI_DDRPLLCFG0_LOCK)) + ; /* TODO: implement a timeout */ + + setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); + write32(&prci->ddrpllcfg1, cfg1); +} + +int clock_get_coreclk_khz(void) +{ + if (read32(&prci->coreclksel) & PRCI_CORECLK_MASK) { + return FU540_BASE_FQY; + } else { + u32 cfg = read32(&prci->corepllcfg0); + u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK) + >> PRCI_COREPLLCFG0_DIVR_SHIFT; + u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK) + >> PRCI_COREPLLCFG0_DIVF_SHIFT; + u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK) + >> PRCI_COREPLLCFG0_DIVQ_SHIFT; + + printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq); + return FU540_BASE_FQY + * 2 * (divf + 1) + / (divr + 1) + / (1 << divq); + } +} + +static void my_sdram_init(void) +{ + setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_CTRL_RST_N); + mb(); + setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_AXI_RST_N); + setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_AHB_RST_N); + setbits_le32(&prci->devicesresetreg, PRCI_RESET_DDR_PHY_RST_N); + for(int i = 0; i<256; i++) + mb(); +} + +void clock_init(void) +{ + init_pll_core(); + + // put all peripherals in reset + write32(&prci->devicesresetreg, 0); + init_pll_ddr(); + + my_sdram_init(); +} diff --git a/src/soc/sifive/fu540/include/soc/clock.h b/src/soc/sifive/fu540/include/soc/clock.h new file mode 100644 index 0000000..cc868e3 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/clock.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Philipp Hug <philipp(a)hug.cx> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_CLOCK_H__ +#define __SOC_SIFIVE_HIFIVE_U_CLOCK_H__ + +#define PRCI_CORECLKSEL_CORECLKSEL 1 + +void clock_init(void); +int clock_get_coreclk_khz(void); + +#endif /* __SOC_SIFIVE_HIFIFE_U_CLOCK_H__ */ -- To view, visit https://review.coreboot.org/27439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iba0669e08940e373aaf42cbba3a1ceffd68a4f52 Gerrit-Change-Number: 27439 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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coreboot-gerrit July 2018