coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

1 participants
877 discussions

Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Ricky Liang (Code Review) 11 Jul '18

11 Jul '18

Ricky Liang has posted comments on this change. ( https://review.coreboot.org/27433 ) Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27433/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h: https://review.coreboot.org/#/c/27433/1/src/mainboard/google/poppy/variants… PS1, Line 44: > Is GPP_D8 not connected now? You will have to configure it accordingly in gpio.c: https://review. […] Done -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 1 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Jul 2018 16:11:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Ricky Liang (Code Review) 11 Jul '18

11 Jul '18

Hello Tomasz Figa, Nick Vaccaro, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27433 to look at the new patch set (#2). Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board schematics. Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Signed-off-by: Ricky Liang <jcliang(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/27433/2 -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 2 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
by Furquan Shaikh (Code Review) 11 Jul '18

11 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27433 ) Change subject: mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27433/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h: https://review.coreboot.org/#/c/27433/1/src/mainboard/google/poppy/variants… PS1, Line 44: Is GPP_D8 not connected now? You will have to configure it accordingly in gpio.c: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/pop… -- To view, visit https://review.coreboot.org/27433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Gerrit-Change-Number: 27433 Gerrit-PatchSet: 1 Gerrit-Owner: Ricky Liang <jcliang(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Jul 2018 15:57:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/sifive: driver for otp memory
by Philipp Hug (Code Review) 11 Jul '18

11 Jul '18

Philipp Hug has uploaded a new patch set (#2). ( https://review.coreboot.org/27435 ) Change subject: soc/sifive: driver for otp memory ...................................................................... soc/sifive: driver for otp memory Provides minimal functionality to read the SOC s/n from the NeoFuse OTP memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/include/soc/otp.h A src/soc/sifive/fu540/otp.c 3 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27435/2 -- To view, visit https://review.coreboot.org/27435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Gerrit-Change-Number: 27435 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/sifive: driver for otp memory
by build bot (Jenkins) (Code Review) 11 Jul '18

11 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27435 ) Change subject: soc/sifive: driver for otp memory ...................................................................... Patch Set 1: (31 comments) https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c File src/soc/sifive/fu540/otp.c: https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@31 PS1, Line 31: u32 pa; /* Address input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@31 PS1, Line 31: u32 pa; /* Address input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@32 PS1, Line 32: u32 paio; /* Program address input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@32 PS1, Line 32: u32 paio; /* Program address input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@33 PS1, Line 33: u32 pas; /* Program redundancy cell selection input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@33 PS1, Line 33: u32 pas; /* Program redundancy cell selection input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@34 PS1, Line 34: u32 pce; /* OTP Macro enable input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@34 PS1, Line 34: u32 pce; /* OTP Macro enable input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@35 PS1, Line 35: u32 pclk; /* Clock input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@35 PS1, Line 35: u32 pclk; /* Clock input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@36 PS1, Line 36: u32 pdin; /* Write data input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@36 PS1, Line 36: u32 pdin; /* Write data input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@37 PS1, Line 37: u32 pdout; /* Read data output */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@37 PS1, Line 37: u32 pdout; /* Read data output */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@38 PS1, Line 38: u32 pdstb; /* Deep standby mode enable input (active low) */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@38 PS1, Line 38: u32 pdstb; /* Deep standby mode enable input (active low) */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@39 PS1, Line 39: u32 pprog; /* Program mode enable input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@39 PS1, Line 39: u32 pprog; /* Program mode enable input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@40 PS1, Line 40: u32 ptc; /* Test column enable input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@40 PS1, Line 40: u32 ptc; /* Test column enable input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@41 PS1, Line 41: u32 ptm; /* Test mode enable input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@41 PS1, Line 41: u32 ptm; /* Test mode enable input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@42 PS1, Line 42: u32 ptm_rep;/* Repair function test mode enable input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@42 PS1, Line 42: u32 ptm_rep;/* Repair function test mode enable input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@43 PS1, Line 43: u32 ptr; /* Test row enable inpu */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@43 PS1, Line 43: u32 ptr; /* Test row enable inpu */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@44 PS1, Line 44: u32 ptrim; /* Repair function enable input */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@44 PS1, Line 44: u32 ptrim; /* Repair function enable input */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@45 PS1, Line 45: u32 pwe; /* Write enable input (defines program cycle) */ code indent should use tabs where possible https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@45 PS1, Line 45: u32 pwe; /* Write enable input (defines program cycle) */ please, no spaces at the start of a line https://review.coreboot.org/#/c/27435/1/src/soc/sifive/fu540/otp.c@63 PS1, Line 63: // adress to read 'adress' may be misspelled - perhaps 'address'? -- To view, visit https://review.coreboot.org/27435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Gerrit-Change-Number: 27435 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Jul 2018 13:17:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: arch/riscv: provide a monotonic timer using CLINT timer register
by Philipp Hug (Code Review) 11 Jul '18

11 Jul '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/27434 ) Change subject: arch/riscv: provide a monotonic timer using CLINT timer register ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/27434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Gerrit-Change-Number: 27434 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Jul 2018 13:17:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/sifive: driver for otp memory
by Philipp Hug (Code Review) 11 Jul '18

11 Jul '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/27435 Change subject: soc/sifive: driver for otp memory ...................................................................... soc/sifive: driver for otp memory Provides minimal functionality to read the SOC s/n from the NeoFuse OTP memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/include/soc/otp.h A src/soc/sifive/fu540/otp.c 3 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/27435/1 diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 8a2f3a6..6a0355e 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -19,10 +19,12 @@ romstage-y += uart.c romstage-y += media.c +romstage-y += otp.c ramstage-y += uart.c ramstage-y += media.c ramstage-y += cbmem.c +ramstage-y += otp.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/otp.h b/src/soc/sifive/fu540/include/soc/otp.h new file mode 100644 index 0000000..027d57f --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/otp.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Philipp Hug <philipp(a)hug.cx> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_OTP_H__ +#define __SOC_SIFIVE_HIFIVE_U_OTP_H__ + +u32 otp_read_word(u8 idx); +u32 otp_read_serial(void); + +#endif /* __SOC_SIFIVE_HIFIFE_U_OTP_H__ */ diff --git a/src/soc/sifive/fu540/otp.c b/src/soc/sifive/fu540/otp.c new file mode 100644 index 0000000..2326ce2 --- /dev/null +++ b/src/soc/sifive/fu540/otp.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Philipp Hug <philipp(a)hug.cx> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <delay.h> +#include <arch/barrier.h> +#include <arch/io.h> +#include <console/uart.h> +#include <soc/addressmap.h> +#include <soc/otp.h> + +/* + * This is a driver for SiFive's one-time programmable memory, + * documented in the FU540 manual: + * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ + */ + +typedef struct sifive_otp_registers { + u32 pa; /* Address input */ + u32 paio; /* Program address input */ + u32 pas; /* Program redundancy cell selection input */ + u32 pce; /* OTP Macro enable input */ + u32 pclk; /* Clock input */ + u32 pdin; /* Write data input */ + u32 pdout; /* Read data output */ + u32 pdstb; /* Deep standby mode enable input (active low) */ + u32 pprog; /* Program mode enable input */ + u32 ptc; /* Test column enable input */ + u32 ptm; /* Test mode enable input */ + u32 ptm_rep;/* Repair function test mode enable input */ + u32 ptr; /* Test row enable inpu */ + u32 ptrim; /* Repair function enable input */ + u32 pwe; /* Write enable input (defines program cycle) */ +} __packed; + +u32 otp_read_word(u8 idx) +{ + u32 w; + + struct sifive_otp_registers *regs = (void *)(FU540_OTP); + + // wake-up from stand-by + write32(&regs->pdstb, 0x01); + + // enable repair function + write32(&regs->ptrim, 0x01); + + // enable input + write32(&regs->pce, 0x01); + + // adress to read + write32(&regs->pa, idx); + + // cycle clock to read + write32(&regs->pclk, 0x01); + mdelay(1); + + write32(&regs->pclk, 0x00); + mdelay(1); + + w = read32(&regs->pdout); + + // shutdown + write32(&regs->pce, 0x00); + write32(&regs->ptrim, 0x00); + write32(&regs->pdstb, 0x00); + + return w; +} + +u32 otp_read_serial(void) +{ + u32 serial = 0; + u32 serial_n = 0; + for (int i = 0xfe; i > 0; i -= 2) { + serial = otp_read_word(i); + serial_n = otp_read_word(i+1); + if (serial == ~serial_n) + break; + } + return serial; +} -- To view, visit https://review.coreboot.org/27435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Gerrit-Change-Number: 27435 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

1 0

Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by build bot (Jenkins) (Code Review) 11 Jul '18

11 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25382 ) Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... Patch Set 37: (4 comments) https://review.coreboot.org/#/c/25382/37/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25382/37/src/soc/cavium/cn81xx/soc.c@82 PS37, Line 82: Remove 'phy-handle' if this option is not availble */ 'availble' may be misspelled - perhaps 'available'? https://review.coreboot.org/#/c/25382/37/src/soc/cavium/cn81xx/soc.c@140 PS37, Line 140: /* Extract our MAC address info so we can assign them in the device tree */ line over 80 characters https://review.coreboot.org/#/c/25382/37/src/soc/cavium/cn81xx/soc.c@172 PS37, Line 172: if (!strcmp(name, prop->prop.name)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25382/37/src/soc/cavium/cn81xx/soc.c@268 PS37, Line 268: BDK_BGXX_CMRX_RX_DMAC_CTL(bgx_interface, bgx_index)); line over 80 characters -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 37 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Jul 2018 12:07:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/cavium: Enable DRAM test
by build bot (Jenkins) (Code Review) 11 Jul '18

11 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27103 ) Change subject: soc/cavium: Enable DRAM test ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/27103/4/src/soc/cavium/cn81xx/sdram.c File src/soc/cavium/cn81xx/sdram.c: https://review.coreboot.org/#/c/27103/4/src/soc/cavium/cn81xx/sdram.c@93 PS4, Line 93: if (0 != bdk_numa_master()) Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27103/4/src/soc/cavium/cn81xx/sdram.c@97 PS4, Line 97: if (0 == bdk_numa_master()) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Gerrit-Change-Number: 27103 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Jul 2018 12:07:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: device/pci: Add MSI-X helper functions
by build bot (Jenkins) (Code Review) 11 Jul '18

11 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26329 ) Change subject: device/pci: Add MSI-X helper functions ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/#/c/26329/14/src/device/pci_device.c File src/device/pci_device.c: https://review.coreboot.org/#/c/26329/14/src/device/pci_device.c@404 PS14, Line 404: if (addr > 0x100000000ULL && sizeof(void*) == 4) { "(foo*)" should be "(foo *)" -- To view, visit https://review.coreboot.org/26329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Gerrit-Change-Number: 26329 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 11 Jul 2018 12:07:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

← Newer
1
...
59
60
61
62
63
64
65
...
88
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2018