coreboot-gerrit July 2018

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add Pantheon sku-id
by Ivy Jian (Code Review) 11 Jul '18

11 Jul '18

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/27432 Change subject: mb/google/poppy/variants/nami: Add Pantheon sku-id ...................................................................... mb/google/poppy/variants/nami: Add Pantheon sku-id Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4 Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/27432/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 33d6bf3..8080c94 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -178,6 +178,7 @@ switch (sku_id) { case SKU_0_PANTHEON: case SKU_1_PANTHEON: + case SKU_2_PANTHEON: return "vbt-pantheon.bin"; case SKU_0_VAYNE: case SKU_1_VAYNE: -- To view, visit https://review.coreboot.org/27432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4 Gerrit-Change-Number: 27432 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com>

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Change in coreboot[master]: mb/google/octopus/variants/yorp: Enable TBMC device
by Furquan Shaikh (Code Review) 11 Jul '18

11 Jul '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/27431 ) Change subject: mb/google/octopus/variants/yorp: Enable TBMC device ...................................................................... mb/google/octopus/variants/yorp: Enable TBMC device This change enables tablet mode ACPI device for yorp. BUG=b:111264961 CQ-DEPEND=CL:1132686 Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/yorp/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27431/2 -- To view, visit https://review.coreboot.org/27431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Gerrit-Change-Number: 27431 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/octopus/variants/yorp: Enable tablet mode device
by Furquan Shaikh (Code Review) 11 Jul '18

11 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27431 Change subject: mb/google/octopus/variants/yorp: Enable tablet mode device ...................................................................... mb/google/octopus/variants/yorp: Enable tablet mode device This change enables tablet mode ACPI device for yorp. BUG=b:111264961 CQ-DEPEND=CL:1132686 Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/yorp/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27431/1 diff --git a/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h b/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h index 16f931b..48cb584 100644 --- a/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/yorp/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + #endif -- To view, visit https://review.coreboot.org/27431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Gerrit-Change-Number: 27431 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: riscv: src/arch/riscv/bootblock.S
by Xiang Wang (Code Review) 11 Jul '18

11 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27430 to look at the new patch set (#3). Change subject: riscv: src/arch/riscv/bootblock.S ...................................................................... riscv: src/arch/riscv/bootblock.S Add an interface to support cache as ram. Initialize stack pointer for each hart. Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/bootblock.S 1 file changed, 21 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27430/3 -- To view, visit https://review.coreboot.org/27430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Gerrit-Change-Number: 27430 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: src/arch/riscv/bootblock.S
by Xiang Wang (Code Review) 11 Jul '18

11 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27430 to look at the new patch set (#2). Change subject: riscv: src/arch/riscv/bootblock.S ...................................................................... riscv: src/arch/riscv/bootblock.S Add an interface to support cache as ram. Initialize stack pointer for each hart. Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/bootblock.S 1 file changed, 22 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27430/2 -- To view, visit https://review.coreboot.org/27430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Gerrit-Change-Number: 27430 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: src/arch/riscv/bootblock.S
by Xiang Wang (Code Review) 11 Jul '18

11 Jul '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27430 Change subject: riscv: src/arch/riscv/bootblock.S ...................................................................... riscv: src/arch/riscv/bootblock.S Add an interface to support cache as ram. Initialize stack pointer for each hart. Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/bootblock.S 1 file changed, 24 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27430/1 diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 0b5a2b2..0c30f6f 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -34,31 +34,38 @@ # csrw mscratch, a1 - # N.B. This only works on low 4G of the address space + # initialize cache as ram + call cache_as_ram + + # initialize stack point for each hart # and the stack must be page-aligned. - la sp, _estack + # 0xDEADBEEF used to check stack overflow + csrr a0, mhartid + la t0, _stack + slli t1, a0, RISCV_PGSHIFT + add t0, t0, t1 + li t1, 0xDEADBEEF + sd t1, 0(t0) + li t1, RISCV_PGSIZE - HLS_SIZE + add sp, t0, t1 - # poison the stack - la t1, _stack - li t0, 0xdeadbeef - sd t0, 0(t1) - - # make room for HLS and initialize it - addi sp, sp, -HLS_SIZE - - // Once again, the docs and toolchain disagree. - // Rather than get fancy I'll just lock this down - // until it all stabilizes. - //csrr a0, mhartid - csrr a0, 0xf14 - call hls_init - + # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 + # initialize hart-local storage + csrr a0, mhartid + call hls_init + # clear any pending interrupts csrwi mip, 0 # set up the mstatus register for VM call mstatus_init tail main + + // These codes need to be implemented on a specific SoC. + .weak cache_as_ram +cache_as_ram: + ret + -- To view, visit https://review.coreboot.org/27430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409 Gerrit-Change-Number: 27430 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: mb/google/octopus: Enable TBMC device only for phaser
by Furquan Shaikh (Code Review) 11 Jul '18

11 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27429 Change subject: mb/google/octopus: Enable TBMC device only for phaser ...................................................................... mb/google/octopus: Enable TBMC device only for phaser Enabling of TBMC device on AP side requires corresponding support on the EC side as well. Since not all octopus variants have tablet mode support enabled, this change enables TBMC device only for phaser. BUG=b:111264961 Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/octopus/variants/phaser/include/variant/ec.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/27429/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h index 3398875..471495a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h @@ -67,9 +67,6 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -/* Enable Tablet switch */ -#define EC_ENABLE_TBMC_DEVICE - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h index 16f931b..48cb584 100644 --- a/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/phaser/include/variant/ec.h @@ -18,4 +18,7 @@ #include <baseboard/ec.h> +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + #endif -- To view, visit https://review.coreboot.org/27429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8 Gerrit-Change-Number: 27429 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/octopus/variants/bip: Enable EC SW sync
by Furquan Shaikh (Code Review) 11 Jul '18

11 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27428 Change subject: mb/google/octopus/variants/bip: Enable EC SW sync ...................................................................... mb/google/octopus/variants/bip: Enable EC SW sync This change enables EC SW sync for bip by removing GBB flag selection for disabling SW sync. BUG=b:110523189 TEST=Verified that EC SW sync works fine on bip. Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/Kconfig.name 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27428/1 diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index cfe051c..02fabff 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -15,7 +15,6 @@ bool "-> Bip" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_PHASER -- To view, visit https://review.coreboot.org/27428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3 Gerrit-Change-Number: 27428 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: buildgcc: Actually verify checksums
by Martin Roth (Code Review) 11 Jul '18

11 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27426 ) Change subject: buildgcc: Actually verify checksums ...................................................................... Patch Set 1: (2 comments) Welcome, and thanks for the patch. > Build Unstable > https://qa.coreboot.org/job/coreboot-toolchain/444/ : UNSTABLE This is obviously not the fault of this patch. I need to get the builders updated to the new toolchain. https://review.coreboot.org/#/c/27426/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27426/1//COMMIT_MSG@2 PS1, Line 2: olidHal <SolidHal(a)users.noreply.github.com> Could we get a real name and contact information? https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure https://review.coreboot.org/#/c/27426/1/util/crossgcc/buildgcc File util/crossgcc/buildgcc: https://review.coreboot.org/#/c/27426/1/util/crossgcc/buildgcc@323 PS1, Line 323: Tabs, here and below. -- To view, visit https://review.coreboot.org/27426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I132f5f86cd31a001372b19e0f81ad933916d2a83 Gerrit-Change-Number: 27426 Gerrit-PatchSet: 1 Gerrit-Owner: SolidHal (1002051) Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 10 Jul 2018 22:31:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: configure PL1/PL2 for AML
by Roy Mingi Park (Code Review) 10 Jul '18

10 Jul '18

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/27427 Change subject: mb/google/poppy/variants/nocturne: configure PL1/PL2 for AML ...................................................................... mb/google/poppy/variants/nocturne: configure PL1/PL2 for AML This patch updates Power Limit(PL) for AML. - PL1 as 5W TDP as POR - PL2 as 18W TDP as POR BUG=None BRANCH=None TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP. cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power 5000000 (5W TDP) cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power 18000000 (18W TDP) Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/27427/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index fe9f850..7318dc5 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -73,7 +73,7 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 7000, /* PowerLimitMaximum */ + 5000, /* PowerLimitMaximum */ 5000, /* TimeWindowMinimum */ 5000, /* TimeWindowMaximum */ 200 /* StepSize */ @@ -81,7 +81,7 @@ Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 15000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 18000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */ -- To view, visit https://review.coreboot.org/27427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67 Gerrit-Change-Number: 27427 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>

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coreboot-gerrit July 2018