coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

1 participants
877 discussions

Change in coreboot[master]: buildgcc: Actually verify checksums
by SolidHal (Code Review) 10 Jul '18

10 Jul '18

SolidHal has uploaded this change for review. ( https://review.coreboot.org/27426 Change subject: buildgcc: Actually verify checksums ...................................................................... buildgcc: Actually verify checksums buildgcc doesn't verify the checksum of gcc downloaded using download(). This can be verified by modifying the gcc checksum in coreboot/util/crossgcc/sum, which won't cause a failure without this patch Change-Id: I132f5f86cd31a001372b19e0f81ad933916d2a83 Signed-off-by: SolidHal <SolidHal(a)users.noreply.github.com> --- M util/crossgcc/buildgcc 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/27426/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a9d9057..5083773 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -320,6 +320,10 @@ cd tarballs download_showing_percentage $archive cd .. + if ! check_sum $FILE; then + printf "\n${RED}$FILE Failed Checksum Verification${NC}\n" + exit 1 + fi fi if [ ! -f tarballs/$FILE ]; then -- To view, visit https://review.coreboot.org/27426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I132f5f86cd31a001372b19e0f81ad933916d2a83 Gerrit-Change-Number: 27426 Gerrit-PatchSet: 1 Gerrit-Owner: SolidHal (1002051)

1 0

Change in coreboot[master]: soc/cavium: Enable DRAM test
by build bot (Jenkins) (Code Review) 10 Jul '18

10 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27103 ) Change subject: soc/cavium: Enable DRAM test ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/27103/3/src/soc/cavium/cn81xx/sdram.c File src/soc/cavium/cn81xx/sdram.c: https://review.coreboot.org/#/c/27103/3/src/soc/cavium/cn81xx/sdram.c@93 PS3, Line 93: if (0 != bdk_numa_master()) Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27103/3/src/soc/cavium/cn81xx/sdram.c@97 PS3, Line 97: if (0 == bdk_numa_master()) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Gerrit-Change-Number: 27103 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Jul 2018 14:47:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by build bot (Jenkins) (Code Review) 10 Jul '18

10 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25382 ) Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... Patch Set 36: (4 comments) https://review.coreboot.org/#/c/25382/36/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25382/36/src/soc/cavium/cn81xx/soc.c@82 PS36, Line 82: Remove 'phy-handle' if this option is not availble */ 'availble' may be misspelled - perhaps 'available'? https://review.coreboot.org/#/c/25382/36/src/soc/cavium/cn81xx/soc.c@140 PS36, Line 140: /* Extract our MAC address info so we can assign them in the device tree */ line over 80 characters https://review.coreboot.org/#/c/25382/36/src/soc/cavium/cn81xx/soc.c@172 PS36, Line 172: if (!strcmp(name, prop->prop.name)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25382/36/src/soc/cavium/cn81xx/soc.c@268 PS36, Line 268: BDK_BGXX_CMRX_RX_DMAC_CTL(bgx_interface, bgx_index)); line over 80 characters -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 36 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Jul 2018 14:46:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [HACK]cavium/arm-trusted-firmware: Use 9elements ATF
by build bot (Jenkins) (Code Review) 10 Jul '18

10 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25751 ) Change subject: [HACK]cavium/arm-trusted-firmware: Use 9elements ATF ...................................................................... Patch Set 25: (2 comments) https://review.coreboot.org/#/c/25751/25/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25751/25/src/soc/cavium/cn81xx/soc.c@73 PS25, Line 73: void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb", CBFS_TYPE_RAW, &size); line over 80 characters https://review.coreboot.org/#/c/25751/25/src/soc/cavium/common/include/soc/… File src/soc/cavium/common/include/soc/bl31_plat_params.h: https://review.coreboot.org/#/c/25751/25/src/soc/cavium/common/include/soc/… PS25, Line 21: #include <soc/cavium/common/arm-trusted-firmware/plat/cavium/common/include/plat_params.h> line over 80 characters -- To view, visit https://review.coreboot.org/25751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Gerrit-Change-Number: 25751 Gerrit-PatchSet: 25 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Jul 2018 14:46:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP]mb/facebook/satima: Add new port
by Patrick Rudolph (Code Review) 10 Jul '18

10 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27425 Change subject: [WIP]mb/facebook/satima: Add new port ...................................................................... [WIP]mb/facebook/satima: Add new port Add support for satima. TODO: Fill in correct devicetree values Change-Id: I4f972d59ac2243823a77f614c4f92c1666185705 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/mainboard/facebook/satima/Kconfig A src/mainboard/facebook/satima/Kconfig.name A src/mainboard/facebook/satima/Makefile.inc A src/mainboard/facebook/satima/bdk_devicetree.c A src/mainboard/facebook/satima/board.fmd A src/mainboard/facebook/satima/board_info.txt A src/mainboard/facebook/satima/bootblock.c A src/mainboard/facebook/satima/cn81xx-linux.dtsi A src/mainboard/facebook/satima/death.c A src/mainboard/facebook/satima/devicetree.cb A src/mainboard/facebook/satima/mainboard.c A src/mainboard/facebook/satima/memlayout.ld A src/mainboard/facebook/satima/romstage.c A src/mainboard/facebook/satima/sff8104-linux.dts 14 files changed, 1,371 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27425/1 diff --git a/src/mainboard/facebook/satima/Kconfig b/src/mainboard/facebook/satima/Kconfig new file mode 100644 index 0000000..9a6acc9 --- /dev/null +++ b/src/mainboard/facebook/satima/Kconfig @@ -0,0 +1,71 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_FACEBOOK_SATIMA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select COMMON_CBFS_SPI_WRAPPER + select RTC + select SOC_CAVIUM_CN81XX + select SPI_FLASH + select SPI_FLASH_WINBOND + +config MAINBOARD_DIR + string + default "facebook/satima" + +config MAINBOARD_VENDOR + string + default "Facebook" + +config DRAM_SIZE_MB + int + default 8192 + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 0 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0x87E028000000 + +config UART_FOR_CONSOLE + int + depends on DRIVERS_UART + default 0 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAX_CPUS + default 4 + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "SATIMA" + +endif diff --git a/src/mainboard/facebook/satima/Kconfig.name b/src/mainboard/facebook/satima/Kconfig.name new file mode 100644 index 0000000..8830cda --- /dev/null +++ b/src/mainboard/facebook/satima/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FACEBOOK_SATIMA + bool "Satima" diff --git a/src/mainboard/facebook/satima/Makefile.inc b/src/mainboard/facebook/satima/Makefile.inc new file mode 100644 index 0000000..bc4ece3 --- /dev/null +++ b/src/mainboard/facebook/satima/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-y += memlayout.ld +bootblock-y += death.c + +romstage-y += memlayout.ld +romstage-y += romstage.c +romstage-y += bdk_devicetree.c +romstage-y += death.c + +ramstage-y += mainboard.c +ramstage-y += memlayout.ld +ramstage-y += bdk_devicetree.c +ramstage-y += death.c + +verstage-y += memlayout.ld +verstage-y += death.c + +MB_DIR = src/mainboard/$(MAINBOARDDIR) + +LINUX_DTB = sff8104-linux.dtb +build/$(LINUX_DTB): + # FIXME: why isn't this producing the correct size DTB? + dtc -p 4096 -I dts -O dtb -o build/$(LINUX_DTB) -i $(MB_DIR) $(MB_DIR)/$(patsubst %.dtb,%.dts,$(LINUX_DTB)) + +cbfs-files-y += $(LINUX_DTB) +$(LINUX_DTB)-file := build/$(LINUX_DTB) +$(LINUX_DTB)-type := raw diff --git a/src/mainboard/facebook/satima/bdk_devicetree.c b/src/mainboard/facebook/satima/bdk_devicetree.c new file mode 100644 index 0000000..6b8a7e4 --- /dev/null +++ b/src/mainboard/facebook/satima/bdk_devicetree.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +// This file is automatically generated. +// DO NOT EDIT BY HAND. + +#include <bdk-devicetree.h> + +const struct bdk_devicetree_key_value devtree[] = { +{"DDR-TEST-BOOT", "0"}, +{"DDR-CONFIG-DQX-CTL", "0x4"}, +{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"}, +{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"}, +{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"}, +{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"}, +{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"}, +{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"}, +{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"}, +{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"}, +{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"}, +{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"}, +{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"}, +{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"}, +{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"}, +{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"}, +{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"}, +{"DDR-CONFIG-CUSTOM-CK-CTL", "0x4"}, +{"DDR-CONFIG-CUSTOM-CMD-CTL", "0x4"}, +{"DDR-CONFIG-CUSTOM-CTL-CTL", "0x4"}, +{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"}, +{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"}, +{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"}, +{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"}, +{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"}, +{"PHY-ADDRESS.N0.BGX0.P0", "0xff000010"}, +{"PHY-ADDRESS.N0.BGX0.P1", "0xff000011"}, +{"PHY-ADDRESS.N0.BGX0.P2", "0xff000012"}, +{"PHY-ADDRESS.N0.BGX0.P3", "0xff000013"}, +{"PHY-ADDRESS.N0.BGX1.P0", "0xff002014"}, +{"PHY-ADDRESS.N0.BGX1.P1", "0xff002014"}, +{"PHY-ADDRESS.N0.BGX2.P0", "0xff000000"}, +{"BGX-ENABLE.N0.BGX0.P0", "1"}, +{"BGX-ENABLE.N0.BGX0.P1", "1"}, +{"BGX-ENABLE.N0.BGX0.P2", "1"}, +{"BGX-ENABLE.N0.BGX0.P3", "1"}, +{"BGX-ENABLE.N0.BGX1.P0", "0"}, +{"BGX-ENABLE.N0.BGX1.P1", "0"}, +{"BGX-ENABLE.N0.BGX2.P0", "0"}, +{"BDK-NUM-PACKET-BUFFERS", "0x1000"}, +{"BDK-PACKET-BUFFER-SIZE", "0x400"}, +{"BDK-SHOW-LINK-STATUS", "1"}, +{"BDK-COREMASK", "0"}, +{"MULTI-NODE", "0"}, +{"QLM-AUTO-CONFIG", "0"}, +{"QLM-DIP-AUTO-CONFIG", "0"}, +{"DDR-SPEED.N0", "1333"}, +{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"}, +{"USB-PWR-GPIO.N0.PORT0", "12"}, +{"USB-PWR-GPIO-POLARITY.N0.PORT0", "0"}, +{"USB-REFCLK-SRC.N0.PORT0", "0"}, +{"GPIO-PIN-SELECT-GPIO15", "0x24f"}, +{"GPIO-PIN-SELECT-GPIO16", "0x24e"}, +{"GPIO-PIN-SELECT-GPIO17", "0x24b"}, +{"GPIO-PIN-SELECT-GPIO18", "0x247"}, +{"GPIO-PIN-SELECT-GPIO19", "0x24d"}, +{"GPIO-PIN-SELECT-GPIO20", "0x24c"}, +{"GPIO-PIN-SELECT-GPIO37", "0x24a"}, +{"GPIO-PIN-SELECT-GPIO38", "0x246"}, +{"GPIO-PIN-SELECT-GPIO7", "0xe1"}, +{"GPIO-PIN-SELECT-GPIO24", "0xeb"}, +{"GPIO-PIN-SELECT-GPIO27", "0xed"}, +{"GPIO-PIN-SELECT-GPIO28", "0xe3"}, +{"GPIO-PIN-SELECT-GPIO29", "0xe0"}, +{"GPIO-PIN-SELECT-GPIO30", "0xe2"}, +{"GPIO-PIN-SELECT-GPIO40", "0x112"}, +{"GPIO-PIN-SELECT-GPIO41", "0x113"}, +{"GPIO-PIN-SELECT-GPIO42", "0x114"}, +{"GPIO-PIN-SELECT-GPIO43", "0x115"}, +{"GPIO-PIN-SELECT-GPIO44", "0x116"}, +{"GPIO-PIN-SELECT-GPIO45", "0x117"}, +{"GPIO-PIN-SELECT-GPIO46", "0x118"}, +{"GPIO-PIN-SELECT-GPIO47", "0x119"}, +{"GPIO-POLARITY-GPIO7", "1"}, +{"GPIO-POLARITY-GPIO27", "1"}, +{"GPIO-POLARITY-GPIO28", "1"}, +{"GPIO-POLARITY-GPIO30", "1"}, +{0, 0}, +}; diff --git a/src/mainboard/facebook/satima/board.fmd b/src/mainboard/facebook/satima/board.fmd new file mode 100644 index 0000000..3a7dbfc --- /dev/null +++ b/src/mainboard/facebook/satima/board.fmd @@ -0,0 +1,27 @@ +FLASH@0x0 16M { + WP_RO@0x0 0x800000 { + RO_SECTION@0x0 0x800000 { + # bootblock includes trusted/non-trusted CLIB, CSIB, + # and BL1FWs packaged in + # src/soc/cavium/common/Makefile.inc. + BOOTBLOCK@0x10000 0x70000 + FMAP@0x80000 0x1000 + COREBOOT(CBFS)@0x90000 0x770000 + } + } + RW_SECTION_A@0x800000 0x100000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0xfdf00 + RW_FWID_A@0xfff00 0x100 + } + RW_SECTION_B@0x900000 0x100000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0xfdf00 + RW_FWID_B@0xfff00 0x100 + } + RW_ELOG@0xfd0000 0x1000 + RW_SHARED@0xfe0000 0x10000 { + SHARED_DATA@0x0 0x10000 + } + RW_NVRAM@0xff0000 0x10000 +} diff --git a/src/mainboard/facebook/satima/board_info.txt b/src/mainboard/facebook/satima/board_info.txt new file mode 100644 index 0000000..6d0d0a8 --- /dev/null +++ b/src/mainboard/facebook/satima/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Facebook +Board name: Satima +Category: network +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/facebook/satima/bootblock.c b/src/mainboard/facebook/satima/bootblock.c new file mode 100644 index 0000000..a8e6961 --- /dev/null +++ b/src/mainboard/facebook/satima/bootblock.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/soc.h> +#include <soc/spi.h> +#include <soc/uart.h> + +void bootblock_mainboard_early_init(void) +{ + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE)) + uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD); + } +} + +static void configure_spi_flash(void) +{ + /* FIXME: Only tested on EM100 Pro */ + spi_init_custom(0, // bus + 12500000, // speed Hz + 0, // idle low disabled + 0, // zero idle cycles between transfers + 0, // MSB first + 0, // Chip select 0 + 1); // assert is high +} + +void bootblock_mainboard_init(void) +{ + configure_spi_flash(); +} diff --git a/src/mainboard/facebook/satima/cn81xx-linux.dtsi b/src/mainboard/facebook/satima/cn81xx-linux.dtsi new file mode 100644 index 0000000..d82b5ac --- /dev/null +++ b/src/mainboard/facebook/satima/cn81xx-linux.dtsi @@ -0,0 +1,496 @@ +/* + * Cavium Thunder DTS file - Thunder SoC description + * + * Copyright (C) 2016, Cavium Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + model = "Cavium ThunderX CN81XX board"; + compatible = "cavium,thunder-81xx"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + /* socket 0 */ + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + }; + + thunderx_L2_0: l2-cache0 { + compatible = "cache"; + numa-node-id = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; + }; + + pmu { + compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; + interrupts = <1 7 4>; + }; + + mmc_supply_3v3: mmc_supply_3v3 { + compatible = "regulator-fixed"; + regulator-name = "mmc_supply_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_6_0 8 0>; + enable-active-high; + }; + + gic0: interrupt-controller@801000000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + #redistributor-regions = <1>; + ranges; + interrupt-controller; + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ + <0x8010 0x80000000 0x0 0x600000>; /* GICR */ + interrupts = <1 9 4>; + + its: gic-its@801000020000 { + compatible = "arm,gic-v3-its"; + reg = <0x8010 0x20000 0x0 0x200000>; + msi-controller; + numa-node-id = <0>; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + numa-node-id = <0>; + + refclkuaa: refclkuaa { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <116640000>; + clock-output-names = "refclkuaa"; + }; + + sclk: sclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sclk"; + }; + + uaa0: serial@87e028000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x28000000 0x0 0x1000>; + interrupts = <0 5 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + uaa1: serial@87e029000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x29000000 0x0 0x1000>; + interrupts = <0 6 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + uaa2: serial@87e02a000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x2a000000 0x0 0x1000>; + interrupts = <0 7 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + uaa3: serial@87e02b000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x2b000000 0x0 0x1000>; + interrupts = <0 8 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + watch-dog@8440000a0000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>; + interrupts = <0 9 4>; + }; + + pbus0: nor@0 { + compatible = "cfi-flash"; + reg = <0x8000 0x0 0x0 0x800000>; + device-width = <1>; + bank-width = <1>; + clocks = <&sclk>; + }; + + smmu0@830000000000 { + compatible = "cavium,smmu-v2"; + reg = <0x8300 0x0 0x0 0x2000000>; + #global-interrupts = <1>; + interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>; + + mmu-masters = <&ecam0 0x100>, + <&pem0 0x200>, + <&pem1 0x300>, + <&pem2 0x400>; + + }; + + ecam0: pci@848000000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0 31>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + u-boot,dm-pre-reloc; + dma-coherent; + reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */ + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */ + <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */ + <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */ + <0x03000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x000 0x94000000>, /* PEMs */ + <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */ + <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/ + <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>; + + mrml_bridge: mrml-bridge0@1,0 { + compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; + #size-cells = <2>; + #address-cells = <3>; + ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>; + reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */ + device_type = "pci"; + u-boot,dm-pre-reloc; + + mdio-nexus@1,3 { + compatible = "cavium,thunder-8890-mdio-nexus"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */ + assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>; + ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>; + mdio0@87e005003800 { + compatible = "cavium,thunder-8890-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x87e0 0x05003800 0x0 0x30>; + }; + mdio1@87e005003880 { + compatible = "cavium,thunder-8890-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x87e0 0x05003880 0x0 0x30>; + }; + }; + + mmc_1_4: mmc@1,4 { + compatible = "cavium,thunder-8890-mmc"; + reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sclk>; + }; + + i2c_9_0: i2c@9,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-twsi"; + reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */ + clock-frequency = <100000>; + clocks = <&sclk>; + u-boot,dm-pre-reloc; + }; + + i2c_9_1: i2c@9,1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-twsi"; + reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */ + clock-frequency = <100000>; + clocks = <&sclk>; + u-boot,dm-pre-reloc; + }; + + rgx0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-bgx"; + reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */ + }; + bgx0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-bgx"; + reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */ + }; + bgx1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-bgx"; + reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */ + }; + }; + + spi_7_0: spi@7,0 { + compatible = "cavium,thunder-8190-spi"; + reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sclk>; + }; + + gpio_6_0: gpio0@6,0 { + #gpio-cells = <2>; + compatible = "cavium,thunder-8890-gpio"; + gpio-controller; + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ + u-boot,dm-pre-reloc; + }; + + nfc: nand@b,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,cn8130-nand"; + reg = <0x5800 0 0 0 0>; /* DEVFN = 0x58 (b:0) */ + clocks = <&sclk>; + }; + }; + + pem0: pci@87e0c0000000 { + + /* "cavium,pci-host-thunder-pem" implies that + the first bus in bus-range has config access + via the "PEM space", subsequent buses have + config assess via the "Configuration space". + The "mem64 PEM" range is used to map the PEM + BAR0, which is used by the AER and PME MSI-X + sources. UEFI and Linux must assign the same + bus number to each device, otherwise Linux + enumeration gets confused. Because UEFI + skips the PEM bus and its PCIe-RC bridge it + uses a numbering that starts 1 bus higher. + */ + + compatible = "cavium,pci-host-thunder-pem"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0x1f 0x57>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + dma-coherent; + reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */ + <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */ + ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */ + <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */ + <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */ + <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */ + <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */ + <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */ + <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */ + }; + + pem1: pci@87e0c1000000 { + compatible = "cavium,pci-host-thunder-pem"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0x57 0x8f>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + dma-coherent; + reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */ + <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */ + ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */ + <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */ + <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */ + <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */ + <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */ + <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */ + <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */ + }; + + pem2: pci@87e0c2000000 { + compatible = "cavium,pci-host-thunder-pem"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0x8f 0xc7>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + dma-coherent; + reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ + <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */ + ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ + <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ + <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ + <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ + <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ + <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ + <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ + }; + + tdm: tdm@d,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8190-tdm"; + reg = <0x6800 0 0 0>; /* DEVFN = 0x68 (d:0) */ + clocks = <&sclk>; + }; + }; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + serial2 = &uaa2; + serial3 = &uaa3; + i2c0 = &i2c_9_0; + i2c1 = &i2c_9_1; + spi0 = &spi_7_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + + memory@0 { + device_type = "memory"; + reg = <0x0 0x01400000 0x0 0x7EC00000>; + /* socket 0 */ + numa-node-id = <0>; + }; +}; diff --git a/src/mainboard/facebook/satima/death.c b/src/mainboard/facebook/satima/death.c new file mode 100644 index 0000000..1e64e15 --- /dev/null +++ b/src/mainboard/facebook/satima/death.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <soc/gpio.h> +#include <console/console.h> +#include <delay.h> + +void die_notify(void) +{ + const u32 rate = 1000 / 5; // blink at 5 Hz + + do { + gpio_output(11, 0); + mdelay(rate); + gpio_output(11, 1); + mdelay(rate); + } while(1); +} diff --git a/src/mainboard/facebook/satima/devicetree.cb b/src/mainboard/facebook/satima/devicetree.cb new file mode 100644 index 0000000..07d508a --- /dev/null +++ b/src/mainboard/facebook/satima/devicetree.cb @@ -0,0 +1,210 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/cavium/cn81xx + device cpu_cluster 0 on end + + device domain 0 on + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.0 on # PCI bridge + chip soc/cavium/common/pci + register "secure" = "0" + device pci 00.0 on end # MRML + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 00.1 on end # RESET + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 00.2 on end # DAP + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 00.3 on end # MDIO + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 00.4 on end # FUSE + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.2 on end # SGPIO + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.3 on end # SMI + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.4 on end # MMC + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 01.5 on end # KEY + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 01.6 on end # BOOT BUS + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 01.7 on end # PBUS + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 02.0 on end # XCV + end + device pci 04.0 on end + + chip soc/cavium/common/pci + register "secure" = "0" + device pci 06.0 on end # L2C-TAD + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 07.0 on end # L2C-CBC + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 07.4 on end # L2C-MCI + end + + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.0 on end # UUA0 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.1 on end # UUA1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.2 off end # UUA2 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.3 off end # UUA3 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 08.4 on end # VRM + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 09.0 on end # I2C0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 09.1 on end # I2C1 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 0a.0 on end # PCC Bridge + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0b.0 on end # IOBN + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 0c.0 on end # OCLA0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 0c.1 on end # OCLA1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0d.0 on end + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0e.0 on end # PCIe0 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0e.1 on end # PCIe1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 0e.2 on end # PCIe2 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 10.0 on end # bgx0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 10.1 off end # bgx1 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 11.0 on end # rgx0 + end + chip soc/cavium/common/pci + register "secure" = "0" + device pci 12.0 on end # MAC + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.0 on end # GSER0 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.1 on end # GSER1 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.2 on end # GSER2 + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 1c.3 on end # GSER3 + end + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 02.0 on end #SMMU + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 03.0 on end #GIC + end + chip soc/cavium/common/pci + register "secure" = "1" + device pci 04.0 on end #GTI + end + + device pci 05.0 on end # NIC + device pci 06.0 on end # GPIO + device pci 07.0 on end # SPI + device pci 08.0 on end # MIO + device pci 09.0 on end # PCI bridge + device pci 0a.0 on end # PCI bridge + device pci 0b.0 on end # NFC + device pci 0c.0 on end # PCI bridge + device pci 0d.0 on end # PCM + device pci 0e.0 on end # VRM + device pci 0f.0 on end # PCI bridge + + device pci 10.0 on end # USB0 + device pci 11.0 on end # USB1 + device pci 16.0 on end # SATA0 + device pci 17.0 on end # SATA1 + end + end +end diff --git a/src/mainboard/facebook/satima/mainboard.c b/src/mainboard/facebook/satima/mainboard.c new file mode 100644 index 0000000..9636715 --- /dev/null +++ b/src/mainboard/facebook/satima/mainboard.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. (support(a)cavium.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. + */ + +#include <device/device.h> +#include <libbdk-hal/bdk-config.h> +#include <libbdk-hal/bdk-twsi.h> +#include <soc/gpio.h> +#include <delay.h> +#include <soc/uart.h> +#include <console/console.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/timer.h> +#include <soc/cpu.h> +#include <soc/sdram.h> +#include <libbdk-hal/bdk-config.h> + +static void mainboard_print_info(void) +{ + printk(BIOS_INFO, "MB: trusted boot : %s\n", + gpio_strap_value(10) ? "yes" : "no"); + + const size_t boot_method = gpio_strap_value(0) | + (gpio_strap_value(1) << 1) | + (gpio_strap_value(2) << 2) | + (gpio_strap_value(3) << 3); + + printk(BIOS_INFO, "MB: boot method : "); + switch (boot_method) { + case 0x2: + case 0x3: + printk(BIOS_INFO, "EMMC\n"); + break; + case 0x5: + case 0x6: + printk(BIOS_INFO, "SPI\n"); + break; + case 0x8: + printk(BIOS_INFO, "REMOTE\n"); + break; + case 0xc: + case 0xd: + printk(BIOS_INFO, "PCIe\n"); + break; + default: + printk(BIOS_INFO, "unknown\n"); + } + + printk(BIOS_INFO, "MB: REFclk : %llu MHz\n", + thunderx_get_ref_clock() / 1000000ULL); + + printk(BIOS_INFO, "MB: IOclk : %llu MHz\n", + thunderx_get_io_clock() / 1000000ULL); + + printk(BIOS_INFO, "MB: COREclk : %llu MHz\n", + thunderx_get_core_clock() / 1000000ULL); + + printk(BIOS_INFO, "MB: #CPU cores : %zu\n", + cpu_get_num_available_cores()); + + printk(BIOS_INFO, "MB: RAM : %zu MiB\n", + sdram_size_mb()); +} + +extern const struct bdk_devicetree_key_value devtree[]; + +static void mainboard_init(struct device *dev) +{ + size_t i; + + /* Init UARTs */ + for (i = 0; i < 4; i++) { + if (!uart_is_enabled(i)) + uart_setup(i, 0); + } + + /* Init timer */ + soc_timer_init(); + + /* Init CPUs */ + for (i = 1; i < CONFIG_MAX_CPUS; i++) + start_cpu(i, NULL); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; + + bdk_config_set_fdt(devtree); + + mainboard_print_info(); +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/facebook/satima/memlayout.ld b/src/mainboard/facebook/satima/memlayout.ld new file mode 100644 index 0000000..9349362 --- /dev/null +++ b/src/mainboard/facebook/satima/memlayout.ld @@ -0,0 +1 @@ + #include <soc/memlayout.ld> diff --git a/src/mainboard/facebook/satima/romstage.c b/src/mainboard/facebook/satima/romstage.c new file mode 100644 index 0000000..e8e5cd6 --- /dev/null +++ b/src/mainboard/facebook/satima/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/exception.h> +#include <cbmem.h> +#include <romstage_handoff.h> +#include <soc/sdram.h> +#include <soc/timer.h> +#include <soc/mmu.h> +#include <stdlib.h> +#include <console/console.h> +#include <program_loading.h> +#include <libbdk-hal/bdk-config.h> +#include <string.h> + +extern const struct bdk_devicetree_key_value devtree[]; + +void main(void) +{ + watchdog_poke(0); + + console_init(); + exception_init(); + + bdk_config_set_fdt(devtree); + + sdram_init(); + soc_mmu_init(); + + watchdog_poke(0); + + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/mainboard/facebook/satima/sff8104-linux.dts b/src/mainboard/facebook/satima/sff8104-linux.dts new file mode 100644 index 0000000..ff0121e --- /dev/null +++ b/src/mainboard/facebook/satima/sff8104-linux.dts @@ -0,0 +1,156 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2016, Cavium Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "cn81xx-linux.dtsi" + +&mrml_bridge { + mdio-nexus@1,3 { + mdio0@87e005003800 { + rgmii00: rgmii00 { + reg = <0> ; + compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; + }; + + qsgmii00: qsgmii00 { + qlm-mode = "0x000,qsgmii"; + reg = <0x10> ; + compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; + }; + }; + mdio1@87e005003880 { + xfi00: xfi00 { + qlm-mode = "0x000,xfi"; + reg = <0x0>; + compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + rgx0 { + rgmii00 { + reg = <0>; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&rgmii00>; + }; + }; + + bgx0 { + /* typename+qlm+typenumber eg : + qsgmii+bgx0+sgmmi0 + */ + qsgmii00 { + reg = <0>; + qlm-mode = "0x000,qsgmii"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&qsgmii00>; + }; + }; +}; + +&mmc_1_4 { + /* NOTE: the BDK is responsible for swapping the two slots. + * Unfortunately there does not appear to be any way to read the + * position of SW2-7 in software. + */ + mmc-slot@0 { + compatible = "mmc-slot"; + reg = <0>; + vmmc-supply = <&mmc_supply_3v3>; + max-frequency = <26000000>; + /* 1.8v is not supported */ + no-1-8-v; + /* Bus width is only 4 bits maximum */ + bus-width = <4>; + /* No write-protect switch is present */ + disable-wp; + /* There is no card detection available; polling must be used. */ + broken-cd; + /* High-speed mode is supported */ + cap-sd-highspeed; + /* speed up device probing */ + no-sdio; + no-mmc; + }; + mmc-slot@1 { + compatible = "mmc-slot"; + reg = <1>; + vmmc-supply = <&mmc_supply_3v3>; + max-frequency = <26000000>; + mmc-ddr-3_3v; + /* 1.8v is not supported */ + no-1-8-v; + /* Bus width is only 8 bits maximum */ + bus-width = <8>; + /* No write-protect switch is present */ + disable-wp; + /* There is no card detection available; polling must be used. */ + broken-cd; + /* High-speed mode is supported */ + cap-mmc-highspeed; + /* eMMC device is soldered onto the board */ + non-removable; + /* speed up device probing */ + no-sdio; + no-sd; + }; +}; + +&spi_7_0 { + flash@0 { + compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <16000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + flash@1 { + compatible = "spinand,mt29f", "mt29f"; + reg = <0x1>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "none"; + }; +}; -- To view, visit https://review.coreboot.org/27425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4f972d59ac2243823a77f614c4f92c1666185705 Gerrit-Change-Number: 27425 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: riscv: add spin lock support
by build bot (Jenkins) (Code Review) 10 Jul '18

10 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27356 ) Change subject: riscv: add spin lock support ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/27356/12/src/arch/riscv/include/arch/smp/sp… File src/arch/riscv/include/arch/smp/spinlock.h: https://review.coreboot.org/#/c/27356/12/src/arch/riscv/include/arch/smp/sp… PS12, Line 29: while (atomic_swap(&lock->lock, -1)); trailing statements should be on next line -- To view, visit https://review.coreboot.org/27356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Gerrit-Change-Number: 27356 Gerrit-PatchSet: 12 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 10 Jul 2018 13:59:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/google/kahlee: Init careena WLAN card at PCIe Gen 1
by build bot (Jenkins) (Code Review) 10 Jul '18

10 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27424 ) Change subject: mainboard/google/kahlee: Init careena WLAN card at PCIe Gen 1 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27424/1/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/careena/OemCustomize.c: https://review.coreboot.org/#/c/27424/1/src/mainboard/google/kahlee/variant… PS1, Line 148: VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/27424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib692d202a7fe67195a390553f70d60a9d955b6d8 Gerrit-Change-Number: 27424 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Jul 2018 03:48:15 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mainboard/google/kahlee: Init careena WLAN card at PCIe Gen 1
by Martin Roth (Code Review) 10 Jul '18

10 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27424 Change subject: mainboard/google/kahlee: Init careena WLAN card at PCIe Gen 1 ...................................................................... mainboard/google/kahlee: Init careena WLAN card at PCIe Gen 1 The WLAN card used for careena does not enumerate correctly if set to a higer speed, so set the max speed to Gen 1. BUG=b:110449139 TEST=Boot careena, verify that the wlan card is present. Change-Id: Ib692d202a7fe67195a390553f70d60a9d955b6d8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/careena/Makefile.inc A src/mainboard/google/kahlee/variants/careena/OemCustomize.c M src/mainboard/google/kahlee/variants/grunt/Makefile.inc 3 files changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27424/1 diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index 0579e18..3b14bf3 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -16,5 +16,6 @@ subdirs-y += ../baseboard/spd romstage-y += ../baseboard/romstage.c +romatage-y += OemCustomize.c ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/careena/OemCustomize.c b/src/mainboard/google/kahlee/variants/careena/OemCustomize.c new file mode 100644 index 0000000..ac93712 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/careena/OemCustomize.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <compiler.h> +#include <amdblocks/agesawrapper.h> +#include <variant/gpio.h> +#include <boardid.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 1, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + 0, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeMob0db, /* mChannelType */ + 2, /* mDevAddress */ + 2, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGen1, /* mPcieGen1 */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_0_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 3, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_1_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2( + PortEnabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 4, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_2_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, + /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2( + PortDisabled, /* mPortPresent */ + ChannelTypeExt6db, /* mChannelType */ + 2, /* mDevAddress */ + 5, /* mDevFunction */ + HotplugDisabled, /* mHotplug */ + PcieGenMaxSupported, /* mMaxLinkSpeed */ + PcieGenMaxSupported, /* mMaxLinkCap */ + AspmL0sL1, /* mAspm */ + PCIE_3_RST, /* mResetId */ + 0) /* mClkPmSupport */ + }, +}; + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DDI0 - eDP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1) + }, + /* DDI1 - DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DDI2 - DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; + InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; + InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; + +} diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc index 0579e18..d5ad4ed 100644 --- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc @@ -16,5 +16,6 @@ subdirs-y += ../baseboard/spd romstage-y += ../baseboard/romstage.c +romstage-y += ../baseboard/OemCustomize.c ramstage-y += ../baseboard/mainboard.c -- To view, visit https://review.coreboot.org/27424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib692d202a7fe67195a390553f70d60a9d955b6d8 Gerrit-Change-Number: 27424 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mb/google/atlas: MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 10 Jul '18

10 Jul '18

Ping-chung Chen has posted comments on this change. ( https://review.coreboot.org/27350 ) Change subject: mb/google/atlas: MIPI camera ASL files for Atlas ...................................................................... Patch Set 7: (3 comments) https://review.coreboot.org/#/c/27350/5/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl: https://review.coreboot.org/#/c/27350/5/src/mainboard/google/poppy/variants… PS5, Line 32: : > Tab needed Done https://review.coreboot.org/#/c/27350/5/src/mainboard/google/poppy/variants… PS5, Line 62: > FCPR naming convention is used to refer that it'a front camera. […] This is front camera. https://review.coreboot.org/#/c/27350/5/src/mainboard/google/poppy/variants… PS5, Line 123: > I don't believe SSDB is currently used. Please remove. Done -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 7 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Jul 2018 03:21:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/atlas: MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 10 Jul '18

10 Jul '18

Hello Rajmohan Mani, JasonX Z Chen, Andy Yeh, Hyungwoo Yang, Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27350 to look at the new patch set (#7). Change subject: mb/google/atlas: MIPI camera ASL files for Atlas ...................................................................... mb/google/atlas: MIPI camera ASL files for Atlas Atlas has one sensor, create a single endpoint to CIO2. create power resource for enabling/disabling camera. BUG=b:111141128 Branch=None TEST=Testing (WIP) on Atlas board Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Signed-off-by: Ping-Chung Chen <ping-chung.chen(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl M src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h 7 files changed, 214 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27350/7 -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 7 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

← Newer
1
...
62
63
64
65
66
67
68
...
88
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2018