coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: vendorcode/intel/skykabylake: Update FSP UPD header files
by Aamir Bohra 03 Feb '17

03 Feb '17

Aamir Bohra (aamir.bohra(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18289 -gerrit commit 74c775a50c554693ac0d2a9c5cd345f26bafb875 Author: Aamir Bohra <aamir.bohra(a)intel.com> Date: Thu Feb 2 22:05:02 2017 +0530 vendorcode/intel/skykabylake: Update FSP UPD header files Update FSP UPD header files as per version 1.6.0 BUG=None BRANCH=None TEST=Verify build and boot RVP3 and poppy Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/FspUpd.h | 2 +- .../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 5 ++- .../intel/fsp/fsp2_0/skykabylake/FspsUpd.h | 49 ++++++++++++++++------ 3 files changed, 41 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h index 4981f21..bea3509 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h index 3e65f0a..89dc419 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -773,7 +773,8 @@ typedef struct { UINT8 HyperThreading; /** Offset 0x02D4 - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. + Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. @note If disabled, + BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting. $EN_DIS **/ UINT8 CpuRatioOverride; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h index 0120cf8..f2cc9b4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -363,9 +363,16 @@ typedef struct { **/ UINT8 PchLanEnable; -/** Offset 0x00FC +/** Offset 0x00FC - Delay USB PDO Programming + Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: + disable, 1: enable + $EN_DIS +**/ + UINT8 DelayUsbPdoProgramming; + +/** Offset 0x00FD **/ - UINT8 UnusedUpdSpace3[24]; + UINT8 UnusedUpdSpace3[23]; /** Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for @@ -739,7 +746,7 @@ typedef struct { UINT8 SendVrMbxCmd1; /** Offset 0x02E4 - CpuS3ResumeMtrrData - Pointer CPU S3 Resume MTRR Data + Pointer to CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData; @@ -2041,9 +2048,15 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0779 +/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid + The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. + $EN_DIS +**/ + UINT8 MeUnconfigIsValid; + +/** Offset 0x077A **/ - UINT8 ReservedFspsUpd[7]; + UINT8 ReservedFspsUpd[6]; } FSP_S_CONFIG; /** Fsp S Test Configuration @@ -2517,14 +2530,16 @@ typedef struct { **/ UINT8 C1e; -/** Offset 0x07DA - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. Disable; 1: Enable +/** Offset 0x07DA - Enable or Disable Package C-State Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; 2: Auto + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable +/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion + Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; 2: Auto + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateUnDemotion; @@ -2772,11 +2787,21 @@ typedef struct { **/ UINT16 PsysPmax; -/** Offset 0x087E - ReservedCpuPostMemTest +/** Offset 0x087E - CpuS3ResumeDataSize + Size of CPU S3 Resume Data +**/ + UINT16 CpuS3ResumeDataSize; + +/** Offset 0x0880 - CpuS3ResumeData + Pointer to CPU S3 Resume Data +**/ + UINT32 CpuS3ResumeData; + +/** Offset 0x0884 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[12]; + UINT8 ReservedCpuPostMemTest[6]; /** Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values

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Patch set updated for coreboot: vendorcode/intel/skykabylake: Update CpuConfigFspData.h file
by Aamir Bohra 03 Feb '17

03 Feb '17

Aamir Bohra (aamir.bohra(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18285 -gerrit commit 9afac37cfd6616c6d0605cebf33fd3082f802f53 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Feb 3 13:28:46 2017 +0530 vendorcode/intel/skykabylake: Update CpuConfigFspData.h file The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=chrome-os-partner:61548 BRANCH=none TEST=Build and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index 8fd41e0..c8cdc5f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -62,9 +62,9 @@ typedef union { UINT32 TxtEnable : 1; UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use - EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + UINT32 Reserved; } Bits; - UINT32 Uint32[3]; + UINT32 Uint32[2]; } CPU_CONFIG_FSP_DATA; #pragma pack (pop)

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Patch set updated for coreboot: vendorcode/intel/skykabylake: Update CpuConfigFspData.h file
by Rizwan Qureshi 03 Feb '17

03 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18285 -gerrit commit e77ad57fc73891bf5f69afd18fa57dde4560ad26 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Feb 3 13:28:46 2017 +0530 vendorcode/intel/skykabylake: Update CpuConfigFspData.h file The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=chrome-os-partner:61548 BRANCH=none TEST=Build and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index 8fd41e0..c8cdc5f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -62,9 +62,9 @@ typedef union { UINT32 TxtEnable : 1; UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use - EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + UINT32 Reserved; } Bits; - UINT32 Uint32[3]; + UINT32 Uint32[2]; } CPU_CONFIG_FSP_DATA; #pragma pack (pop)

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Patch merged into coreboot/master: mainboard/google/snappy: Set PL2 override to 15000mW
by gerrit＠coreboot.org 03 Feb '17

03 Feb '17

the following patch was just integrated into master: commit 4a282b84192d4b8ba62521c0dc87db1872853ab0 Author: Harry Pan <harry.pan(a)intel.com> Date: Thu Feb 2 15:42:25 2017 +0800 mainboard/google/snappy: Set PL2 override to 15000mW This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:62110 BRANCH=reef TEST=Apply new firmware to evaluate Octane benchmark score. Change-Id: I51734051586753677129314b5273fb275c74f5d2 Signed-off-by: Harry Pan <harry.pan(a)intel.com> Reviewed-on: https://review.coreboot.org/18283 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18283 for details. -gerrit

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Patch set updated for coreboot: device/dram/ddr2: Add common ddr2 spd decoder
by Patrick Rudolph 03 Feb '17

03 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18273 -gerrit commit 66fbb3c28d16bbc66726f793570bad0dc85199f2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 31 19:43:17 2017 +0100 device/dram/ddr2: Add common ddr2 spd decoder Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Kconfig | 4 + src/device/dram/Makefile.inc | 1 + src/device/dram/ddr2.c | 575 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 201 ++++++++++++++ 4 files changed, 781 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..7e8e50f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -214,6 +214,10 @@ config SPD_CACHE bool default n +config SPD_DDR2 + bool + default n + config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..9b0016a 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-$(CONFIG_SPD_DDR2) += ddr2.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c new file mode 100644 index 0000000..82e4e87 --- /dev/null +++ b/src/device/dram/ddr2.c @@ -0,0 +1,575 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file ddr2.c + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr2.h> +#include <string.h> + +/*============================================================================== + * = DDR2 SPD decoding helpers + *----------------------------------------------------------------------------*/ + +/** + * \brief Checks if the DIMM is Registered based on byte[20] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[20] of the SPD. + */ +int dimm_is_registered(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Calculate the checksum of a DDR2 SPD unique identifier + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the checksum of SPD data bytes 63, or 0 when spd data is truncated. + */ +u8 spd_ddr2_calc_checksum(u8 *spd, int len) +{ + int i; + u8 c = 0; + + if (len < 63) + /* Not enough bytes available to get the checksum */ + return 0; + + for (i = 0; i < 63; i++) + c += spd[i]; + + return c; +} + +/** + * \brief Return size of SPD. + * + * Returns size of SPD. Usually 128 Byte. + */ +u32 spd_decode_spd_size_ddr2(u8 byte0) +{ + return byte0; +} + +/** + * \brief Return size of eeprom. + * + * Returns size of eeprom. Usually 256 Byte. + */ +u32 spd_decode_eeprom_size_ddr2(u8 byte1) +{ + if (!byte1) + return 0; + + if (byte1 > 0x0e) + return 0x3fff; + + return 1 << byte1; +} + +/** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_msbs(u8 c) +{ + int i; + for (i = 7; i >= 0; i--) + if (c & (1 << i)) + return i; + + return 0; +} + +/** + * \brief Decode SPD tck cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_tck_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + + low = c & 0xf; + if (low == 0x0A) + low = 25; + else if (low == 0x0B) + low = 33; + else if (low == 0x0C) + low = 66; + else if (low == 0x0D) + low = 75; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD bcd style timings + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_bcd_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + low = c & 0xf; + + return ((high << 8) / 10) + ((low << 8) / 100); +} + +/** + * \brief Decode SPD tRP, tRRP cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_quarter_time(u8 c) +{ + u8 high, low; + + high = c >> 2; + low = 25 * (c & 0x3); + + return (high << 8) + ((low << 8) / 100); +} + +/** + * \brief Decode SPD tRR time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static u32 spd_decode_tRR_time(u8 c) +{ + switch (c) { + default: + case 0: + return 15625 << 8; + case 1: + return 15625 << 6; + case 2: + return 15625 << 7; + case 3: + return 15625 << 9; + case 4: + return 15625 << 10; + case 5: + return 15625 << 11; + } +} + +/** + * \brief Decode SPD tRP,tRFC time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC) +{ + u8 b40, b41, b42; + + b40 = spd_40_41_42[0]; + b41 = spd_40_41_42[1]; + b42 = spd_40_41_42[2]; + + *tRC = b41 << 8; + *tRFC = b42 << 8; + + if (b40 & 0x01) + *tRFC += 256 << 8; + + switch ((b40 >> 1) & 0x07) { + case 1: + *tRFC += (25 << 8) / 100; + break; + case 2: + *tRFC += (33 << 8) / 100; + break; + case 3: + *tRFC += (50 << 8) / 100; + break; + case 4: + *tRFC += (66 << 8) / 100; + break; + case 5: + *tRFC += (75 << 8) / 100; + break; + default: + break; + } + + switch ((b40 >> 4) & 0x07) { + case 1: + *tRC += (25 << 8) / 100; + break; + case 2: + *tRC += (33 << 8) / 100; + break; + case 3: + *tRC += (50 << 8) / 100; + break; + case 4: + *tRC += (66 << 8) / 100; + break; + case 5: + *tRC += (75 << 8) / 100; + break; + default: + break; + } +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR2 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd) +{ + int ret; + u16 eeprom_size; + u8 spd_size; + u8 cl; + u8 reg8; + + memset(dimm, 0, sizeof(*dimm)); + + spd_size = spd_decode_spd_size_ddr2(spd[0]); + eeprom_size = spd_decode_eeprom_size_ddr2(spd[1]); + + printram("EEPROM with 0x%04x bytes\n", eeprom_size); + printram("SPD contains 0x%02x bytes\n", spd_size); + + if (spd_size < 64 || eeprom_size < 64) { + printram("ERROR: SPD to small\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { + printram("ERROR: SPD checksum error\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + reg8 = spd[62]; + if ((reg8 & 0xf0) != 0x10) { + printram("ERROR: Unsupported SPD revision %01x.%01x\n", + reg8 >> 4, reg8 & 0xf); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Revision : %01x.%01x\n", reg8 >> 4, reg8 & 0xf); + + reg8 = spd[2]; + if (reg8 != 0x08) { + printram("ERROR: Unsupported SPD type %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Type : 0x%02x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR2; + + dimm->row_bits = spd[3]; + if (dimm->row_bits > 31) { + printram(" Invalid number of memory rows\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Rows : %u\n", dimm->row_bits); + + dimm->col_bits = spd[4]; + if (dimm->col_bits > 16) { + printram(" Invalid number of memory columns\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Columns : %u\n", dimm->col_bits); + + dimm->ranks = (spd[5] & 0x7) + 1; + printram(" Ranks : %u\n", dimm->ranks); + + dimm->mod_width = spd[6]; + printram(" Module width : x%u\n", dimm->mod_width); + + dimm->width = spd[13]; + printram(" Width : x%u\n", dimm->width); + + dimm->banks = spd[17]; + printram(" Banks : %u\n", dimm->banks); + + switch (spd[8]) { + case 0: + dimm->flags.operable_5_00V = 1; + printram(" Voltage : 5.0V\n"); + break; + case 1: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 2: + dimm->flags.operable_1_50V = 1; + printram(" Voltage : 1.5V\n"); + break; + case 3: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 4: + dimm->flags.operable_2_50V = 1; + printram(" Voltage : 2.5V\n"); + break; + case 5: + dimm->flags.operable_1_80V = 1; + printram(" Voltage : 1.8V\n"); + break; + default: + printram(" Unknown voltage level.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->cas_supported = spd[18]; + if (dimm->cas_supported & 0x3) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported); + + /* CL=X */ + cl = spd_get_msbs(dimm->cas_supported); + + /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */ + dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); + /* SDRAM Access from Clock */ + dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); + + if (dimm->cas_supported & (1 << (cl - 1))) { + /* Minimum Clock Cycle at CLX-1 */ + dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]); + /* Maximum Data Access Time (tAC) from Clock at CLX-1 */ + dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]); + } + if (dimm->cas_supported & (1 << (cl - 2))) { + /* Minimum Clock Cycle at CLX-2 */ + dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]); + /* Maximum Data Access Time (tAC) from Clock at CLX-2 */ + dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]); + } + + /* Module Rank Density */ + reg8 = (spd[31] >> 5) | (spd[31] << 3); + dimm->size_mb = 128 * reg8; + if (dimm->size_mb < 1024) + printram(" Capacity : %u MB\n", dimm->size_mb); + else + printram(" Capacity : %u GB\n", dimm->size_mb >> 10); + + /* SDRAM Maximum Cycle Time (tCKmax) */ + dimm->tCK = spd_decode_tck_time(spd[43]); + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd_decode_quarter_time(spd[36]); + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd_decode_quarter_time(spd[29]); + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd_decode_quarter_time(spd[28]); + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd_decode_quarter_time(spd[27]); + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = spd[30] << 8; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + spd_decode_tRPtRFC_time(&spd[40], &dimm->tRC, &dimm->tRFC); + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd_decode_quarter_time(spd[37]); + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd_decode_quarter_time(spd[38]); + /* Data Input Setup Time Before Strobe */ + dimm->tDS = spd_decode_bcd_time(spd[34]); + /* Data Input Hold Time After Strobe */ + dimm->tDH = spd_decode_bcd_time(spd[35]); + /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */ + dimm->tDQSQ = (spd[44] << 8) / 100; + /* SDRAM Device Maximum Read Data Hold Skew Factor */ + dimm->tQHS = (spd[45] << 8) / 100; + /* PLL Relock Time in us */ + dimm->tPLL = spd[46] << 8; + /* Refresh rate in us */ + dimm->tRR = spd_decode_tRR_time(spd[12]); + + /* SDRAM Thermal and Refresh Options */ + printram(" General features :"); + if (spd[22] & 0x04) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if (spd[22] & 0x02) { + dimm->flags.terminate_50ohms = 1; + printram(" 50Ohm"); + } + if (spd[22] & 0x01) { + dimm->flags.weak_driver = 1; + printram(" WEAK_DRIVER"); + } + printram("\n"); + + /* SDRAM Supported Burst length */ + printram(" Burst length :"); + if (spd[16] & 0x06) { + dimm->flags.bl8 = 1; + printram(" BL8"); + } + if (spd[22] & 0x04) { + dimm->flags.bl4 = 1; + printram(" BL4"); + } + printram("\n"); + + dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; + printram(" Dimm type : %x\n", dimm->dimm_type); + + dimm->flags.is_ecc = !!(spd[11] & 0x3); + printram(" ECC support : %x\n", dimm->flags.is_ecc); + + if (spd_size > 71) { + memcpy(&dimm->manufacturer_id, &spd[64], 4); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); + } + + if (spd_size > 90) { + dimm->part_number[16] = 0; + memcpy(dimm->part_number, &spd[73], 16); + printram(" Part number : %s\n", dimm->part_number); + } + + return ret; +} + +/* + * The information printed below has a more informational character, and is not + * necessarily tied in to RAM init debugging. Hence, we stop using printram(), + * and use the standard printk()'s below. + */ + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); +} + +static void print_us(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); +} + +/** +* \brief Print the info in DIMM +* +* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected, or for a purely informative output. +* +* @param dimm pointer to already decoded @ref dimm_attr structure +*/ +void dram_print_spd_ddr2(const dimm_attr *dimm) +{ + u8 val8, cl; + char buf[32]; + int i; + + printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); + printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Width : x%u\n", dimm->width); + printk(BIOS_INFO, " Banks : %u\n", dimm->banks); + + /* CAS Latencies Supported */ + val8 = dimm->cas_supported; + printk(BIOS_INFO, " CAS latencies :"); + i = 0; + cl = 0; + do { + if (val8 & 1) { + printk(BIOS_INFO, " %u", i); + cl = i; + } + i++; + val8 >>= 1; + } while (val8); + printk(BIOS_INFO, "\n"); + + for (i = cl - 2; i <= cl; i++) { + if (i < 0) + continue; + snprintf(buf, sizeof(buf), " tCK at CL%u : ", i); + print_ns(buf, dimm->cycle_time[i]); + snprintf(buf, sizeof(buf), " tAC at CL%u : ", i); + print_ns(buf, dimm->access_time[i]); + } + print_ns(" tCKmax : ", dimm->tCK); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tDS : ", dimm->tDS); + print_ns(" tDH : ", dimm->tDH); + print_ns(" tDQSQmax : ", dimm->tDQSQ); + print_ns(" tQHSmax : ", dimm->tQHS); + print_us(" tPLL : ", dimm->tPLL); + print_us(" tRR : ", dimm->tRR); +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h new file mode 100644 index 0000000..026be4b --- /dev/null +++ b/src/include/device/dram/ddr2.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) + */ + +#ifndef DEVICE_DRAM_DDR2L_H +#define DEVICE_DRAM_DDR2L_H + +/** + * @file ddr2.h + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR2 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_800MHZ 320 +#define TCK_700MHZ 365 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/* + * Module type (byte 20, bits 5:0) of SPD + * This definition is specific to DDR2. DDR3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DIMM_TYPE_RDIMM = 0x01, + SPD_DIMM_TYPE_UDIMM = 0x02, + SPD_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, + SPD_DIMM_TYPE_MICRO_DIMM = 0x08, + SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_UDIMM = 0x20, + /* Masks to bits 5:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0x3f, +}; + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +typedef union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Module can work at 5.00V */ + unsigned operable_5_00V:1; + /* Module can work at 3.33V */ + unsigned operable_3_33V:1; + /* Module can work at 2.50V */ + unsigned operable_2_50V:1; + /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ + unsigned operable_1_80V:1; + /* Module can work at 1.50V */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_25V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* Supports weak driver */ + unsigned weak_driver:1; + /* Supports terminating at 50 Ohm */ + unsigned terminate_50ohms:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* Supports burst length 8 */ + unsigned bl8:1; + /* Supports burst length 4 */ + unsigned bl4:1; + }; + unsigned int raw; +} dimm_flags_t; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + u8 cas_supported; + + /* Maximum cloclk to data cycle times for various CAS */ + u32 cycle_time[8]; + /* Maximum data access times for various CAS */ + u32 access_time[8]; + /* Flags extracted from SPD */ + dimm_flags_t flags; + /* Number of banks */ + u8 banks; + /* SDRAM width */ + u8 width; + /* Module width */ + u8 mod_width; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Size of module in MiB */ + u32 size_mb; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tIS; + u32 tIH; + u32 tDS; + u32 tDH; + + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tDQSQ; + u32 tQHS; + + /* Latencies are in units of 1/256 us */ + u32 tPLL; + u32 tRR; + + /* Manufacturer ID */ + u32 manufacturer_id; // + /* ASCII part number - NULL terminated */ + u8 part_number[17]; +} dimm_attr; + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +typedef u8 spd_raw_data[128]; + +int dimm_is_registered(enum spd_dimm_type type); +u8 spd_ddr2_calc_checksum(u8 *spd, int len); +u32 spd_decode_spd_size_ddr2(u8 byte0); +u32 spd_decode_eeprom_size_ddr2(u8 byte1); +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); +void dram_print_spd_ddr2(const dimm_attr *dimm); + + +#endif /* DEVICE_DRAM_DDR2L_H */

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Patch set updated for coreboot: mainboard/google/reef: Tune i2c frequency to under 400 Khz
by Tim Chen 03 Feb '17

03 Feb '17

Tim Chen (Tim-Chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18284 -gerrit commit 49bbe8a1768298edc9ae3d048497516ce51d98bd Author: Tim Chen <Tim-Chen(a)quantatw.com> Date: Fri Feb 3 16:57:39 2017 +0800 mainboard/google/reef: Tune i2c frequency to under 400 Khz tune i2c devices clk for reef: I2C0: audio I2C2: TPM H1 I2C4: elan touchpad BUG=chrome-os-partner:62593 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.1kHz TPM H1: Freq. 369.5kHz elan touchpad: Freq. 397.0kHz Change-Id: If27b7a1333d5f1e14c850a0dfb3c6eb90f0072fc Signed-off-by: Tim Chen <Tim-Chen(a)quantatw.com> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2ccf277..e40bfee 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -76,16 +76,16 @@ chip soc/intel/apollolake # Enable I2C0 for audio codec at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, + .rise_time_ns = 44, + .fall_time_ns = 22, }" # Enable I2C2 bus early for TPM at 400kHz register "i2c[2]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, + .rise_time_ns = 30, + .fall_time_ns = 15, }" # touchscreen at 400kHz @@ -98,8 +98,8 @@ chip soc/intel/apollolake # trackpad at 400kHz register "i2c[4]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, + .rise_time_ns = 57, + .fall_time_ns = 82, }" # digitizer at 400kHz

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Patch set updated for coreboot: google/poppy: Set GPIO GPP_D22 high
by Rizwan Qureshi 03 Feb '17

03 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18282 -gerrit commit 87d9f7911ee8c7021d60982b8d8e5deee4bd3e1b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 2 12:23:37 2017 +0530 google/poppy: Set GPIO GPP_D22 high same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74 this is required for poppy board as well. GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=None BRANCH=None TEST=play test sound in OS over internal speaker Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index 0a2544c..b3849f1 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -144,7 +144,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,

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Patch set updated for coreboot: util/ifdtool: Fix ICH Gbe unlock
by Patrick Rudolph 03 Feb '17

03 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18055 -gerrit commit 2a52aed83a64c71635efde0189cc92ecfee15c21 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 8 09:57:47 2017 +0100 util/ifdtool: Fix ICH Gbe unlock With coreboot 4.4 switched to "Descriptor mode" for Lenovo T500 it automatically unlocks all flash regions. For Gbe region the "Requester ID" was hardcoded resulting in *dead* Gbe. Unlock the Gbe region and keep board specific "Requester ID". Allows Lenovo T500 to boot in "Descriptor mode" with unlocked flash regions. Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: Ia4b5d1928e84bee42182fc83020e3a13fadc93c4 --- util/ifdtool/ifdtool.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 45dd97c..73f8942 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -876,7 +876,8 @@ static void unlock_descriptor(char *filename, char *image, int size) } else { fmba->flmstr1 = 0xffff0000; fmba->flmstr2 = 0xffff0000; - fmba->flmstr3 = 0x08080118; + /* Keep chipset specific Requester ID */ + fmba->flmstr3 = 0x08080000 | (fmba->flmstr3 & 0xffff); } write_image(filename, image, size);

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Patch set updated for coreboot: vendorcode/intel: Update CpuConfigFspData.h file
by Barnali Sarkar 03 Feb '17

03 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18285 -gerrit commit eca30e1a65be7816467537fa65989c607a65fafa Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Feb 3 13:28:46 2017 +0530 vendorcode/intel: Update CpuConfigFspData.h file The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=chrome-os-partner:61548 BRANCH=none TEST=Build and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index 8fd41e0..c8cdc5f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -62,9 +62,9 @@ typedef union { UINT32 TxtEnable : 1; UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use - EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + UINT32 Reserved; } Bits; - UINT32 Uint32[3]; + UINT32 Uint32[2]; } CPU_CONFIG_FSP_DATA; #pragma pack (pop)

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New patch to review for coreboot: vendorcode/intel: Update CpuConfigFspData.h file
by Barnali Sarkar 03 Feb '17

03 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18285 -gerrit commit 3317fd7e9ffecb3c6db4570338fe9af8ef8a40ec Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Feb 3 13:28:46 2017 +0530 vendorcode/intel: Update CpuConfigFspData.h file The FSP UPD offsets and the corresponding structure size do not match, CpuConfigData.h needs an update to align the same. Hence update the header file based on FSP version 1.4.0. BUG=none BRANCH=none TEST=Build and booted KBLRVP and verify that all UPDs are in sync in both coreboot and FSP. Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index 8fd41e0..c8cdc5f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -62,9 +62,9 @@ typedef union { UINT32 TxtEnable : 1; UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use - EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + UINT32 Reserved; } Bits; - UINT32 Uint32[3]; + UINT32 Uint32[2]; } CPU_CONFIG_FSP_DATA; #pragma pack (pop)

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coreboot-gerrit February 2017