New patch to review for coreboot: vendorcode/intel/skykabylake: Update FSP UPD header files
Aamir Bohra (aamir.bohra@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18289
-gerrit
commit 74c775a50c554693ac0d2a9c5cd345f26bafb875 Author: Aamir Bohra aamir.bohra@intel.com Date: Thu Feb 2 22:05:02 2017 +0530
vendorcode/intel/skykabylake: Update FSP UPD header files
Update FSP UPD header files as per version 1.6.0
BUG=None BRANCH=None TEST=Verify build and boot RVP3 and poppy
Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- .../intel/fsp/fsp2_0/skykabylake/FspUpd.h | 2 +- .../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 5 ++- .../intel/fsp/fsp2_0/skykabylake/FspsUpd.h | 49 ++++++++++++++++------ 3 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h index 4981f21..bea3509 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h index 3e65f0a..89dc419 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -773,7 +773,8 @@ typedef struct { UINT8 HyperThreading;
/** Offset 0x02D4 - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. + Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. @note If disabled, + BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting. $EN_DIS **/ UINT8 CpuRatioOverride; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h index 0120cf8..f2cc9b4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -363,9 +363,16 @@ typedef struct { **/ UINT8 PchLanEnable;
-/** Offset 0x00FC +/** Offset 0x00FC - Delay USB PDO Programming + Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: + disable, 1: enable + $EN_DIS +**/ + UINT8 DelayUsbPdoProgramming; + +/** Offset 0x00FD **/ - UINT8 UnusedUpdSpace3[24]; + UINT8 UnusedUpdSpace3[23];
/** Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for @@ -739,7 +746,7 @@ typedef struct { UINT8 SendVrMbxCmd1;
/** Offset 0x02E4 - CpuS3ResumeMtrrData - Pointer CPU S3 Resume MTRR Data + Pointer to CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData;
@@ -2041,9 +2048,15 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x0779 +/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid + The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. + $EN_DIS +**/ + UINT8 MeUnconfigIsValid; + +/** Offset 0x077A **/ - UINT8 ReservedFspsUpd[7]; + UINT8 ReservedFspsUpd[6]; } FSP_S_CONFIG;
/** Fsp S Test Configuration @@ -2517,14 +2530,16 @@ typedef struct { **/ UINT8 C1e;
-/** Offset 0x07DA - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b> +/** Offset 0x07DA - Enable or Disable Package C-State Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b> + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateDemotion;
-/** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b> +/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion + Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b> + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateUnDemotion; @@ -2772,11 +2787,21 @@ typedef struct { **/ UINT16 PsysPmax;
-/** Offset 0x087E - ReservedCpuPostMemTest +/** Offset 0x087E - CpuS3ResumeDataSize + Size of CPU S3 Resume Data +**/ + UINT16 CpuS3ResumeDataSize; + +/** Offset 0x0880 - CpuS3ResumeData + Pointer to CPU S3 Resume Data +**/ + UINT32 CpuS3ResumeData; + +/** Offset 0x0884 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[12]; + UINT8 ReservedCpuPostMemTest[6];
/** Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values
-
Aamir Bohra