coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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1019 discussions

Patch set updated for coreboot: google/eve: Fix DRAM DQS map
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18279 -gerrit commit 2f7a5eedd99ac33ba6d1640c44d27a4e9f119e9b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Feb 1 16:37:29 2017 -0800 google/eve: Fix DRAM DQS map This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- 3rdparty/blobs | 2 +- src/mainboard/google/eve/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8090bdd..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 4ae87fd..2378e90 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 1, 0, 2, 3, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 3, 2, 7, 6 } }; + { 1, 0, 5, 4, 2, 3, 7, 6 } }; /* Rcomp resistor */ const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */

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Patch set updated for coreboot: google/eve: Set GPIO GPP_D22 high
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18281 -gerrit commit 342146d11e2066bffc282c3fdd61adcca72a7209 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:09:02 2017 -0800 google/eve: Set GPIO GPP_D22 high GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=chrome-os-partner:58666 TEST=play test sound in OS over internal speaker Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index e8d42f0..f5b09d9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -142,7 +142,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */

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Patch set updated for coreboot: google/eve: Fix keyboard backlight enable in wake from G3
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18280 -gerrit commit 5c2011a504a12811f4b33ccbd47937530d5b8e4c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:10:10 2017 -0800 google/eve: Fix keyboard backlight enable in wake from G3 The WAK_STS bit is not set in a wake from G3, so the check for this bit needs to only be done when checking for a wake from S3. This change correctly enables the keyboard backlight in wake from G3 and only does not enable it during a wake from S3. BUG=chrome-os-partner:58666 TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard backlight turns on like it does when waking from S5. Also force enter hibernate with Alt+VolumeUp+H and then power back up and ensure that the keyboard backlight is enabled when booting. Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index baca9c8..872825f 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -34,7 +34,7 @@ void bootblock_mainboard_init(void) uint32_t pm1_sts = inl(ACPI_BASE_ADDRESS + PM1_STS); /* Turn on keyboard backlight to indicate we are booting */ - if ((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) != ACPI_S3)) + if (!((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) == ACPI_S3))) google_chromeec_kbbacklight(75); early_config_gpio();

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Patch set updated for coreboot: google/eve: Fix DRAM DQS map
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18279 -gerrit commit 4526988089742e09c673c8d722b1e3003d790550 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Feb 1 16:37:29 2017 -0800 google/eve: Fix DRAM DQS map This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- 3rdparty/blobs | 2 +- src/mainboard/google/eve/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8090bdd..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 4ae87fd..2378e90 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 1, 0, 2, 3, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 3, 2, 7, 6 } }; + { 1, 0, 5, 4, 2, 3, 7, 6 } }; /* Rcomp resistor */ const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */

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New patch to review for coreboot: google/eve: Set GPIO GPP_D22 high
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18281 -gerrit commit 555627a8fcc22ff5bec8b16aa45307419ebb4d41 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:09:02 2017 -0800 google/eve: Set GPIO GPP_D22 high GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=chrome-os-partner:58666 TEST=play test sound in OS over internal speaker Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index e8d42f0..f5b09d9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -142,7 +142,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */

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New patch to review for coreboot: google/eve: Fix keyboard backlight enable in wake from G3
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18280 -gerrit commit f7d3d757f8fb40981a0e95040c9ed94c650fe173 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:10:10 2017 -0800 google/eve: Fix keyboard backlight enable in wake from G3 The WAK_STS bit is not set in a wake from G3, so the check for this bit needs to only be done when checking for a wake from S3. This change correctly enables the keyboard backlight in wake from G3 and only does not enable it during a wake from S3. BUG=chrome-os-partner:58666 TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard backlight turns on like it does when waking from S5. Also force enter hibernate with Alt+VolumeUp+H and then power back up and ensure that the keyboard backlight is enabled when booting. Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index baca9c8..872825f 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -34,7 +34,7 @@ void bootblock_mainboard_init(void) uint32_t pm1_sts = inl(ACPI_BASE_ADDRESS + PM1_STS); /* Turn on keyboard backlight to indicate we are booting */ - if ((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) != ACPI_S3)) + if (!((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) == ACPI_S3))) google_chromeec_kbbacklight(75); early_config_gpio();

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New patch to review for coreboot: google/eve: Fix DRAM DQS map
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18279 -gerrit commit 777a534e867995d8f81f8df38bfd5d616a37bb35 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Feb 1 16:37:29 2017 -0800 google/eve: Fix DRAM DQS map This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- 3rdparty/blobs | 2 +- src/mainboard/google/eve/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8090bdd..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 4ae87fd..2378e90 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 1, 0, 2, 3, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 3, 2, 7, 6 } }; + { 1, 0, 5, 4, 2, 3, 7, 6 } }; /* Rcomp resistor */ const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */

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Patch set updated for coreboot: ectool: Support OpenBSD
by Steven Dee 02 Feb '17

02 Feb '17

Steven Dee (i(a)wholezero.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18260 -gerrit commit 85150875b4080a0b387aad7b84ae8763cfb93106 Author: Steven Dee <i(a)wholezero.org> Date: Sun Jan 29 14:52:56 2017 -0500 ectool: Support OpenBSD Adds checks for OpenBSD in all the places that were already checking for NetBSD. This fixes e.g.: ec.c:21:20: error: sys/io.h: No such file or directory which was caused by defaulting to Linux. Also, OpenBSD calls its amd64 iopl amd64_iopl instead of x86_64_iopl. This change just defines iopl appropriately depending on the OS and architecture. TEST=Build on OpenBSD 6.0 or -current from 2017-01-25. Change-Id: If6d92a9850c15cd9f8e287cc4f963d3ff881f72c Signed-off-by: Steven Dee <i(a)wholezero.org> --- util/ectool/Makefile | 2 +- util/ectool/ec.c | 4 ++-- util/ectool/ectool.c | 22 ++++++++++++---------- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/util/ectool/Makefile b/util/ectool/Makefile index 8aa1415..234e931 100644 --- a/util/ectool/Makefile +++ b/util/ectool/Makefile @@ -25,7 +25,7 @@ ifeq ($(shell uname -o 2>/dev/null), Cygwin) LDFLAGS = -lioperm endif -ifeq ($(OS_ARCH), NetBSD) +ifeq ($(OS_ARCH), $(filter $(OS_ARCH), NetBSD OpenBSD)) LDFLAGS = -l$(shell uname -p) endif diff --git a/util/ectool/ec.c b/util/ectool/ec.c index 098e812..08b6b1b 100644 --- a/util/ectool/ec.c +++ b/util/ectool/ec.c @@ -17,12 +17,12 @@ #include <stdint.h> #include <stdlib.h> #include <unistd.h> -#ifndef __NetBSD__ +#if !(defined __NetBSD__ || defined __OpenBSD__) #include <sys/io.h> #endif #include "ec.h" -#ifdef __NetBSD__ +#if defined __NetBSD__ || defined __OpenBSD__ #include <machine/sysarch.h> static uint8_t inb(unsigned port) { diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index 50ac30b..6d9668d 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -18,14 +18,24 @@ #include <stdlib.h> #include <unistd.h> #include <getopt.h> -#ifndef __NetBSD__ +#if !(defined __NetBSD__ || defined __OpenBSD__) #include <sys/io.h> #endif #include <ec.h> #include <stdlib.h> -#ifdef __NetBSD__ +#if defined __NetBSD__ || defined __OpenBSD__ + #include <machine/sysarch.h> + +# if defined __i386__ +# define iopl i386_iopl +# elif defined __NetBSD__ +# define iopl x86_64_iopl +# else +# define iopl amd64_iopl +# endif + #endif @@ -113,15 +123,7 @@ int main(int argc, char *argv[]) } } -#ifdef __NetBSD__ -# ifdef __i386__ - if (i386_iopl(3)) { -# else - if (x86_64_iopl(3)) { -# endif -#else if (iopl(3)) { -#endif printf("You need to be root.\n"); exit(1); }

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New patch to review for coreboot: NOT FOR MERGE: test ddr2 spd decode
by Arthur Heymans 01 Feb '17

01 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18278 -gerrit commit e359ef9c71f59334ce3fea81975c9c7088da4ccd Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 1 23:02:17 2017 +0100 NOT FOR MERGE: test ddr2 spd decode Change-Id: I3494009eec88eb31efd031a6da27fd1108131beb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/Kconfig | 4 ++++ src/device/dram/Makefile.inc | 1 + src/device/dram/ddr2.c | 4 ++-- src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/raminit.c | 10 +++++++++- 5 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..baa72c0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -214,6 +214,10 @@ config SPD_CACHE bool default n +config DDR2_SPD + bool + default n + config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..dbe4412 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-$(CONFIG_DDR2_SPD) += ddr2.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index e8791c7..7c9b2ed 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -205,7 +205,7 @@ static u32 spd_decode_tRR_time(u8 c) * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th us. */ -static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 tRFC) +static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC) { u8 b40, b41, b42; @@ -385,7 +385,7 @@ int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd) } printram(" Supported CAS : 0x%x\n", dimm->cas_supported); - cl = spd_get_msbs(dimm->cas_supported); + cl = spd_get_msbs(dimm->cas_supported) - 2; dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index efe192b..65be5a1 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE + select DDR2_SPD config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..c84f90f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,7 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; + int i, j; /** * i945 supports two DIMMs, in two configurations: @@ -360,6 +361,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) for (i = 0; i<(2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); u8 reg8; + spd_raw_data raw_spd; + dimm_attr *dimm = NULL; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -375,6 +378,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) continue; } + for (j = 0; j < 128; j++) + raw_spd[j] = spd_read_byte(device, j); + spd_decode_ddr2(dimm, raw_spd); + dram_print_spd_ddr2(dimm); + reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); if (reg8 == ERROR_SCHEME_ECC) die("Error: ECC memory not supported by this chipset\n");

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Patch set updated for coreboot: [WIP] nb/i945/gma.c: Refactor panel setup
by Arthur Heymans 01 Feb '17

01 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit ef41ffc44f9a968a9e94b0b27cb0167005c8427f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 [WIP] nb/i945/gma.c: Refactor panel setup This reuses gm45 code to set up panel. Panel start and stop delays and pwm frequency can now be set in devicetree. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. TESTED on Lenovo Thinkpad X60 Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/i915_reg.h | 2 +- src/mainboard/apple/macbook21/devicetree.cb | 7 +- src/mainboard/lenovo/t60/devicetree.cb | 7 +- src/mainboard/lenovo/x60/devicetree.cb | 7 +- src/northbridge/intel/i945/chip.h | 7 +- src/northbridge/intel/i945/gma.c | 104 +++++++++++++++++++++++++--- 6 files changed, 118 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..dee6865 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -62,7 +62,7 @@ #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..b6e61eb 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..6ad054c 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "275" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..28b63d3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..5bbda81 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,13 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..8b73d7b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -46,6 +46,19 @@ #define PGETBL_ENABLED 0x00000001 #define BASE_FREQUENCY 100000 +#define DEFAULT_PWM 1000 + +static struct resource *gtt_res = NULL; + +u32 gtt_read(u32 reg) +{ + return read32(res2mmio(gtt_res, reg, 0)); +} + +void gtt_write(u32 reg, u32 data) +{ + write32(res2mmio(gtt_res, reg, 0), data); +} static int gtt_setup(void *mmiobase) { @@ -292,17 +305,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(pmmio + DSPPOS(0), 0); - /* Backlight init. */ - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC, 0x011d011a); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC_SELF, 0x0001003f); - write32(pmmio + FW_BLC, 0x011d0109); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(pmmio + DSPADDR(0), 0); write32(pmmio + DSPSURF(0), 0); @@ -579,6 +581,80 @@ static int probe_edid(u8 *pmmio, u8 slave) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + u16 gcfgc = pci_read_config16(dev, GCFGC); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) + return 133333333; + else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_320_MHZ: + return 320000000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 200000000; + } + } +} + +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + /* Set duty cycle to 100% due to use of legacy backlight control */ + blc_mod = get_cdclk(dev) / (128 * pwm_freq); + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(PP_ON_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(PP_ON_DELAYS, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(PP_OFF_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(PP_OFF_DELAYS, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = (get_cdclk(dev) / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + gtt_write(PP_DIVISOR, reg32); + } + + /* Backlight init. */ + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC, 0x011d011a); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC_SELF, 0x0001003f); + gtt_write(FW_BLC, 0x011d0109); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + if (conf->pwm_freq == 0) { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, DEFAULT_PWM)); + } else { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); + } +} static void gma_func0_init(struct device *dev) { @@ -596,6 +672,8 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); @@ -623,6 +701,10 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + panel_setup(dev); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

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coreboot-gerrit February 2017