coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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1019 discussions

New patch to review for coreboot: mainboard/google/reef: Tune i2c frequency to under 400 Khz
by Tim Chen 03 Feb '17

03 Feb '17

Tim Chen (Tim-Chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18284 -gerrit commit 8fca0ab3999413daeadb990aca4cb5fcad41b366 Author: Tim Chen <Tim-Chen(a)quantatw.com> Date: Fri Feb 3 16:57:39 2017 +0800 mainboard/google/reef: Tune i2c frequency to under 400 Khz tune i2c devices clk for reef: I2C0: audio I2C2: TPM H1 I2C4: elan touchpad BUG=chrome-os-partner:62593 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.1kHz TPM H1: Freq. 369.5kHz elan touchpad: Freq. 397.0kHz Change-Id: If27b7a1333d5f1e14c850a0dfb3c6eb90f0072fc --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2ccf277..e40bfee 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -76,16 +76,16 @@ chip soc/intel/apollolake # Enable I2C0 for audio codec at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, + .rise_time_ns = 44, + .fall_time_ns = 22, }" # Enable I2C2 bus early for TPM at 400kHz register "i2c[2]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, + .rise_time_ns = 30, + .fall_time_ns = 15, }" # touchscreen at 400kHz @@ -98,8 +98,8 @@ chip soc/intel/apollolake # trackpad at 400kHz register "i2c[4]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, + .rise_time_ns = 57, + .fall_time_ns = 82, }" # digitizer at 400kHz

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New patch to review for coreboot: mainboard/google/snappy: Set PL2 override to 15000mW
by Harry Pan 03 Feb '17

03 Feb '17

Harry Pan (harry.pan(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18283 -gerrit commit dfe7358bcfced64520c63857fde25e557cfa1e2e Author: Harry Pan <harry.pan(a)intel.com> Date: Thu Feb 2 15:42:25 2017 +0800 mainboard/google/snappy: Set PL2 override to 15000mW This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:62110 BRANCH=reef TEST=Apply new firmware to evaluate Octane benchmark score. Change-Id: I51734051586753677129314b5273fb275c74f5d2 Signed-off-by: Harry Pan <harry.pan(a)intel.com> --- src/mainboard/google/reef/variants/snappy/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 6d7c8ca..c83306d 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -53,6 +53,8 @@ chip soc/intel/apollolake # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1"

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Patch set updated for coreboot: util/docker: Update dockerfiles & build method
by Martin Roth 03 Feb '17

03 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18001 -gerrit commit c83ccbcb92ab0358726a846e05a2fca325c3a576 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Dec 30 17:00:19 2016 -0700 util/docker: Update dockerfiles & build method All files: - Previously, various things were hardcoded into the docker containers that made it necessary to update the Dockerfile files for each new version of the sdk. Turn those into 'Variables" that are updated during the build step. Because the makefile is piping the dockerfile through the sed command and back into the docker build command, the normal docker "COPY" keyword doesn't work. coreboot-jenkins-node changes: - Run ssh-keygen -A to explicitly generate the ssh keys. This fixes an error: Could not load host key: /etc/ssh/ssh_host_dsa_key coreboot-sdk changes: - Remove apt-get upgrade command - The Dockerfile guide recommends not to run this. - Change libssl-dev to libssl1.0-dev. libssl-dev's header files won't build the Chrome-EC codebase. - Add libisl-dev, needed to build the riscv toolchain. - Build the toolchain using the -b option - Add environment variables containing the version and commit that the coreboot-sdk was built from. Makefile: - Update targets to use the version and commit variables Change-Id: I2c1376fe4b791da2a62fca11bc92c4774cbef1c8 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/docker/Makefile | 31 +++++++++++++++++++++------- util/docker/coreboot-jenkins-node/Dockerfile | 30 +++++++++++++++++++++------ util/docker/coreboot-sdk/Dockerfile | 27 ++++++++++++++++++------ 3 files changed, 69 insertions(+), 19 deletions(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index f669b93..7df6851 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -14,7 +14,13 @@ ## export top=$(abspath $(CURDIR)/../..) export crossgcc_version=$(shell $(top)/util/crossgcc/buildgcc --version | grep 'cross toolchain' | sed 's/^.*\sv//' | sed 's/\s.*$$//') -export DOCKER:=$(shell env sh -c "command -v docker") +export DOCKER:=$(shell $(SHELL) -c "command -v docker") + +# Version of the jenkins / sdk container +export COREBOOT_CONTAINER_VERSION?=$(crossgcc_version) + +# Commit id to build from +export DOCKER_COMMIT?=$(shell git log -n 1 --pretty=%h) test-docker: $(if $(DOCKER),,\ @@ -28,16 +34,23 @@ test-docker-login: test-docker $(error Docker authentication file not found. Run 'docker login')) coreboot-sdk: test-docker - $(DOCKER) build -t coreboot/coreboot-sdk:$(crossgcc_version) coreboot-sdk + @echo "Building coreboot SDK $(crossgcc_version) from commit $(DOCKER_COMMIT)" + cat coreboot-sdk/Dockerfile | \ + sed "s/{{DOCKER_COMMIT}}/$(DOCKER_COMMIT)/" | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_CONTAINER_VERSION)/" | \ + $(DOCKER) build -t coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) - upload-coreboot-sdk: test-docker-login - $(DOCKER) push coreboot/coreboot-sdk:$(crossgcc_version) + $(DOCKER) push coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) coreboot-jenkins-node: test-docker - $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(crossgcc_version) coreboot-jenkins-node + cat coreboot-jenkins-node/Dockerfile | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_CONTAINER_VERSION)/" | \ + sed "s|{{SSH_KEY}}|$$(cat coreboot-jenkins-node/authorized_keys)|" | \ + $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(COREBOOT_CONTAINER_VERSION) - upload-coreboot-jenkins-node: test-docker-login - $(DOCKER) push coreboot/coreboot-jenkins-node:$(crossgcc_version) + $(DOCKER) push coreboot/coreboot-jenkins-node:$(COREBOOT_CONTAINER_VERSION) docker-killall: test-docker @if [ -n "$$($(DOCKER) ps | grep 'coreboot')" ]; then \ @@ -52,7 +65,7 @@ clean-coreboot-images: docker-killall docker-build-coreboot: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ - --rm coreboot/coreboot-sdk:$(crossgcc_version) \ + --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ /bin/bash -c "cd /home/coreboot/coreboot && \ make clean && \ make $(BUILD_CMD)" @@ -62,7 +75,7 @@ docker-build-coreboot: test-docker docker-abuild: test-docker $(DOCKER) run -u root -it -v $(top):/home/coreboot/coreboot \ - --rm coreboot/coreboot-sdk:$(crossgcc_version) \ + --rm coreboot/coreboot-sdk:$(COREBOOT_CONTAINER_VERSION) \ /bin/bash -c "cd /home/coreboot/coreboot && \ make clean && \ util/abuild/abuild $(ABUILD_ARGS)" @@ -82,6 +95,10 @@ help: @echo "Commands for using docker images" @echo " docker-build-coreboot <BUILD_CMD=target> - Build coreboot under coreboot-sdk" @echo " docker-abuild <ABUILD_ARGS='-a -B'> - Run abuild under coreboot-sdk" + @echo + @echo "Variables:" + @echo " COREBOOT_CONTAINER_VERSION = $(COREBOOT_CONTAINER_VERSION)" + @echo " DOCKER_COMMIT = $(DOCKER_COMMIT)" .PHONY: test-docker test-docker-login .PHONY: coreboot-jenkins-node upload-coreboot-jenkins-node diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index b60466d..230842c 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -1,5 +1,20 @@ -FROM coreboot/coreboot-sdk:1.42 -MAINTAINER Martin Roth <gaumless(a)gmail.com> +# This dockerfile is not meant to be used directly by docker. The +# {{}} varibles are replaced with values by the makefile. Please generate +# the docker image for this file by running: +# +# make coreboot-jenkins-node +# +# Variables can be updated on the make command line or left blank to use +# the default values set by the makefile. +# +# SDK_VERSION is used to name the version of the coreboot sdk to use. +# Typically, this corresponds to the toolchain version. +# SSH_KEY is the contents of the file coreboot-jenkins-node/authorized_keys +# Because we're piping the contents of the dockerfile into the +# docker build command, the 'COPY' keyword isn't valid. + +FROM coreboot/coreboot-sdk:{{SDK_VERSION}} +MAINTAINER Martin Roth <martin(a)coreboot.org> USER root # Check to make sure /dev is a tmpfs file system @@ -10,13 +25,17 @@ RUN apt-get -y update && \ lua5.3 liblua5.3-dev openjdk-8-jre-headless openssh-server && \ apt-get clean -COPY authorized_keys /home/coreboot/.ssh/authorized_keys -RUN chown -R coreboot /home/coreboot/.ssh && \ +# Because of the way that the variables are being replaced, docker's 'COPY' +# command does not work +RUN mkdir -p /home/coreboot/.ssh && \ + echo "{{SSH_KEY}}" > /home/coreboot/.ssh/authorized_keys && \ + chown -R coreboot:coreboot /home/coreboot/.ssh && \ chmod 0700 /home/coreboot/.ssh && \ chmod 0600 /home/coreboot/.ssh/authorized_keys RUN mkdir /var/run/sshd && \ - chmod 0755 /var/run/sshd + chmod 0755 /var/run/sshd && \ + /usr/bin/ssh-keygen -A # Build encapsulate tool ADD https://raw.githubusercontent.com/pgeorgi/encapsulate/master/encapsulate.c /tmp/encapsulate.c @@ -24,7 +43,6 @@ RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \ chown root /usr/sbin/encapsulate && \ chmod +s /usr/sbin/encapsulate - VOLUME /data/cache ENTRYPOINT mkdir /dev/cb-build && chown coreboot /dev/cb-build && /usr/sbin/sshd -p 49151 -D EXPOSE 49151 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index cb0023c..feaf843 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -1,26 +1,39 @@ +# This dockerfile is not meant to be used directly by docker. The +# {{}} varibles are replaced with values by the makefile. Please generate +# the docker image for this file by running: +# +# make coreboot-sdk +# +# Variables can be updated on the make command line or left blank to use +# the default values set by the makefile. +# +# SDK_VERSION is used to name the version of the coreboot sdk to use. +# Typically, this corresponds to the toolchain version. This +# is used to identify this docker image. +# DOCKER_COMMIT is the coreboot Commit-ID to build the toolchain from. + FROM debian:sid -MAINTAINER Martin Roth <gaumless(a)gmail.com> +MAINTAINER Martin Roth <martin(a)coreboot.org> RUN \ useradd -p locked -m coreboot && \ apt-get -qq update && \ - apt-get -qq upgrade && \ apt-get -qqy install gcc g++ make patch python diffutils bison flex \ git doxygen ccache subversion p7zip-full unrar-free \ m4 wget curl bzip2 vim-common cmake xz-utils pkg-config \ dh-autoreconf unifont \ - libssl-dev libgmp-dev zlib1g-dev libpci-dev liblzma-dev \ + libssl1.0-dev libgmp-dev zlib1g-dev libpci-dev liblzma-dev \ libyaml-dev libncurses5-dev uuid-dev libusb-dev libftdi-dev \ libusb-1.0-0-dev libreadline-dev libglib2.0-dev libgmp-dev \ - libelf-dev libxml2-dev libfreetype6-dev && \ + libelf-dev libxml2-dev libfreetype6-dev libisl-dev && \ apt-get clean RUN \ cd /root && \ git clone http://review.coreboot.org/coreboot && \ cd coreboot/util/crossgcc && \ - git checkout 589ef9de8fa && \ - make all_without_gdb CPUS=$(nproc) DEST=/opt/xgcc && \ + git checkout {{DOCKER_COMMIT}} && \ + make all_without_gdb CPUS=$(nproc) DEST=/opt/xgcc BUILDGCC_OPTIONS=-b && \ cd /root && \ rm -rf coreboot @@ -31,4 +44,6 @@ RUN mkdir /home/coreboot/.ccache && \ VOLUME /home/coreboot/.ccache ENV PATH $PATH:/opt/xgcc/bin +ENV SDK_VERSION={{SDK_VERSION}} +ENV SDK_COMMIT={{DOCKER_COMMIT}} USER coreboot

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Patch merged into coreboot/master: mb/lenovo/x60, t60: Move EC CMOS parameters in checksummed space
by gerrit＠coreboot.org 03 Feb '17

03 Feb '17

the following patch was just integrated into master: commit 84e6881ba5bdba7dc54c82b8f372079191ba4cd8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Oct 16 23:09:16 2016 +0200 mb/lenovo/x60,t60: Move EC CMOS parameters in checksummed space This allows for defaults to be applied to CMOS parameters when cmos checksum is incorrect. This probably results in changed cmos settings for current users of these targets. Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17041 for details. -gerrit

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Patch merged into coreboot/master: asus/f2a85-m_le: Activate IOMMU support
by gerrit＠coreboot.org 03 Feb '17

03 Feb '17

the following patch was just integrated into master: commit 31db6f5e179d6e0162c010583a31e1f3addf03b7 Author: Tobias Diedrich <ranma+openocd(a)tdiedrich.de> Date: Sun Jan 29 18:03:09 2017 +0100 asus/f2a85-m_le: Activate IOMMU support Activate the IOMMU for the ASUS F2A85-M LE board. Enable the IOMMU in `devicetree.cb` and build AGESA IOMMU code by enabling the option in `buildOpts.c`. ACPI and MPTABLES interrupt routers are already present since they are syminks to the F2A85-M version. ``` $ uname -a Linux nukunuku 4.8.5 #35 SMP Sun Oct 30 19:34:55 CET 2016 x86_64 GNU/Linux $ lspci -s 0.2 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg | grep -i IOMMU ACPI: IVRS 0x00000000BFFAFF70 000070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) AMD-Vi: Applying erratum 746 workaround for IOMMU at 0000:00:00.2 iommu: Adding device 0000:00:01.0 to group 0 [...] iommu: Adding device 0000:00:18.5 to group 9 iommu: Adding device 0000:03:00.0 to group 8 AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40 AMD IOMMUv2 driver by Joerg Roedel <jroedel(a)suse.de> ``` Change-Id: I6049fcfad53d16a99495d7a8fbc584c71e371d73 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Reviewed-on: https://review.coreboot.org/18259 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18259 for details. -gerrit

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Patch set updated for coreboot: device/dram/ddr2: Add common ddr2 spd decoder
by Patrick Rudolph 02 Feb '17

02 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18273 -gerrit commit 8cf1ac241194d94a2ef4bb0db175be3191a86cc1 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 31 19:43:17 2017 +0100 device/dram/ddr2: Add common ddr2 spd decoder Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr2.c | 568 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 201 +++++++++++++++ 2 files changed, 769 insertions(+) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c new file mode 100644 index 0000000..4871fa0 --- /dev/null +++ b/src/device/dram/ddr2.c @@ -0,0 +1,568 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file ddr2.c + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr2.h> +#include <string.h> + +/*============================================================================== + * = DDR2 SPD decoding helpers + *----------------------------------------------------------------------------*/ + +/** + * \brief Checks if the DIMM is Registered based on byte[20] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[20] of the SPD. + */ +int dimm_is_registered(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Calculate the checksum of a DDR2 SPD unique identifier + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the checksum of SPD data bytes 63, or 0 when spd data is truncated. + */ +u8 spd_ddr2_calc_checksum(u8 *spd, int len) +{ + int i; + u8 c = 0; + + if (len < 63) + /* Not enough bytes available to get the checksum */ + return 0; + + for (i = 0; i < 63; i++) + c += spd[i]; + + return c; +} + +/** + * \brief Return size of SPD. + * + * Returns size of SPD. Usually 128 Byte. + */ +u32 spd_decode_spd_size_ddr2(u8 byte0) +{ + return byte0; +} + +/** + * \brief Return size of eeprom. + * + * Returns size of eeprom. Usually 256 Byte. + */ +u32 spd_decode_eeprom_size_ddr2(u8 byte1) +{ + if (!byte1) + return 0; + + if (byte1 > 0x0e) + return 0x3fff; + + return 1 << byte1; +} + +/** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_msbs(u8 c) +{ + int i; + for (i = 7; i >= 0; i--) + if (c & (1 << i)) + return i; + + return 0; +} + +/** + * \brief Decode SPD tck cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_tck_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + + low = c & 0xf; + if (low == 0x0A) + low = 25; + else if (low == 0x0B) + low = 33; + else if (low == 0x0C) + low = 66; + else if (low == 0x0D) + low = 75; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD bcd style timings + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_bcd_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + low = c & 0xf; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD tRP, tRRP cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_quarter_time(u8 c) +{ + u8 high, low; + + high = c >> 6; + + low = c & 0x3; + + if (low == 1) + low = 25; + else if (low == 2) + low = 50; + else if (low == 3) + low = 75; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD tRR time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static u32 spd_decode_tRR_time(u8 c) +{ + switch (c) { + default: + case 0: + return 15625 << 8; + case 1: + return 15625 << 6; + case 2: + return 15625 << 7; + case 3: + return 15625 << 9; + case 4: + return 15625 << 10; + case 5: + return 15625 << 11; + } +} + +/** + * \brief Decode SPD tRP,tRFC time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC) +{ + u8 b40, b41, b42; + + b40 = spd_40_41_42[0]; + b41 = spd_40_41_42[1]; + b42 = spd_40_41_42[2]; + + *tRC = b41 << 8; + *tRFC = b42 << 8; + + if (b40 & 0x01) + *tRFC += 256 << 8; + + switch ((b40 >> 1) & 0x07) { + case 1: + *tRFC += (25 << 8) / 100; + break; + case 2: + *tRFC += (33 << 8) / 100; + break; + case 3: + *tRFC += (50 << 8) / 100; + break; + case 4: + *tRFC += (66 << 8) / 100; + break; + case 5: + *tRFC += (75 << 8) / 100; + break; + default: + break; + } + + switch ((b40 >> 4) & 0x07) { + case 1: + *tRC += (25 << 8) / 100; + break; + case 2: + *tRC += (33 << 8) / 100; + break; + case 3: + *tRC += (50 << 8) / 100; + break; + case 4: + *tRC += (66 << 8) / 100; + break; + case 5: + *tRC += (75 << 8) / 100; + break; + default: + break; + } +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR2 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd) +{ + int ret, i; + u16 eeprom_size; + u8 spd_size; + u8 cl; + u8 reg8; + + spd_size = spd_decode_spd_size_ddr2(spd[0]); + eeprom_size = spd_decode_eeprom_size_ddr2(spd[1]); + + printram("EEPROM with 0x%04x bytes\n", eeprom_size); + printram("SPD contains 0x%02x bytes\n", spd_size); + + if (spd_size < 64 || eeprom_size < 64) { + printram("ERROR: SPD to small\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { + printram("ERROR: SPD checksum error\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + reg8 = spd[62]; + if ((reg8 & 0xf0) != 0x10) { + printram("ERROR: Unsupported SPD revision %01x.%01x\n", + reg8 >> 4, reg8 & 0xf); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Revision : %01x.%01x\n", reg8 >> 4, reg8 & 0xf); + + reg8 = spd[2]; + if (reg8 != 0x08) { + printram("ERROR: Unsupported SPD type %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Type : %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR2; + + dimm->row_bits = spd[3]; + if (dimm->row_bits > 31) { + printram(" Invalid number of memory rows\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Rows : %x\n", dimm->row_bits); + + dimm->col_bits = spd[4]; + if (dimm->col_bits > 16) { + printram(" Invalid number of memory columns\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Columns : %x\n", dimm->col_bits); + + dimm->ranks = spd[5] & 0x7; + printram(" Ranks : %x\n", dimm->ranks); + + dimm->mod_width = spd[6]; + printram(" Module width : x%u\n", dimm->mod_width); + + dimm->width = spd[13]; + printram(" Width : x%u\n", dimm->width); + + dimm->banks = spd[17]; + printram(" Banks : %x\n", dimm->banks); + + switch (spd[8]) { + case 0: + dimm->flags.operable_5_00V = 1; + printram(" Voltage : 5.0V\n"); + break; + case 1: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 2: + dimm->flags.operable_1_50V = 1; + printram(" Voltage : 1.5V\n"); + break; + case 3: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 4: + dimm->flags.operable_2_50V = 1; + printram(" Voltage : 2.5V\n"); + break; + case 5: + dimm->flags.operable_1_80V = 1; + printram(" Voltage : 1.8V\n"); + break; + default: + printram(" Unknown voltage level.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->cas_supported = spd[18]; + if (dimm->cas_supported & 0x3) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Supported CAS : 0x%x\n", dimm->cas_supported); + + cl = spd_get_msbs(dimm->cas_supported); + + dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); + dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); + + if (dimm->cas_supported & (1 << (cl - 1))) { + dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]); + dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]); + } + if (dimm->cas_supported & (1 << (cl - 2))) { + dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]); + dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]); + } + + for (i = 2; i < 8; i++) { + printram(" Cycle time at CL%d : %u\n", i, dimm->cycle_time[i]); + printram(" Accesstime at CL%d : %u\n", i, dimm->access_time[i]); + } + + reg8 = (spd[31] >> 5) | (spd[31] << 3); + dimm->size_mb = 64 << reg8; + + if (reg8 < 0x08) + printram(" Capacity : %u Mb\n", 64 << reg8); + else + printram(" Capacity : %u Gb\n", 1 << (reg8 - 8)); + + + /* SDRAM Minimum Cycle Time (tCKmin) */ + dimm->tCK = spd_decode_tck_time(spd[43]); + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd_decode_quarter_time(spd[36]); + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd_decode_quarter_time(spd[29]); + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd_decode_quarter_time(spd[28]); + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd_decode_quarter_time(spd[27]); + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = spd[30] << 8; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + spd_decode_tRPtRFC_time(&spd[40], &dimm->tRC, &dimm->tRFC); + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd_decode_quarter_time(spd[37]); + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd_decode_quarter_time(spd[38]); + /* Data Input Setup Time Before Strobe */ + dimm->tDS = spd_decode_bcd_time(spd[34]); + /* Data Input Hold Time After Strobe */ + dimm->tDH = spd_decode_bcd_time(spd[35]); + /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */ + dimm->tDQSQ = spd[44]; + /* SDRAM Device Read Data Hold Skew Factor */ + dimm->tQHS = spd[45]; + /* PLL Relock Time */ + dimm->tPLL = spd[46] << 8; + /* Refresh rate */ + dimm->tRR = spd_decode_tRR_time(spd[12]); + + /* SDRAM Thermal and Refresh Options */ + printram(" General features :"); + if (spd[22] & 0x04) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if (spd[22] & 0x02) { + dimm->flags.terminate_50ohms = 1; + printram(" 50Ohm"); + } + if (spd[22] & 0x01) { + dimm->flags.weak_driver = 1; + printram(" WEAK DRIVER"); + } + printram("\n"); + + /* SDRAM Supported Burst length */ + printram(" Burst length :"); + if (spd[16] & 0x06) { + dimm->flags.bl8 = 1; + printram(" BL8"); + } + if (spd[22] & 0x04) { + dimm->flags.bl4 = 1; + printram(" BL4"); + } + printram("\n"); + + dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; + printram(" Dimm type : %x\n", dimm->dimm_type); + + dimm->flags.is_ecc = !!(spd[11] & 0x3); + printram(" ECC support : %x\n", dimm->flags.is_ecc); + + if (spd_size > 71) { + memcpy(&dimm->manufacturer_id, &spd[64], 4); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); + } + + if (spd_size > 90) { + dimm->part_number[16] = 0; + memcpy(&dimm->part_number, &spd[73], 16); + printram(" Part number : %s\n", dimm->part_number); + } + + return ret; +} + +/* + * The information printed below has a more informational character, and is not + * necessarily tied in to RAM init debugging. Hence, we stop using printram(), + * and use the standard printk()'s below. + */ + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); +} + +static void print_us(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); +} + +/** +* \brief Print the info in DIMM +* +* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected, or for a purely informative output. +* +* @param dimm pointer to already decoded @ref dimm_attr structure +*/ +void dram_print_spd_ddr2(const dimm_attr *dimm) +{ + u8 val8; + int i; + + printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); + printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Width : x%u\n", dimm->width); + printk(BIOS_INFO, " Banks : %u\n", dimm->banks); + + /* CAS Latencies Supported */ + val8 = dimm->cas_supported; + printk(BIOS_INFO, " CAS latencies :"); + i = 2; + do { + if (val8 & 1) + printk(BIOS_INFO, " %u", i); + i++; + val8 >>= 1; + } while (val8); + printk(BIOS_INFO, "\n"); + + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tDS : ", dimm->tDS); + print_ns(" tDH : ", dimm->tDH); + print_ns(" tDQSQ : ", dimm->tDQSQ); + print_ns(" tQHS : ", dimm->tQHS); + print_ns(" tPLL : ", dimm->tPLL); + print_us(" tRR : ", dimm->tRR); +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h new file mode 100644 index 0000000..6a20c12 --- /dev/null +++ b/src/include/device/dram/ddr2.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) + */ + +#ifndef DEVICE_DRAM_DDR2L_H +#define DEVICE_DRAM_DDR2L_H + +/** + * @file ddr2.h + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR2 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_800MHZ 320 +#define TCK_700MHZ 365 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/* + * Module type (byte 20, bits 5:0) of SPD + * This definition is specific to DDR2. DDR3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DIMM_TYPE_RDIMM = 0x01, + SPD_DIMM_TYPE_UDIMM = 0x02, + SPD_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, + SPD_DIMM_TYPE_MICRO_DIMM = 0x08, + SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_UDIMM = 0x20, + /* Masks to bits 5:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0x3f, +}; + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +typedef union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Module can work at 5.00V */ + unsigned operable_5_00V:1; + /* Module can work at 3.33V */ + unsigned operable_3_33V:1; + /* Module can work at 2.50V */ + unsigned operable_2_50V:1; + /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ + unsigned operable_1_80V:1; + /* Module can work at 1.50V */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_25V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* Supports weak driver */ + unsigned weak_driver:1; + /* Supports terminating at 50 Ohm */ + unsigned terminate_50ohms:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* Supports burst length 8 */ + unsigned bl8:1; + /* Supports burst length 4 */ + unsigned bl4:1; + }; + unsigned int raw; +} dimm_flags_t; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + u8 cas_supported; + + /* Cycle times for various CAS */ + u32 cycle_time[8]; + /* Maximum data access times for various CAS */ + u32 access_time[8]; + /* Flags extracted from SPD */ + dimm_flags_t flags; + /* Number of banks */ + u8 banks; + /* SDRAM width */ + u8 width; + /* Module width */ + u8 mod_width; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Size of module in MiB */ + u32 size_mb; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tIS; + u32 tIH; + u32 tDS; + u32 tDH; + + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tDQSQ; + u32 tQHS; + u32 tPLL; + + /* Latencies are in units of 1/256 us */ + u32 tRR; + + /* Manufacturer ID */ + u32 manufacturer_id; // + /* ASCII part number - NULL terminated */ + u8 part_number[17]; +} dimm_attr; + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +typedef u8 spd_raw_data[128]; + +int dimm_is_registered(enum spd_dimm_type type); +u8 spd_ddr2_calc_checksum(u8 *spd, int len); +u32 spd_decode_spd_size_ddr2(u8 byte0); +u32 spd_decode_eeprom_size_ddr2(u8 byte1); +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); +void dram_print_spd_ddr2(const dimm_attr *dimm); + + +#endif /* DEVICE_DRAM_DDR2L_H */

1 0

Patch set updated for coreboot: NOT FOR MERGE: test ddr2 spd decode
by Arthur Heymans 02 Feb '17

02 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18278 -gerrit commit 83fc8fd667926e46aaa46bd697bdc34f6edb2bde Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 1 23:02:17 2017 +0100 NOT FOR MERGE: test ddr2 spd decode Change-Id: I3494009eec88eb31efd031a6da27fd1108131beb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/Kconfig | 4 ++++ src/device/dram/Makefile.inc | 1 + src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/raminit.c | 12 +++++++++++- 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..baa72c0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -214,6 +214,10 @@ config SPD_CACHE bool default n +config DDR2_SPD + bool + default n + config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..dbe4412 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-$(CONFIG_DDR2_SPD) += ddr2.c diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index efe192b..65be5a1 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE + select DDR2_SPD config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..e86ff17 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,7 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; + int i, j; /** * i945 supports two DIMMs, in two configurations: @@ -360,6 +361,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) for (i = 0; i<(2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); u8 reg8; + spd_raw_data raw_spd; + dimm_attr *dimm = NULL; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -375,6 +378,13 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) continue; } + for (j = 0; j < 128; j++) + raw_spd[j] = spd_read_byte(device, j); + printk(BIOS_DEBUG, "Before spd_decode_ddr2\n"); + spd_decode_ddr2(dimm, raw_spd); + printk(BIOS_DEBUG, "Before dram_print_spd_ddr2\n"); + dram_print_spd_ddr2(dimm); + reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); if (reg8 == ERROR_SCHEME_ECC) die("Error: ECC memory not supported by this chipset\n");

1 0

Patch set updated for coreboot: NOT FOR MERGE: test ddr2 spd decode
by Arthur Heymans 02 Feb '17

02 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18278 -gerrit commit 6f58ad358a479147844ed2c82a7feeb5c84e24c2 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 1 23:02:17 2017 +0100 NOT FOR MERGE: test ddr2 spd decode Change-Id: I3494009eec88eb31efd031a6da27fd1108131beb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/Kconfig | 4 ++++ src/device/dram/Makefile.inc | 1 + src/device/dram/ddr2.c | 2 +- src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/raminit.c | 12 +++++++++++- 5 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..baa72c0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -214,6 +214,10 @@ config SPD_CACHE bool default n +config DDR2_SPD + bool + default n + config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..dbe4412 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-$(CONFIG_DDR2_SPD) += ddr2.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index aa51b50..4f257bc 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -385,7 +385,7 @@ int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd) } printram(" Supported CAS : 0x%x\n", dimm->cas_supported); - cl = spd_get_msbs(dimm->cas_supported); + cl = spd_get_msbs(dimm->cas_supported) - 2; dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index efe192b..65be5a1 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE + select DDR2_SPD config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..e86ff17 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,7 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; + int i, j; /** * i945 supports two DIMMs, in two configurations: @@ -360,6 +361,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) for (i = 0; i<(2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); u8 reg8; + spd_raw_data raw_spd; + dimm_attr *dimm = NULL; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -375,6 +378,13 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) continue; } + for (j = 0; j < 128; j++) + raw_spd[j] = spd_read_byte(device, j); + printk(BIOS_DEBUG, "Before spd_decode_ddr2\n"); + spd_decode_ddr2(dimm, raw_spd); + printk(BIOS_DEBUG, "Before dram_print_spd_ddr2\n"); + dram_print_spd_ddr2(dimm); + reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); if (reg8 == ERROR_SCHEME_ECC) die("Error: ECC memory not supported by this chipset\n");

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Patch set updated for coreboot: device/dram/ddr2: Add common ddr2 spd decoder
by Patrick Rudolph 02 Feb '17

02 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18273 -gerrit commit 7aea02ac823b2fde04bdb5001a077ded28776d8d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 31 19:43:17 2017 +0100 device/dram/ddr2: Add common ddr2 spd decoder Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr2.c | 568 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 201 +++++++++++++++ 2 files changed, 769 insertions(+) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c new file mode 100644 index 0000000..aa51b50 --- /dev/null +++ b/src/device/dram/ddr2.c @@ -0,0 +1,568 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file ddr2.c + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr2.h> +#include <string.h> + +/*============================================================================== + * = DDR2 SPD decoding helpers + *----------------------------------------------------------------------------*/ + +/** + * \brief Checks if the DIMM is Registered based on byte[20] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[20] of the SPD. + */ +int dimm_is_registered(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Calculate the checksum of a DDR2 SPD unique identifier + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the checksum of SPD data bytes 63, or 0 when spd data is truncated. + */ +u8 spd_ddr2_calc_checksum(u8 *spd, int len) +{ + int i; + u8 c = 0; + + if (len < 63) + /* Not enough bytes available to get the checksum */ + return 0; + + for (i = 0; i < 63; i++) + c += spd[i]; + + return c; +} + +/** + * \brief Return size of SPD. + * + * Returns size of SPD. Usually 128 Byte. + */ +u32 spd_decode_spd_size_ddr2(u8 byte0) +{ + return byte0; +} + +/** + * \brief Return size of eeprom. + * + * Returns size of eeprom. Usually 256 Byte. + */ +u32 spd_decode_eeprom_size_ddr2(u8 byte1) +{ + if (!byte1) + return 0; + + if (byte1 > 0x0e) + return 0x3fff; + + return 1 << byte1; +} + +/** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_msbs(u8 c) +{ + int i; + for (i = 7; i >= 0; i--) + if (c & (1 << i)) + return i; + + return 0; +} + +/** + * \brief Decode SPD tck cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_tck_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + + low = c & 0xf; + if (low == 0x0A) + low = 25; + else if (low == 0x0B) + low = 33; + else if (low == 0x0C) + low = 66; + else if (low == 0x0D) + low = 75; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD bcd style timings + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_bcd_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + low = c & 0xf; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD tRP, tRRP cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_quarter_time(u8 c) +{ + u8 high, low; + + high = c >> 6; + + low = c & 0x3; + + if (low == 1) + low = 25; + else if (low == 2) + low = 50; + else if (low == 3) + low = 75; + + return (high << 8) + ((low << 8) / 10); +} + +/** + * \brief Decode SPD tRR time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static u32 spd_decode_tRR_time(u8 c) +{ + switch (c) { + default: + case 0: + return 15625 << 8; + case 1: + return 15625 << 6; + case 2: + return 15625 << 7; + case 3: + return 15625 << 9; + case 4: + return 15625 << 10; + case 5: + return 15625 << 11; + } +} + +/** + * \brief Decode SPD tRP,tRFC time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static void spd_decode_tRPtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC) +{ + u8 b40, b41, b42; + + b40 = spd_40_41_42[0]; + b41 = spd_40_41_42[1]; + b42 = spd_40_41_42[2]; + + *tRC = b41 << 8; + *tRFC = b42 << 8; + + if (b40 & 0x01) + *tRFC += 256 << 8; + + switch ((b40 >> 1) & 0x07) { + case 1: + *tRFC += (25 << 8) / 100; + break; + case 2: + *tRFC += (33 << 8) / 100; + break; + case 3: + *tRFC += (50 << 8) / 100; + break; + case 4: + *tRFC += (66 << 8) / 100; + break; + case 5: + *tRFC += (75 << 8) / 100; + break; + default: + break; + } + + switch ((b40 >> 4) & 0x07) { + case 1: + *tRC += (25 << 8) / 100; + break; + case 2: + *tRC += (33 << 8) / 100; + break; + case 3: + *tRC += (50 << 8) / 100; + break; + case 4: + *tRC += (66 << 8) / 100; + break; + case 5: + *tRC += (75 << 8) / 100; + break; + default: + break; + } +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR2 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd) +{ + int ret, i; + u16 eeprom_size; + u8 spd_size; + u8 cl; + u8 reg8; + + spd_size = spd_decode_spd_size_ddr2(spd[0]); + eeprom_size = spd_decode_eeprom_size_ddr2(spd[1]); + + printram("EEPROM with 0x%04x bytes\n", eeprom_size); + printram("SPD contains 0x%02x bytes\n", spd_size); + + if (spd_size < 64 || eeprom_size < 64) { + printram("ERROR: SPD to small\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { + printram("ERROR: SPD checksum error\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + reg8 = spd[62]; + if ((reg8 & 0xf0) != 0x10) { + printram("ERROR: Unsupported SPD revision %01x.%01x\n", + reg8 >> 4, reg8 & 0xf); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Revision : %01x.%01x\n", reg8 >> 4, reg8 & 0xf); + + reg8 = spd[2]; + if (reg8 != 0x08) { + printram("ERROR: Unsupported SPD type %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Type : %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR2; + + dimm->row_bits = spd[3]; + if (dimm->row_bits > 31) { + printram(" Invalid number of memory rows\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Rows : %x\n", dimm->row_bits); + + dimm->col_bits = spd[4]; + if (dimm->col_bits > 16) { + printram(" Invalid number of memory columns\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Columns : %x\n", dimm->col_bits); + + dimm->ranks = spd[5] & 0x7; + printram(" Ranks : %x\n", dimm->ranks); + + dimm->mod_width = spd[6]; + printram(" Module width : x%u\n", dimm->mod_width); + + dimm->width = spd[13]; + printram(" Width : x%u\n", dimm->width); + + dimm->banks = spd[17]; + printram(" Banks : %x\n", dimm->banks); + + switch (spd[8]) { + case 0: + dimm->flags.operable_5_00V = 1; + printram(" Voltage : 5.0V\n"); + break; + case 1: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 2: + dimm->flags.operable_1_50V = 1; + printram(" Voltage : 1.5V\n"); + break; + case 3: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 4: + dimm->flags.operable_2_50V = 1 + printram(" Voltage : 2.5V\n"); + break; + case 5: + dimm->flags.operable_1_80V = 1; + printram(" Voltage : 1.8V\n"); + break; + default: + printram(" Unknown voltage level.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->cas_supported = spd[18]; + if (dimm->cas_supported & 0x3) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Supported CAS : 0x%x\n", dimm->cas_supported); + + cl = spd_get_msbs(dimm->cas_supported); + + dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); + dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); + + if (dimm->cas_supported & (1 << (cl - 1))) { + dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]); + dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]); + } + if (dimm->cas_supported & (1 << (cl - 2))) { + dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]); + dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]); + } + + for (i = 2; i < 8; i++) { + printram(" Cycle time at CL%d : %u\n", i, dimm->cycle_time[i]); + printram(" Accesstime at CL%d : %u\n", i, dimm->access_time[i]); + } + + reg8 = (spd[31] >> 5) | (spd[31] << 3); + dimm->size_mb = 64 << reg8; + + if (reg8 < 0x08) + printram(" Capacity : %u Mb\n", 64 << reg8); + else + printram(" Capacity : %u Gb\n", 1 << (reg8 - 8)); + + + /* SDRAM Minimum Cycle Time (tCKmin) */ + dimm->tCK = spd_decode_tck_time(spd[43]); + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd_decode_quarter_time(spd[36]); + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd_decode_quarter_time(spd[29]); + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd_decode_quarter_time(spd[28]); + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd_decode_quarter_time(spd[27]); + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = spd[30] << 8; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + spd_decode_tRPtRFC_time(&spd[40], &dimm->tRC, &dimm->tRFC); + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd_decode_quarter_time(spd[37]); + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd_decode_quarter_time(spd[38]); + /* Data Input Setup Time Before Strobe */ + dimm->tDS = spd_decode_bcd_time(spd[34]); + /* Data Input Hold Time After Strobe */ + dimm->tDH = spd_decode_bcd_time(spd[35]); + /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */ + dimm->tDQSQ = spd[44]; + /* SDRAM Device Read Data Hold Skew Factor */ + dimm->tQHS = spd[45]; + /* PLL Relock Time */ + dimm->tPLL = spd[46] << 8; + /* Refresh rate */ + dimm->tRR = spd_decode_tRR_time(spd[12]); + + /* SDRAM Thermal and Refresh Options */ + printram(" General features :"); + if (spd[22] & 0x04) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if (spd[22] & 0x02) { + dimm->flags.terminate_50ohms = 1; + printram(" 50Ohm"); + } + if (spd[22] & 0x01) { + dimm->flags.weak_driver = 1; + printram(" WEAK DRIVER"); + } + printram("\n"); + + /* SDRAM Supported Burst length */ + printram(" Burst length :"); + if (spd[16] & 0x06) { + dimm->flags.bl8 = 1; + printram(" BL8"); + } + if (spd[22] & 0x04) { + dimm->flags.bl4 = 1; + printram(" BL4"); + } + printram("\n"); + + dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; + printram(" Dimm type : %x\n", dimm->dimm_type); + + dimm->flags.is_ecc = !!(spd[11] & 0x3); + printram(" ECC support : %x\n", dimm->flags.is_ecc); + + if (spd_size > 71) { + memcpy(&dimm->manufacturer_id, &spd[64], 4); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); + } + + if (spd_size > 90) { + dimm->part_number[16] = 0; + memcpy(dimm->part_number, &spd[73], 16); + printram(" Part number : %s\n", dimm->part_number); + } + + return ret; +} + +/* + * The information printed below has a more informational character, and is not + * necessarily tied in to RAM init debugging. Hence, we stop using printram(), + * and use the standard printk()'s below. + */ + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); +} + +static void print_us(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); +} + +/** +* \brief Print the info in DIMM +* +* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected, or for a purely informative output. +* +* @param dimm pointer to already decoded @ref dimm_attr structure +*/ +void dram_print_spd_ddr2(const dimm_attr *dimm) +{ + u8 val8; + int i; + + printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); + printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Width : x%u\n", dimm->width); + printk(BIOS_INFO, " Banks : %u\n", dimm->banks); + + /* CAS Latencies Supported */ + val8 = dimm->cas_supported; + printk(BIOS_INFO, " CAS latencies :"); + i = 2; + do { + if (val8 & 1) + printk(BIOS_INFO, " %u", i); + i++; + val8 >>= 1; + } while (val8); + printk(BIOS_INFO, "\n"); + + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tDS : ", dimm->tDS); + print_ns(" tDH : ", dimm->tDH); + print_ns(" tDQSQ : ", dimm->tDQSQ); + print_ns(" tQHS : ", dimm->tQHS); + print_ns(" tPLL : ", dimm->tPLL); + print_us(" tRR : ", dimm->tRR); +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h new file mode 100644 index 0000000..6a20c12 --- /dev/null +++ b/src/include/device/dram/ddr2.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) + */ + +#ifndef DEVICE_DRAM_DDR2L_H +#define DEVICE_DRAM_DDR2L_H + +/** + * @file ddr2.h + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR2 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_800MHZ 320 +#define TCK_700MHZ 365 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/* + * Module type (byte 20, bits 5:0) of SPD + * This definition is specific to DDR2. DDR3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DIMM_TYPE_RDIMM = 0x01, + SPD_DIMM_TYPE_UDIMM = 0x02, + SPD_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, + SPD_DIMM_TYPE_MICRO_DIMM = 0x08, + SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_UDIMM = 0x20, + /* Masks to bits 5:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0x3f, +}; + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +typedef union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Module can work at 5.00V */ + unsigned operable_5_00V:1; + /* Module can work at 3.33V */ + unsigned operable_3_33V:1; + /* Module can work at 2.50V */ + unsigned operable_2_50V:1; + /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ + unsigned operable_1_80V:1; + /* Module can work at 1.50V */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_25V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* Supports weak driver */ + unsigned weak_driver:1; + /* Supports terminating at 50 Ohm */ + unsigned terminate_50ohms:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* Supports burst length 8 */ + unsigned bl8:1; + /* Supports burst length 4 */ + unsigned bl4:1; + }; + unsigned int raw; +} dimm_flags_t; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + u8 cas_supported; + + /* Cycle times for various CAS */ + u32 cycle_time[8]; + /* Maximum data access times for various CAS */ + u32 access_time[8]; + /* Flags extracted from SPD */ + dimm_flags_t flags; + /* Number of banks */ + u8 banks; + /* SDRAM width */ + u8 width; + /* Module width */ + u8 mod_width; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Size of module in MiB */ + u32 size_mb; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tIS; + u32 tIH; + u32 tDS; + u32 tDH; + + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tDQSQ; + u32 tQHS; + u32 tPLL; + + /* Latencies are in units of 1/256 us */ + u32 tRR; + + /* Manufacturer ID */ + u32 manufacturer_id; // + /* ASCII part number - NULL terminated */ + u8 part_number[17]; +} dimm_attr; + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +typedef u8 spd_raw_data[128]; + +int dimm_is_registered(enum spd_dimm_type type); +u8 spd_ddr2_calc_checksum(u8 *spd, int len); +u32 spd_decode_spd_size_ddr2(u8 byte0); +u32 spd_decode_eeprom_size_ddr2(u8 byte1); +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); +void dram_print_spd_ddr2(const dimm_attr *dimm); + + +#endif /* DEVICE_DRAM_DDR2L_H */

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Patch merged into coreboot/master: ectool: Support OpenBSD
by gerrit＠coreboot.org 02 Feb '17

02 Feb '17

the following patch was just integrated into master: commit 3236f7be093b3dfed606d6a6b4e81743ecfe0c5c Author: Steven Dee <i(a)wholezero.org> Date: Sun Jan 29 14:52:56 2017 -0500 ectool: Support OpenBSD Adds checks for OpenBSD in all the places that were already checking for NetBSD. This fixes e.g.: ec.c:21:20: error: sys/io.h: No such file or directory which was caused by defaulting to Linux. Also, OpenBSD calls its amd64 iopl amd64_iopl instead of x86_64_iopl. This change just defines iopl appropriately depending on the OS and architecture. TEST=Build on OpenBSD 6.0 or -current from 2017-01-25. Change-Id: If6d92a9850c15cd9f8e287cc4f963d3ff881f72c Signed-off-by: Steven Dee <i(a)wholezero.org> Reviewed-on: https://review.coreboot.org/18260 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18260 for details. -gerrit

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coreboot-gerrit February 2017