coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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1019 discussions

Patch set updated for coreboot: WIP Documentation/backlight-pwm: Gather backlight PWM infos
by Arthur Heymans 01 Feb '17

01 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18250 -gerrit commit f49809fb14b197e57eafcf0d2a2b7d28213bc384 Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Jan 27 15:55:28 2017 +0100 WIP Documentation/backlight-pwm: Gather backlight PWM infos Change-Id: I3a3456cee8ed053db13b4b9d2d3f5a8fc04bb7ff Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- Documentation/backlight-pwm.md | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/backlight-pwm.md b/Documentation/backlight-pwm.md new file mode 100644 index 0000000..fbb1b2a --- /dev/null +++ b/Documentation/backlight-pwm.md @@ -0,0 +1,27 @@ +# PWM frequencies for display backlights + +## Values found in use by vendors + +* `Lenovo Thinkpad T60`: 0x58be/275Hz (@200MHz CDClk) + +* `Lenovo ThinkPad X60`: 0x879e/180Hz (@200MHz CDClk) + +* `Lenovo ThinkPad X200s`: 0x0cf8/753Hz (@320MHz CDClk) + LED backlight, panel: + Manufacturer: LEN Model 4014 Serial Number 0 + ASCII string: LTD121EQ3B + +* `Lenovo ThinkPad X301`: 0x24fc/264Hz (@320MHz CDClk) + LED backlight, panel: + Manufacturer: LEN Model 4074 Serial Number 0 + ASCII string: LTD133EQ1B + +## Often copy-pasted constants + +* `0x0610 for gm45`: First seen in commit 6481e10 + "gma45: Ensure that brightness register in gma contains a sane vaule" + Depending on the CDClk frequency (222MHz .. 333MHz) 1.12kHz .. 1.61kHz + +* `0x0128 for i945`: First seen for lenovo/x60 in commit 26ca08c + "i945: Replace video gfx init." + With a CDClk of 200MHz it gives a 21.1kHz PWM.

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New patch to review for coreboot: mainboards/google/reef: Add support for tablet mode switch.
by Gwendal Grignou 01 Feb '17

01 Feb '17

Gwendal Grignou (gwendal(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18277 -gerrit commit b195f9f0dac361b13e6a36e9bcc6415ef59443f5 Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Wed Feb 1 12:56:24 2017 -0800 mainboards/google/reef: Add support for tablet mode switch. Reef is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I6dfddbfdb5a2ffbdfd77c5f49602bf68e9693a06 Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> --- .../google/reef/variants/baseboard/include/baseboard/ec.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h index 87c127c..47b193f 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h @@ -34,7 +34,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) @@ -67,7 +68,10 @@ /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TABLET_EVENT #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */

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New patch to review for coreboot: google/eve: Add support for tablet mode switch.
by Gwendal Grignou 01 Feb '17

01 Feb '17

Gwendal Grignou (gwendal(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18276 -gerrit commit 8a0a20566362d02a181fe90b017e914d9a2374dd Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Wed Feb 1 12:11:27 2017 -0800 google/eve: Add support for tablet mode switch. Eve is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I35133ebc1439852d0ceb88d7d679b37356b0869d Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> --- src/mainboard/google/eve/ec.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/ec.h b/src/mainboard/google/eve/ec.h index d0e59e1..884b105 100644 --- a/src/mainboard/google/eve/ec.h +++ b/src/mainboard/google/eve/ec.h @@ -35,7 +35,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) @@ -73,6 +74,9 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable Tablet switch */ +#define EC_ENABLE_TABLET_EVENT + #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */

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Patch set updated for coreboot: ec/google/chromeec: Add support for tablet mode switch driver
by Gwendal Grignou 01 Feb '17

01 Feb '17

Gwendal Grignou (gwendal(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18173 -gerrit commit 738d1f9998c755f004c0ccfd0fbb1e37ca610a28 Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Thu Jan 19 18:30:21 2017 -0800 ec/google/chromeec: Add support for tablet mode switch driver Add a new driver GOOG0006 to report tablet switch to user space. On glados based convertible, check that with a new kernel driver (cros_ec_tbmc) that evtest collects tablet switch changes. Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/430951 Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/ec/google/chromeec/acpi/ec.asl | 7 +++++++ src/ec/google/chromeec/acpi/tbmc.asl | 29 +++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index b182766..a40d0ac 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -322,6 +322,7 @@ Device (EC0) Notify (CREC, 0x80) } +#ifdef EC_ENABLE_TABLET_EVENT // TABLET mode switch Event Method (_Q1D, 0, NotSerialized) { @@ -329,7 +330,9 @@ Device (EC0) If (CondRefOf (\_SB.DPTF.TPET)) { \_SB.DPTF.TPET() } + Notify (TBMC, 0x80) } +#endif /* * Dynamic Platform Thermal Framework support @@ -478,4 +481,8 @@ Device (EC0) #ifdef EC_ENABLE_PD_MCU_DEVICE #include "pd.asl" #endif + +#ifdef EC_ENABLE_TABLET_EVENT + #include "tbmc.asl" +#endif } diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl new file mode 100644 index 0000000..25a27ef1b --- /dev/null +++ b/src/ec/google/chromeec/acpi/tbmc.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (TBMC) +{ + Name (_HID, "GOOG0006") + Name (_UID, 1) + Name (_DDN, "Tablet Motion Control") + Method (TBMC) + { + If (LEqual (^^RCTM, One)) { + Return (0x1) + } Else { + Return (0x0) + } + } +}

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Patch set updated for coreboot: Select a default SeaBIOS PS2 timeout in H8 Kconfig
by Arthur Heymans 01 Feb '17

01 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18274 -gerrit commit 09bcb862001238c3ccac1c00ba8fbb77e2c2ad19 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Jan 31 23:16:25 2017 +0100 Select a default SeaBIOS PS2 timeout in H8 Kconfig This timeout is probably needed on all devices with Lenovo H8 embedded controllers so set the default there. Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/ec/lenovo/h8/Kconfig | 9 +++++++++ src/mainboard/lenovo/t400/Kconfig | 5 ----- src/mainboard/lenovo/t420/Kconfig | 5 ----- src/mainboard/lenovo/t420s/Kconfig | 5 ----- src/mainboard/lenovo/t520/Kconfig | 5 ----- src/mainboard/lenovo/t60/Kconfig | 5 ----- src/mainboard/lenovo/x200/Kconfig | 5 ----- src/mainboard/lenovo/x201/Kconfig | 5 ----- src/mainboard/lenovo/x220/Kconfig | 5 ----- src/mainboard/lenovo/x60/Kconfig | 5 ----- 10 files changed, 9 insertions(+), 45 deletions(-) diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 6a9d055..98e8e30 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -2,5 +2,14 @@ config EC_LENOVO_H8 select EC_ACPI bool +if EC_LENOVO_H8 + +config SEABIOS_PS2_TIMEOUT + int + depends on PAYLOAD_SEABIOS + default 3000 + +endif + config H8_DOCK_EARLY_INIT bool diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f21f672..23c7d02 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -55,9 +55,4 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif # BOARD_LENOVO_T400 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index e2272b1..04233e7 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -76,9 +76,4 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif # BOARD_LENOVO_T420 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index d278ccb..feacb51 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -75,9 +75,4 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 4ce27f1..ee5dd81 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -75,9 +75,4 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif # BOARD_LENOVO_T520 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 9fb46e2..289c06a 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -42,9 +42,4 @@ config MAX_CPUS int default 2 -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index cec08f6..ff6139e 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -47,9 +47,4 @@ config CBFS_SIZE hex default 0x200000 -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif # BOARD_LENOVO_X200 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 0bf6135..239a815 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -48,9 +48,4 @@ config CPU_ADDR_BITS int default 36 -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 5367fd1..0ef6689 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -73,9 +73,4 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21db -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index d80b22d..7667a75 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -49,9 +49,4 @@ config MAX_CPUS int default 2 -config SEABIOS_PS2_TIMEOUT - int - depends on PAYLOAD_SEABIOS - default 3000 - endif

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Patch set updated for coreboot: [WIP] nb/i945/gma.c: Refactor panel setup
by Arthur Heymans 01 Feb '17

01 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit 837f1e34a298511bdf2adc0de34131c46047eebc Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 [WIP] nb/i945/gma.c: Refactor panel setup This reuses gm45 code to set up panel. Panel start and stop delays and pwm frequency can now be set in devicetree. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60. TODO: find pwm freq on T60 and macbook21. TESTED on Lenovo Thinkpad X60 Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/i915_reg.h | 2 +- src/mainboard/apple/macbook21/devicetree.cb | 7 +- src/mainboard/lenovo/t60/devicetree.cb | 7 +- src/mainboard/lenovo/x60/devicetree.cb | 7 +- src/northbridge/intel/i945/chip.h | 7 +- src/northbridge/intel/i945/gma.c | 104 +++++++++++++++++++++++++--- 6 files changed, 118 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..dee6865 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -62,7 +62,7 @@ #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..b6e61eb 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..9daba3a 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..28b63d3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..5bbda81 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,13 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..8b73d7b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -46,6 +46,19 @@ #define PGETBL_ENABLED 0x00000001 #define BASE_FREQUENCY 100000 +#define DEFAULT_PWM 1000 + +static struct resource *gtt_res = NULL; + +u32 gtt_read(u32 reg) +{ + return read32(res2mmio(gtt_res, reg, 0)); +} + +void gtt_write(u32 reg, u32 data) +{ + write32(res2mmio(gtt_res, reg, 0), data); +} static int gtt_setup(void *mmiobase) { @@ -292,17 +305,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(pmmio + DSPPOS(0), 0); - /* Backlight init. */ - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC, 0x011d011a); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC_SELF, 0x0001003f); - write32(pmmio + FW_BLC, 0x011d0109); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(pmmio + DSPADDR(0), 0); write32(pmmio + DSPSURF(0), 0); @@ -579,6 +581,80 @@ static int probe_edid(u8 *pmmio, u8 slave) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + u16 gcfgc = pci_read_config16(dev, GCFGC); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) + return 133333333; + else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_320_MHZ: + return 320000000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 200000000; + } + } +} + +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + /* Set duty cycle to 100% due to use of legacy backlight control */ + blc_mod = get_cdclk(dev) / (128 * pwm_freq); + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(PP_ON_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(PP_ON_DELAYS, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(PP_OFF_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(PP_OFF_DELAYS, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = (get_cdclk(dev) / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + gtt_write(PP_DIVISOR, reg32); + } + + /* Backlight init. */ + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC, 0x011d011a); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC_SELF, 0x0001003f); + gtt_write(FW_BLC, 0x011d0109); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + if (conf->pwm_freq == 0) { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, DEFAULT_PWM)); + } else { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); + } +} static void gma_func0_init(struct device *dev) { @@ -596,6 +672,8 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); @@ -623,6 +701,10 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + panel_setup(dev); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

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Patch merged into coreboot/master: payloads/depthcharge: Allow generic libpayload config
by gerrit＠coreboot.org 01 Feb '17

01 Feb '17

the following patch was just integrated into master: commit fc18507134bfe2cb9add3f1196832318cd8adcdc Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Dec 22 20:25:29 2016 -0500 payloads/depthcharge: Allow generic libpayload config Change depthcharge to not require a board-specific config file for libpayload. If the Kconfig option is selected, use the settings in libpayload/configs/defconfig instead. Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/18271 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18271 for details. -gerrit

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Patch merged into coreboot/master: Add Baytrail ChromeOS devices using variant scheme
by gerrit＠coreboot.org 01 Feb '17

01 Feb '17

the following patch was just integrated into master: commit 9be3f5dab46dd6997dc98203022b60241cf3d1c8 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jan 16 17:32:38 2017 -0600 Add Baytrail ChromeOS devices using variant scheme Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty, heli, kip, orco, quawks, squawks, sumo, swanky, and winky using their common reference board (rambi) as a base. Chromium sources used: firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...] firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...] firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...] firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...] firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...] firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...] firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*] firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.] firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data] firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data] firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...] firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table] firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...] The same basic cleanup/changes are made here as with the initial BYT variant commit: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) - Micron 2GB SPD file for kip with updated values renamed to distinguish from same file used by other boards Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/18164 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18164 for details. -gerrit

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Patch set updated for coreboot: payloads/depthcharge: Allow generic libpayload config
by Martin Roth 01 Feb '17

01 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18271 -gerrit commit f06f98f7a1d89ef849714701d86d062e3d8d4ac6 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Dec 22 20:25:29 2016 -0500 payloads/depthcharge: Allow generic libpayload config Change depthcharge to not require a board-specific config file for libpayload. If the Kconfig option is selected, use the settings in libpayload/configs/defconfig instead. Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- payloads/external/Makefile.inc | 3 ++- payloads/external/depthcharge/Kconfig | 8 ++++++++ payloads/external/depthcharge/Makefile | 13 ++++++++++--- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index d159da9..1c0d38c 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -109,7 +109,8 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \ DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \ DEPTHCHARGE_REVISION=$(CONFIG_DEPTHCHARGE_REVISION) \ - DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) + DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) \ + OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE) # FILO diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig index d6ce538..a913c7e 100644 --- a/payloads/external/depthcharge/Kconfig +++ b/payloads/external/depthcharge/Kconfig @@ -35,4 +35,12 @@ config PAYLOAD_FILE string default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" +config LP_DEFCONFIG_OVERRIDE + def_bool n + help + The Depthcharge makefile looks for a file config.<boardname> in the + libpayload/configs directory. Say Y here to use the file defconfig + instead. This is can be a convenience for development purposes, or + if the defaults in defconfig are sufficient for your system. + endif diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index 97d0950..f249a4a 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -30,6 +30,13 @@ unexport src srck obj objk BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR)) +ifeq ($(OVERRIDE_DEFCONFIG),y) +$(info Depthcharge: Using default defconfig for libpayload) +libpayload_config=$(libpayload_dir)/configs/defconfig +else +libpayload_config=$(libpayload_dir)/configs/config.$(BOARD) +endif + all: build $(project_dir): @@ -47,10 +54,10 @@ checkout: fetch cd $(project_dir) ; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) $(libpayload_install_dir): $(project_dir) - test -f $(libpayload_dir)/configs/config.$(BOARD) || \ - (echo "Error: $(libpayload_dir)/configs/config.$(BOARD) is not present" && \ + test -f $(libpayload_config)|| \ + (echo "Error: $(libpayload_config) is not present" && \ false) - cp $(libpayload_dir)/configs/config.$(BOARD) $(libpayload_dir)/.config + cp $(libpayload_config) $(libpayload_dir)/.config $(MAKE) -C $(libpayload_dir) olddefconfig $(MAKE) -C $(libpayload_dir) $(MAKE) -C $(libpayload_dir) install DESTDIR=$(libpayload_install_dir)

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Patch merged into coreboot/master: payloads/depthcharge: Specify revision to build
by gerrit＠coreboot.org 01 Feb '17

01 Feb '17

the following patch was just integrated into master: commit f9973b5c2bf9ec09c72579e152a2aefee3b6dd85 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Dec 22 18:16:48 2016 -0500 payloads/depthcharge: Specify revision to build Add the capability for specifying which version of depthcharge to checkout and build. This is similar to the existing feature for SeaBIOS. The depthcharge makefile already contains some structure for checking out master vs. stable however the calling Makefile.inc ingored this feature. Add the command-line variable assignment for these, along with a tree-ish for any revision. Change-Id: I99a5b088cb0ebb29e5d96a84217b3bfa852de8ac Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/18270 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18270 for details. -gerrit

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coreboot-gerrit February 2017