coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: payloads/depthcharge: Use variable target name
by gerrit＠coreboot.org 01 Feb '17

01 Feb '17

the following patch was just integrated into master: commit 8f470c7a7ef78266564403f46543737b400d8be6 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Dec 23 10:16:43 2016 -0500 payloads/depthcharge: Use variable target name Depending on the commit to build, depthcharge may have a different target name (depthcharge vs. depthcharge_unified). Add some logic to determine which name should be used based on the commit ID being requested. Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/18269 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18269 for details. -gerrit

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Patch set updated for coreboot: payloads/depthcharge: Use variable target name
by Martin Roth 01 Feb '17

01 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18269 -gerrit commit 86323f7c73a4ef95a2bcd4554d3d86c30d506f2b Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Dec 23 10:16:43 2016 -0500 payloads/depthcharge: Use variable target name Depending on the commit to build, depthcharge may have a different target name (depthcharge vs. depthcharge_unified). Add some logic to determine which name should be used based on the commit ID being requested. Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- payloads/external/depthcharge/Makefile | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index fb0c75b..89db111 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -14,6 +14,11 @@ VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot) TAG-$(DEPTHCHARGE_MASTER)=origin/master TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID) +# todo: consider reverting this once stable moves past the commit below +payload_target=depthcharge +payload_target_old=$(payload_target)_unified +payload_namechange=74a07395eb9976747055b4ac7a0ae7dcb603a6f4 + unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG unexport KCONFIG_DEPENDENCIES @@ -60,8 +65,12 @@ config: $(libpayload_install_dir) checkout build: config echo " MAKE $(project_name) $(TAG-y)" - cd $(project_dir) && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ - VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" depthcharge + cd $(project_dir) && \ + git merge-base --is-ancestor $(payload_namechange) $(TAG-y) >/dev/null 2>&1 && \ + $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ + VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" $(payload_target) || \ + $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ + VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" $(payload_target_old) clean: test -d $(output_dir) && rm -rf $(output_dir) || exit 0

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Patch merged into coreboot/master: payloads/depthcharge: Change make target from unified
by gerrit＠coreboot.org 01 Feb '17

01 Feb '17

the following patch was just integrated into master: commit 9e33e27a461e245a48208f57d93da7c23d1dbe33 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Dec 14 15:14:51 2016 -0500 payloads/depthcharge: Change make target from unified Drop the _unified moniker from the depthcharge build. The payload and coreboot have drifted out of sync and there is no longer a non-unified depthcharge. This patch corresponds with the depthcharge change: https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739 Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/18268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18268 for details. -gerrit

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Patch set updated for coreboot: payloads/depthcharge: Allow generic libpayload config
by Marshall Dawson 01 Feb '17

01 Feb '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18271 -gerrit commit f8cb8e01292d1070f044d4e485d6cf8627345431 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Dec 22 20:25:29 2016 -0500 payloads/depthcharge: Allow generic libpayload config Change depthcharge to not require a board-specific config file for libpayload. If the Kconfig option is selected, use the settings in libpayload/configs/defconfig instead. Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- payloads/external/Makefile.inc | 3 ++- payloads/external/depthcharge/Kconfig | 8 ++++++++ payloads/external/depthcharge/Makefile | 13 ++++++++++--- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index d09305c..c46ee58 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -108,7 +108,8 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \ DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \ DEPTHCHARGE_REVISION=$(CONFIG_DEPTHCHARGE_REVISION) \ - DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) + DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) \ + OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE) # FILO diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig index d6ce538..a913c7e 100644 --- a/payloads/external/depthcharge/Kconfig +++ b/payloads/external/depthcharge/Kconfig @@ -35,4 +35,12 @@ config PAYLOAD_FILE string default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" +config LP_DEFCONFIG_OVERRIDE + def_bool n + help + The Depthcharge makefile looks for a file config.<boardname> in the + libpayload/configs directory. Say Y here to use the file defconfig + instead. This is can be a convenience for development purposes, or + if the defaults in defconfig are sufficient for your system. + endif diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index 97d0950..f249a4a 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -30,6 +30,13 @@ unexport src srck obj objk BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR)) +ifeq ($(OVERRIDE_DEFCONFIG),y) +$(info Depthcharge: Using default defconfig for libpayload) +libpayload_config=$(libpayload_dir)/configs/defconfig +else +libpayload_config=$(libpayload_dir)/configs/config.$(BOARD) +endif + all: build $(project_dir): @@ -47,10 +54,10 @@ checkout: fetch cd $(project_dir) ; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) $(libpayload_install_dir): $(project_dir) - test -f $(libpayload_dir)/configs/config.$(BOARD) || \ - (echo "Error: $(libpayload_dir)/configs/config.$(BOARD) is not present" && \ + test -f $(libpayload_config)|| \ + (echo "Error: $(libpayload_config) is not present" && \ false) - cp $(libpayload_dir)/configs/config.$(BOARD) $(libpayload_dir)/.config + cp $(libpayload_config) $(libpayload_dir)/.config $(MAKE) -C $(libpayload_dir) olddefconfig $(MAKE) -C $(libpayload_dir) $(MAKE) -C $(libpayload_dir) install DESTDIR=$(libpayload_install_dir)

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Patch set updated for coreboot: payloads/depthcharge: Specify revision to build
by Marshall Dawson 01 Feb '17

01 Feb '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18270 -gerrit commit 03211e2ab9edfd902889c849111c7087d24fb4af Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Dec 22 18:16:48 2016 -0500 payloads/depthcharge: Specify revision to build Add the capability for specifying which version of depthcharge to checkout and build. This is similar to the existing feature for SeaBIOS. The depthcharge makefile already contains some structure for checking out master vs. stable however the calling Makefile.inc ingored this feature. Add the command-line variable assignment for these, along with a tree-ish for any revision. Change-Id: I99a5b088cb0ebb29e5d96a84217b3bfa852de8ac Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- payloads/external/Makefile.inc | 7 +++++-- payloads/external/depthcharge/Kconfig | 31 +++++++++++++++++++++++++++++++ payloads/external/depthcharge/Makefile | 1 + 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 29163d0..d09305c 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -102,10 +102,13 @@ endif # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) - $(MAKE) -C payloads/external/depthcharge \ BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) \ - MFLAGS= MAKEFLAGS= + MFLAGS= MAKEFLAGS= \ + DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \ + DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \ + DEPTHCHARGE_REVISION=$(CONFIG_DEPTHCHARGE_REVISION) \ + DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) # FILO diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig index 84b36e5..d6ce538 100644 --- a/payloads/external/depthcharge/Kconfig +++ b/payloads/external/depthcharge/Kconfig @@ -1,5 +1,36 @@ if PAYLOAD_DEPTHCHARGE +choice +prompt "Depthcharge version" + +config DEPTHCHARGE_STABLE + bool "stable" + help + Latest stable version. + +config DEPTHCHARGE_MASTER + bool "master" + help + Newest Depthcharge version. + +config DEPTHCHARGE_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch that + you want to use as the revision from which to build Depthcharge. + + You will be able to specify the name of a branch or a commit SHA + later. + +endchoice + +config DEPTHCHARGE_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on DEPTHCHARGE_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + config PAYLOAD_FILE string default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf" diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index 89db111..97d0950 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -13,6 +13,7 @@ VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot) TAG-$(DEPTHCHARGE_MASTER)=origin/master TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID) +TAG-$(DEPTHCHARGE_REVISION)=$(DEPTHCHARGE_REVISION_ID) # todo: consider reverting this once stable moves past the commit below payload_target=depthcharge

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Patch set updated for coreboot: payloads/depthcharge: Use variable target name
by Marshall Dawson 01 Feb '17

01 Feb '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18269 -gerrit commit 8f08c5b7997b65a029a68dbb7df962035939a410 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Dec 23 10:16:43 2016 -0500 payloads/depthcharge: Use variable target name Depending on the commit to build, depthcharge may have a different target name (depthcharge vs. depthcharge_unified). Add some logic to determine which name should be used based on the commit ID being requested. Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- payloads/external/depthcharge/Makefile | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index fb0c75b..89db111 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -14,6 +14,11 @@ VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot) TAG-$(DEPTHCHARGE_MASTER)=origin/master TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID) +# todo: consider reverting this once stable moves past the commit below +payload_target=depthcharge +payload_target_old=$(payload_target)_unified +payload_namechange=74a07395eb9976747055b4ac7a0ae7dcb603a6f4 + unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG unexport KCONFIG_DEPENDENCIES @@ -60,8 +65,12 @@ config: $(libpayload_install_dir) checkout build: config echo " MAKE $(project_name) $(TAG-y)" - cd $(project_dir) && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ - VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" depthcharge + cd $(project_dir) && \ + git merge-base --is-ancestor $(payload_namechange) $(TAG-y) >/dev/null 2>&1 && \ + $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ + VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" $(payload_target) || \ + $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ + VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" $(payload_target_old) clean: test -d $(output_dir) && rm -rf $(output_dir) || exit 0

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Patch set updated for coreboot: payloads/depthcharge: Change make target from unified
by Marshall Dawson 01 Feb '17

01 Feb '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18268 -gerrit commit efcc45d3785b5e0e6026b29517e7e1c78609adc9 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Dec 14 15:14:51 2016 -0500 payloads/depthcharge: Change make target from unified Drop the _unified moniker from the depthcharge build. The payload and coreboot have drifted out of sync and there is no longer a non-unified depthcharge. This patch corresponds with the depthcharge change: https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739 Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- payloads/external/depthcharge/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index edc48f8..fb0c75b 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -61,7 +61,7 @@ config: $(libpayload_install_dir) checkout build: config echo " MAKE $(project_name) $(TAG-y)" cd $(project_dir) && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \ - VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" depthcharge_unified + VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" depthcharge clean: test -d $(output_dir) && rm -rf $(output_dir) || exit 0

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New patch to review for coreboot: Kabylake: [WIP] Save Memory Info HOB data in SMBIOS Table
by Barnali Sarkar 01 Feb '17

01 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18275 -gerrit commit 1164fb2c5f6dfa7fd6cce6e9ee0f1c13229d5163 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 1 16:25:04 2017 +0530 Kabylake: [WIP] Save Memory Info HOB data in SMBIOS Table Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save in cbmem. Add the MemInfoHob.h provided by FSP for aid in parsing the HOB. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/include/fsp20/soc/romstage.h | 5 + src/soc/intel/skylake/romstage/romstage_fsp20.c | 86 ++++++- .../intel/fsp/fsp2_0/skykabylake/MemInfoHob.h | 254 +++++++++++++++++++++ 3 files changed, 344 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 41658e1..3db3a53 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -20,11 +20,16 @@ #include <arch/cpu.h> #include <fsp/api.h> +#pragma pack(push) +#include <MemInfoHob.h> +#pragma pack(pop) + asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void save_dimm_info(void); /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index e478890..175b386 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -26,10 +26,13 @@ #include <device/pci_def.h> #include <fsp/util.h> #include <fsp/memmap.h> +#include <memory_info.h> +#include <smbios.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> @@ -56,7 +59,7 @@ asmlinkage void *car_stage_c_entry(void) s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - + save_dimm_info(); if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -187,3 +190,84 @@ __attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < ctrlr_info->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &ctrlr_info->Channel[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + src_dimm = &channel_info->Dimm[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->DimmCapacity) + continue; + + /* Populate the DIMM information */ + dest_dimm->dimm_size = src_dimm->DimmCapacity; + dest_dimm->ddr_type = memory_info_hob->DdrType; + dest_dimm->ddr_frequency = + memory_info_hob->Frequency; + dest_dimm->channel_num = channel_info->ChannelId; + dest_dimm->dimm_num = src_dimm->DimmId; + strncpy((char *)dest_dimm->module_part_number, + (char *)src_dimm->ModulePartNum, + sizeof(dest_dimm->module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + case 128: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_128; + break; + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h new file mode 100644 index 0000000..bdaf39b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h @@ -0,0 +1,254 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + INTEL CONFIDENTIAL + Copyright 1999 - 2016 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT32 Frequency; ///< The system's common memory controller frequency in MT/s. + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + UINT32 FreqMax; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/// +/// Memory Platform Data Hob +/// +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_

1 0

Patch set updated for coreboot: siemens/mc_apl1: Add new mainboard
by Mario Scheithauer 01 Feb '17

01 Feb '17

Mario Scheithauer (mario.scheithauer(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18272 -gerrit commit d359b297e17a1ecf1be8395b3f93d69ed561495b Author: Mario Scheithauer <mario.scheithauer(a)siemens.com> Date: Tue Jan 31 15:45:13 2017 +0100 siemens/mc_apl1: Add new mainboard This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- src/mainboard/siemens/mc_apl1/Kconfig | 17 ++ src/mainboard/siemens/mc_apl1/Kconfig.name | 2 + src/mainboard/siemens/mc_apl1/Makefile.inc | 3 + src/mainboard/siemens/mc_apl1/acpi_tables.c | 3 + src/mainboard/siemens/mc_apl1/board_info.txt | 4 + src/mainboard/siemens/mc_apl1/bootblock.c | 22 +++ src/mainboard/siemens/mc_apl1/brd_gpio.h | 62 ++++++++ src/mainboard/siemens/mc_apl1/devicetree.cb | 226 +++++++++++++++++++++++++++ src/mainboard/siemens/mc_apl1/dsdt.asl | 42 +++++ src/mainboard/siemens/mc_apl1/mainboard.c | 25 +++ src/mainboard/siemens/mc_apl1/mc_apl1.fmd | 40 +++++ src/mainboard/siemens/mc_apl1/romstage.c | 119 ++++++++++++++ 12 files changed, 565 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig new file mode 100644 index 0000000..6201ed3 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -0,0 +1,17 @@ +if BOARD_SIEMENS_MC_APL1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default siemens/mc_apl1 + +config MAINBOARD_PART_NUMBER + string + default "MC APL1" + +endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name new file mode 100644 index 0000000..bbc2a82 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIEMENS_MC_APL1 + bool "MC APL1" diff --git a/src/mainboard/siemens/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/Makefile.inc new file mode 100644 index 0000000..9e3e892 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/acpi_tables.c b/src/mainboard/siemens/mc_apl1/acpi_tables.c new file mode 100644 index 0000000..e06f6a6 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/acpi_tables.c @@ -0,0 +1,3 @@ +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/siemens/mc_apl1/board_info.txt b/src/mainboard/siemens/mc_apl1/board_info.txt new file mode 100644 index 0000000..01963ec --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/board_info.txt @@ -0,0 +1,4 @@ +Board name: MC APL1 +Category: misc +ROM protocol: SPI +ROM socketed: no diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c new file mode 100644 index 0000000..3de44a8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/lpc.h> + +void bootblock_mainboard_init(void) +{ + lpc_configure_pads(); +} diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h new file mode 100644 index 0000000..33b839b --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb new file mode 100644 index 0000000..ce01a8b --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -0,0 +1,226 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_122" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C0 for audio codec at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }" + + # Enable I2C2 bus early for TPM at 400kHz + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 57, + .fall_time_ns = 28, + }" + + # touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }" + + # trackpad at 400kHz + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 114, + .fall_time_ns = 164, + }" + + # digitizer at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on + chip drivers/i2c/wacom + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_DT_DESC, + .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl new file mode 100644 index 0000000..004523a --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c new file mode 100644 index 0000000..f7a2ef1 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + /* Nothing Here Yet */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd new file mode 100644 index 0000000..3da8467 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + WP_RO@0x0 0x400000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x1ff000 + RO_VPD@0x200000 0x4000 + RO_SECTION@0x204000 0x1fc000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x1bb000 + RO_UNUSED@0x1bc000 0x40000 + } + } + MISC_RW@0x400000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c new file mode 100644 index 0000000..5c784ba --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + memupd->FspmConfig.Package = 0x1; + memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LASR = 0x0; + memupd->FspmConfig.ScramblerSupport = 0x1; + memupd->FspmConfig.ChannelHashMask = 0x36; + memupd->FspmConfig.SliceHashMask = 0x9; + memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ChannelsSlicesEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.RmtMode = 0x0; + memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.LowMemoryMaxValue = 0x0; + memupd->FspmConfig.DisableFastBoot = 0x0; + memupd->FspmConfig.HighMemoryMaxValue = 0x0; + memupd->FspmConfig.DIMM0SPDAddress = 0x0; + memupd->FspmConfig.DIMM1SPDAddress = 0x0; + memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; + memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_Option = 0x3; + memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_TristateClk1 = 0x0; + memupd->FspmConfig.Ch0_Mode2N = 0x0; + memupd->FspmConfig.Ch0_OdtLevels = 0x0; + memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; + memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_Option = 0x3; + memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_TristateClk1 = 0x0; + memupd->FspmConfig.Ch1_Mode2N = 0x0; + memupd->FspmConfig.Ch1_OdtLevels = 0x0; + memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; + memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_Option = 0x3; + memupd->FspmConfig.Ch2_OdtConfig = 0x0; + memupd->FspmConfig.Ch2_TristateClk1 = 0x0; + memupd->FspmConfig.Ch2_Mode2N = 0x0; + memupd->FspmConfig.Ch2_OdtLevels = 0x0; + memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; + memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_Option = 0x3; + memupd->FspmConfig.Ch3_OdtConfig = 0x0; + memupd->FspmConfig.Ch3_TristateClk1 = 0x0; + memupd->FspmConfig.Ch3_Mode2N = 0x0; + memupd->FspmConfig.Ch3_OdtLevels = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.MrcDataSaving = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x0; + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; +}

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coreboot-gerrit February 2017