coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Kabylake: [WIP] Save Memory Info HOB data in SMBIOS Table
by Barnali Sarkar 02 Feb '17

02 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18275 -gerrit commit 58f94a2222af16422dc4edeff7f38d3aeaad73e2 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 1 16:25:04 2017 +0530 Kabylake: [WIP] Save Memory Info HOB data in SMBIOS Table Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save in cbmem. Add the MemInfoHob.h provided by FSP for aid in parsing the HOB. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/include/fsp20/soc/romstage.h | 5 + src/soc/intel/skylake/romstage/romstage_fsp20.c | 86 ++++++- .../intel/fsp/fsp2_0/skykabylake/MemInfoHob.h | 249 +++++++++++++++++++++ 3 files changed, 339 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 41658e1..3db3a53 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -20,11 +20,16 @@ #include <arch/cpu.h> #include <fsp/api.h> +#pragma pack(push) +#include <MemInfoHob.h> +#pragma pack(pop) + asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void save_dimm_info(void); /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index e478890..175b386 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -26,10 +26,13 @@ #include <device/pci_def.h> #include <fsp/util.h> #include <fsp/memmap.h> +#include <memory_info.h> +#include <smbios.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> @@ -56,7 +59,7 @@ asmlinkage void *car_stage_c_entry(void) s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - + save_dimm_info(); if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -187,3 +190,84 @@ __attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < ctrlr_info->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &ctrlr_info->Channel[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + src_dimm = &channel_info->Dimm[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->DimmCapacity) + continue; + + /* Populate the DIMM information */ + dest_dimm->dimm_size = src_dimm->DimmCapacity; + dest_dimm->ddr_type = memory_info_hob->DdrType; + dest_dimm->ddr_frequency = + memory_info_hob->Frequency; + dest_dimm->channel_num = channel_info->ChannelId; + dest_dimm->dimm_num = src_dimm->DimmId; + strncpy((char *)dest_dimm->module_part_number, + (char *)src_dimm->ModulePartNum, + sizeof(dest_dimm->module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + case 128: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_128; + break; + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h new file mode 100644 index 0000000..88bb681 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h @@ -0,0 +1,249 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT32 Frequency; ///< The system's common memory controller frequency in MT/s. + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + UINT32 FreqMax; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/// +/// Memory Platform Data Hob +/// +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_

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Patch set updated for coreboot: google/poppy: Set GPIO GPP_D22 high
by Rizwan Qureshi 02 Feb '17

02 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18282 -gerrit commit ab08546877c50872fc0b049b3e6eec25f893cc30 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 2 12:23:37 2017 +0530 google/poppy: Set GPIO GPP_D22 high This is a clone of Duncan's change for eve in https://review.coreboot.org/#/c/18281, same change is required for poppy board as well. BUG=None BRANCH=None TEST=play test sound in OS over internal speaker Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index 0a2544c..b3849f1 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -144,7 +144,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,

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New patch to review for coreboot: google/poppy: Set GPIO GPP_D22 high
by Rizwan Qureshi 02 Feb '17

02 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18282 -gerrit commit 8fb8002165d17765530ee703ae9ddd5f3b746b27 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 2 12:23:37 2017 +0530 google/poppy: Set GPIO GPP_D22 high This is a clone of Duncan's chnage for eve in https://review.coreboot.org/#/c/18281, same change is required for poppy board as well. BUG=None BRANCH=None TEST=play test sound in OS over internal speaker Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index 0a2544c..b3849f1 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -144,7 +144,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_CLK0 */ /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DMIC_DATA0 */ /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* MCLK */ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,

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Patch set updated for coreboot: google/eve: Set GPIO GPP_D22 high
by Rizwan Qureshi 02 Feb '17

02 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18281 -gerrit commit e94108dbb87a155ec9e97c53844e6904521c439b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:09:02 2017 -0800 google/eve: Set GPIO GPP_D22 high GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=chrome-os-partner:58666 TEST=play test sound in OS over internal speaker Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index e8d42f0..f5b09d9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -142,7 +142,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */

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Patch merged into coreboot/master: siemens/mc_apl1: Add new mainboard
by gerrit＠coreboot.org 02 Feb '17

02 Feb '17

the following patch was just integrated into master: commit 092db95742fe6e94b391d32d151868f70c5cab84 Author: Mario Scheithauer <mario.scheithauer(a)siemens.com> Date: Tue Jan 31 15:45:13 2017 +0100 siemens/mc_apl1: Add new mainboard This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Brenton Dong <brenton.m.dong(a)intel.com> See https://review.coreboot.org/18272 for details. -gerrit

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Patch set updated for coreboot: google/eve: Set GPIO GPP_D22 high
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18281 -gerrit commit de49956852d9b461ab1b334e1ecd0a913c529d07 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:09:02 2017 -0800 google/eve: Set GPIO GPP_D22 high GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=chrome-os-partner:58666 TEST=play test sound in OS over internal speaker Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index e8d42f0..f5b09d9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -142,7 +142,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */

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Patch set updated for coreboot: google/eve: Fix keyboard backlight enable in wake from G3
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18280 -gerrit commit 7899e4282bb10a104a237e56b117bc0bcde5bf87 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:10:10 2017 -0800 google/eve: Fix keyboard backlight enable in wake from G3 The WAK_STS bit is not set in a wake from G3, so the check for this bit needs to only be done when checking for a wake from S3. This change correctly enables the keyboard backlight in wake from G3 and only does not enable it during a wake from S3. BUG=chrome-os-partner:58666 TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard backlight turns on like it does when waking from S5. Also force enter hibernate with Alt+VolumeUp+H and then power back up and ensure that the keyboard backlight is enabled when booting. Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index baca9c8..872825f 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -34,7 +34,7 @@ void bootblock_mainboard_init(void) uint32_t pm1_sts = inl(ACPI_BASE_ADDRESS + PM1_STS); /* Turn on keyboard backlight to indicate we are booting */ - if ((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) != ACPI_S3)) + if (!((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) == ACPI_S3))) google_chromeec_kbbacklight(75); early_config_gpio();

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Patch set updated for coreboot: google/eve: Fix DRAM DQS map
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18279 -gerrit commit d81258e2cadeaacbea66004a74a679ee7f67b726 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Feb 1 16:37:29 2017 -0800 google/eve: Fix DRAM DQS map This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 4ae87fd..2378e90 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 1, 0, 2, 3, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 3, 2, 7, 6 } }; + { 1, 0, 5, 4, 2, 3, 7, 6 } }; /* Rcomp resistor */ const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */

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Patch set updated for coreboot: google/eve: Set GPIO GPP_D22 high
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18281 -gerrit commit 52cc076e87ae38866d5d7cdd57f7e4ba4e3ae055 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:09:02 2017 -0800 google/eve: Set GPIO GPP_D22 high GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=chrome-os-partner:58666 TEST=play test sound in OS over internal speaker Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index e8d42f0..f5b09d9 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -142,7 +142,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */

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Patch set updated for coreboot: google/eve: Fix keyboard backlight enable in wake from G3
by Duncan Laurie 02 Feb '17

02 Feb '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18280 -gerrit commit 18f9ba2dbc27dfbbac9e2a9faf6e45492e78bcac Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:10:10 2017 -0800 google/eve: Fix keyboard backlight enable in wake from G3 The WAK_STS bit is not set in a wake from G3, so the check for this bit needs to only be done when checking for a wake from S3. This change correctly enables the keyboard backlight in wake from G3 and only does not enable it during a wake from S3. BUG=chrome-os-partner:58666 TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard backlight turns on like it does when waking from S5. Also force enter hibernate with Alt+VolumeUp+H and then power back up and ensure that the keyboard backlight is enabled when booting. Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index baca9c8..872825f 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -34,7 +34,7 @@ void bootblock_mainboard_init(void) uint32_t pm1_sts = inl(ACPI_BASE_ADDRESS + PM1_STS); /* Turn on keyboard backlight to indicate we are booting */ - if ((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) != ACPI_S3)) + if (!((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) == ACPI_S3))) google_chromeec_kbbacklight(75); early_config_gpio();

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coreboot-gerrit February 2017