coreboot-gerrit February 2017

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Patch set updated for coreboot: nb/i945/gma.c: Refactor panel setup
by Arthur Heymans 04 Feb '17

04 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit 79eedc7019970cefae4e25fe5cd61502d608ce16 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 nb/i945/gma.c: Refactor panel setup This reuses some of gm45 code to set up panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. TESTED on Lenovo Thinkpad X60 Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/i915_reg.h | 2 +- src/mainboard/apple/macbook21/devicetree.cb | 7 ++- src/mainboard/lenovo/t60/devicetree.cb | 7 ++- src/mainboard/lenovo/x60/devicetree.cb | 7 ++- src/northbridge/intel/gm45/gma.c | 8 +-- src/northbridge/intel/i945/chip.h | 10 +++- src/northbridge/intel/i945/gma.c | 78 +++++++++++++++++++++++++---- 7 files changed, 99 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..dee6865 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -62,7 +62,7 @@ #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..b6e61eb 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..6ad054c 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "275" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..28b63d3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4886bb2..cbb8451 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -203,8 +203,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * pixel_p2))); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) @@ -479,8 +479,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * pixel_p2))); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); mdelay(1); write32(mmio + FP0(0), (pixel_n << 16) diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..716e291 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,16 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + /* In units of 100us timer */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + /* In units of 0.1s based on unit of the reference divider.*/ + u8 gpu_panel_power_cycle_delay; + u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..3807cce 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -292,17 +292,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(pmmio + DSPPOS(0), 0); - /* Backlight init. */ - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC, 0x011d011a); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC_SELF, 0x0001003f); - write32(pmmio + FW_BLC, 0x011d0109); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(pmmio + DSPADDR(0), 0); write32(pmmio + DSPSURF(0), 0); @@ -579,6 +568,68 @@ static int probe_edid(u8 *pmmio, u8 slave) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + u16 gcfgc = pci_read_config16(dev, GCFGC); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) + return 133333333; + else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_320_MHZ: + return 320000000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 200000000; + } + } +} + +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + /* Set duty cycle to 100% due to use of legacy backlight control */ + blc_mod = get_cdclk(dev) / (32 * pwm_freq); + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(void *mmio, struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Setup Panel Power On Delays */ + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + write32(mmio + PP_ON_DELAYS, reg32); + + /* Setup Panel Power Off Delays */ + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + write32(mmio + PP_OFF_DELAYS, reg32); + + /* Setup Panel Power Cycle Delay */ + reg32 = (get_cdclk(dev) / 20000 - 1) << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + write32(mmio + PP_DIVISOR, reg32); + + /* Backlight init. */ + write32(mmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(mmio + FW_BLC, 0x011d011a); + write32(mmio + FW_BLC2, 0x00000102); + write32(mmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(mmio + FW_BLC_SELF, 0x0001003f); + write32(mmio + FW_BLC, 0x011d0109); + write32(mmio + FW_BLC2, 0x00000102); + write32(mmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + if (conf->pwm_freq) + write32(mmio + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); +} static void gma_func0_init(struct device *dev) { @@ -596,6 +647,7 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); @@ -623,6 +675,10 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + panel_setup(mmiobase, dev); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

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Patch set updated for coreboot: Revert "google/pyro: remove Wacom touchscreen probed flag"
by Kevin Chiu 03 Feb '17

03 Feb '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18291 -gerrit commit effad20eebe3a74579e201d64342f225a2d1a239 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Sat Feb 4 03:55:01 2017 +0800 Revert "google/pyro: remove Wacom touchscreen probed flag" Reason for revert: Pyro has two touchscreen sources: WACOM/ELAN. It will not have both touchscreen IC in one system at the same time. So the "probed" property of WACOM i2c device is mandatory to set for kernel to know whether it exists before driver initializes it. Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF will be invoked to set GPIO#152 low to cut off power. BUG=chrome-os-partner:62371 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 72ad57c..c36d19d 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -187,6 +187,7 @@ chip soc/intel/apollolake .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), + .probed = 1, .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), .reset_delay_ms = 20, .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152),

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New patch to review for coreboot: Revert "google/pyro: remove Wacom touchscreen probed flag"
by Kevin Chiu 03 Feb '17

03 Feb '17

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18291 -gerrit commit 88c47fb7a283fc717f7c69911a090887be6f9f93 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Sat Feb 4 03:55:01 2017 +0800 Revert "google/pyro: remove Wacom touchscreen probed flag" This reverts commit 1099c665091b64bff3c01234826e8c7640a7b8f6 Reason for revert: Pyro has two touchscreen sources: WACOM/ELAN. It will not have both touchscreen IC in one system at the same time. So the "probed" property of WACOM i2c device is mandatory to set for kernel to know whether it exists before driver initializes it. Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF will be invoked to set GPIO#152 low to cut off power. BUG=chrome-os-partner:62371 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- src/mainboard/google/reef/variants/pyro/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 72ad57c..c36d19d 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -187,6 +187,7 @@ chip soc/intel/apollolake .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), + .probed = 1, .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), .reset_delay_ms = 20, .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152),

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Patch set updated for coreboot: Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented
by Arthur Heymans 03 Feb '17

03 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18232 -gerrit commit 02082f264efaa87aa71d69be5444c0e48e320e12 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Jan 25 15:27:52 2017 +0100 Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented This also selects RELOCATABLE_RAMSTAGE and CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell. Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/Kconfig | 2 +- src/northbridge/intel/haswell/Kconfig | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 436964c..581c36b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -244,7 +244,7 @@ config RELOCATABLE_RAMSTAGE config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM depends on RELOCATABLE_RAMSTAGE - bool "Cache the relocated ramstage outside of cbmem." + bool default n help The relocated ramstage is saved in an area specified by the diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 4fc117d..e9a93ba 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -20,6 +20,8 @@ config NORTHBRIDGE_INTEL_HASWELL select INTEL_DDI select INTEL_DP select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if NORTHBRIDGE_INTEL_HASWELL

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Patch set updated for coreboot: mb/apple/macbook21: Remove unused cmos parameters
by Arthur Heymans 03 Feb '17

03 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18290 -gerrit commit 312b13652c96aeb43d260eb82bad5384f25a2146 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 3 17:30:35 2017 +0100 mb/apple/macbook21: Remove unused cmos parameters These parameters are probably the result of copying from the Thinkpad X60 code. Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/cmos.default | 10 ---------- src/mainboard/apple/macbook21/cmos.layout | 10 ---------- 2 files changed, 20 deletions(-) diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 1cf350c..e9844fc 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -7,14 +7,4 @@ boot_devices='' boot_default=0x40 cmos_defaults_loaded=Yes lpt=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wlan=Enable -wwan=Enable -trackpoint=Enable -fn_ctrl_swap=Disable -sticky_fn=Disable -power_management_beeps=Enable -low_battery_beep=Enable gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 8329347..78d4702 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -81,16 +81,6 @@ entries 1048 4 r 0 C0DRT1 1052 4 r 0 C1DRT1 -1064 8 h 0 volume -1080 1 e 9 first_battery -1081 1 e 1 bluetooth -1082 1 e 1 wwan -1083 1 e 1 wlan -1084 1 e 1 trackpoint -1085 1 e 1 fn_ctrl_swap -1086 1 e 1 sticky_fn -1087 1 e 1 power_management_beeps -1088 1 e 1 low_battery_beep # ----------------------------------------------------------------- enumerations

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Patch set updated for coreboot: nb/i945/gma.c: Refactor panel setup
by Arthur Heymans 03 Feb '17

03 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit e5c4d228dabcd53684f6f7d7a46e8faddee6be12 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 nb/i945/gma.c: Refactor panel setup This reuses gm45 code to set up panel. Panel start and stop delays and pwm frequency can now be set in devicetree. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios intended to do on Thinkpad X60 and T60. TESTED on Lenovo Thinkpad X60 Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/i915_reg.h | 2 +- src/mainboard/apple/macbook21/devicetree.cb | 7 +- src/mainboard/lenovo/t60/devicetree.cb | 7 +- src/mainboard/lenovo/x60/devicetree.cb | 7 +- src/northbridge/intel/i945/chip.h | 7 +- src/northbridge/intel/i945/gma.c | 104 +++++++++++++++++++++++++--- 6 files changed, 118 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..dee6865 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -62,7 +62,7 @@ #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..b6e61eb 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..8341fe9 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "261" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..4296405 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "171" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..5bbda81 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,13 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..828fd5d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -46,6 +46,19 @@ #define PGETBL_ENABLED 0x00000001 #define BASE_FREQUENCY 100000 +#define DEFAULT_PWM 1000 + +static struct resource *gtt_res = NULL; + +u32 gtt_read(u32 reg) +{ + return read32(res2mmio(gtt_res, reg, 0)); +} + +void gtt_write(u32 reg, u32 data) +{ + write32(res2mmio(gtt_res, reg, 0), data); +} static int gtt_setup(void *mmiobase) { @@ -292,17 +305,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(pmmio + DSPPOS(0), 0); - /* Backlight init. */ - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC, 0x011d011a); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC_SELF, 0x0001003f); - write32(pmmio + FW_BLC, 0x011d0109); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(pmmio + DSPADDR(0), 0); write32(pmmio + DSPSURF(0), 0); @@ -579,6 +581,80 @@ static int probe_edid(u8 *pmmio, u8 slave) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + u16 gcfgc = pci_read_config16(dev, GCFGC); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) + return 133333333; + else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_320_MHZ: + return 320000000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 200000000; + } + } +} + +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + /* Set duty cycle to 100% due to use of legacy backlight control */ + blc_mod = get_cdclk(dev) / (32 * pwm_freq); + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(PP_ON_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(PP_ON_DELAYS, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(PP_OFF_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(PP_OFF_DELAYS, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = (get_cdclk(dev) / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + gtt_write(PP_DIVISOR, reg32); + } + + /* Backlight init. */ + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC, 0x011d011a); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + gtt_write(FW_BLC_SELF, 0x0001003f); + gtt_write(FW_BLC, 0x011d0109); + gtt_write(FW_BLC2, 0x00000102); + gtt_write(FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + if (conf->pwm_freq == 0) { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, DEFAULT_PWM)); + } else { + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); + } +} static void gma_func0_init(struct device *dev) { @@ -596,6 +672,8 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); @@ -623,6 +701,10 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + panel_setup(dev); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

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New patch to review for coreboot: mb/apple/macbook21: Remove unused cmos parameters
by Arthur Heymans 03 Feb '17

03 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18290 -gerrit commit f5049f960a8c2b9f1e2f45fd3181cb5e05ba8a6a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 3 17:30:35 2017 +0100 mb/apple/macbook21: Remove unused cmos parameters These parameters are probably the result from copying from the Thinkpad X60 code. Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/cmos.default | 10 ---------- src/mainboard/apple/macbook21/cmos.layout | 10 ---------- 2 files changed, 20 deletions(-) diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 1cf350c..e9844fc 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -7,14 +7,4 @@ boot_devices='' boot_default=0x40 cmos_defaults_loaded=Yes lpt=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wlan=Enable -wwan=Enable -trackpoint=Enable -fn_ctrl_swap=Disable -sticky_fn=Disable -power_management_beeps=Enable -low_battery_beep=Enable gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 8329347..78d4702 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -81,16 +81,6 @@ entries 1048 4 r 0 C0DRT1 1052 4 r 0 C1DRT1 -1064 8 h 0 volume -1080 1 e 9 first_battery -1081 1 e 1 bluetooth -1082 1 e 1 wwan -1083 1 e 1 wlan -1084 1 e 1 trackpoint -1085 1 e 1 fn_ctrl_swap -1086 1 e 1 sticky_fn -1087 1 e 1 power_management_beeps -1088 1 e 1 low_battery_beep # ----------------------------------------------------------------- enumerations

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Patch set updated for coreboot: src/Kconfig: Remove 'default n' statements from early in Kconfig
by Martin Roth 03 Feb '17

03 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17908 -gerrit commit cf08fdc64c79979affaa46e0e1eb6b0d3b1e7ee9 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:35:12 2016 -0700 src/Kconfig: Remove 'default n' statements from early in Kconfig For boolean types, 'n' is the default default value - it doesn't NEED to be set. If it IS set, it prevents a later default from being set. So by removing the 'default n' statements from the early symbols, they can be overridden other places in the tree. Verified that this makes no significant changes to any config file. Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7e473f3..69c8291 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -111,7 +111,6 @@ config SCONFIG_GENPARSER config USE_OPTION_TABLE bool "Use CMOS for configuration values" - default n depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" @@ -119,7 +118,6 @@ config USE_OPTION_TABLE config STATIC_OPTION_TABLE bool "Load default configuration values into CMOS on each boot" - default n depends on USE_OPTION_TABLE help Enable this option to reset "CMOS" NVRAM values to default on @@ -179,14 +177,12 @@ config INCLUDE_CONFIG_FILE config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. config USE_BLOBS bool "Allow use of binary-only repository" - default n help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. @@ -195,7 +191,6 @@ config USE_BLOBS config COVERAGE bool "Code coverage support" depends on COMPILER_GCC - default n help Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. @@ -204,7 +199,6 @@ config COVERAGE config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." - default n select RELOCATABLE_MODULES help The reloctable ramstage support allows for the ramstage to be built @@ -216,7 +210,6 @@ config RELOCATABLE_RAMSTAGE config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM depends on RELOCATABLE_RAMSTAGE bool "Cache the relocated ramstage outside of cbmem." - default n help The relocated ramstage is saved in an area specified by the by the board and/or chipset. @@ -241,7 +234,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" - default n depends on BOOTBLOCK_NORMAL help Do not clear the reboot count immediately after successful boot. @@ -251,7 +243,6 @@ config SKIP_MAX_REBOOT_CNT_CLEAR config UPDATE_IMAGE bool "Update existing coreboot.rom image" - default n help If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already @@ -270,7 +261,6 @@ config BOARD_ID_STRING config RAM_CODE_SUPPORT bool - default n help If enabled, coreboot discovers RAM configuration (value obtained by reading board straps) and stores it in coreboot table.

1 0

Patch set updated for coreboot: src/Kconfig: Move options with no prompt towards the end of the file
by Martin Roth 03 Feb '17

03 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17907 -gerrit commit 95008cbfeb8d7089c097bca52f8e6f7aa7be0f8e Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:25:15 2016 -0700 src/Kconfig: Move options with no prompt towards the end of the file Options with no prompt can go anywhere in the tree with the same dependencies and they have the same effect. Moving them lower in the tree allows the default values to be overridden by other Kconfig files. This patch just moves options with default values that aren't 'n'. The 'n' options are just removed in the next patch, since they aren't needed. Verified that this makes no significant changes to any config file. Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 192 +++++++++++++++++++++++++++++------------------------------- 1 file changed, 94 insertions(+), 98 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f6c3ff7..7e473f3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -126,10 +126,6 @@ config STATIC_OPTION_TABLE every boot. Use this if you want the NVRAM configuration to never be modified from its default values. -config UNCOMPRESSED_RAMSTAGE - bool - default n - config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" # Default value set at the end of the file @@ -181,22 +177,6 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 -config NO_XIP_EARLY_STAGES - bool - default n if ARCH_X86 - default y - help - Identify if early stages are eXecute-In-Place(XIP). - -config EARLY_CBMEM_INIT - def_bool !LATE_CBMEM_INIT - -config EARLY_CBMEM_LIST - bool - default n - help - Enable display of CBMEM during romstage and postcar. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -221,14 +201,6 @@ config COVERAGE coverage information in CBMEM for extraction from user space. If unsure, say N. -config RELOCATABLE_MODULES - bool - default n - help - If RELOCATABLE_MODULES is selected then support is enabled for - building relocatable modules in the RAM stage. Those modules can be - loaded anywhere and all the relocations are handled automatically. - config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." @@ -249,13 +221,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -config NO_STAGE_CACHE - bool - default n - help - Do not save any component in stage cache for resume path. On resume, - all components would be read back from CBFS again. - # TODO: This doesn't belong here, move to src/arch/x86/Kconfig choice prompt "Bootblock behaviour" @@ -269,23 +234,11 @@ config BOOTBLOCK_NORMAL endchoice -# To be selected by arch, SoC or mainboard if it does not want use the normal -# src/lib/bootblock.c#main() C entry point. -config BOOTBLOCK_CUSTOM - bool - default n - config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL -# To be selected by arch or platform if a C environment is available during the -# bootblock. Normally this signifies availability of RW memory (e.g. SRAM). -config C_ENVIRONMENT_BOOTBLOCK - bool - default n - config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n @@ -307,56 +260,6 @@ config UPDATE_IMAGE If unsure, select 'N' -config GENERIC_GPIO_LIB - bool - default n - help - If enabled, compile the generic GPIO library. A "generic" GPIO - implies configurability usually found on SoCs, particularly the - ability to control internal pull resistors. - -config GENERIC_SPD_BIN - bool - default n - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - depends on GENERIC_SPD_BIN - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - depends on GENERIC_SPD_BIN - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config BOARD_ID_AUTO - bool - default n - help - Mainboards that can read a board ID from the hardware straps - (ie. GPIO) select this configuration option. - -config BOARD_ID_MANUAL - bool - default n - depends on !BOARD_ID_AUTO - help - If you want to maintain a board ID, but the hardware does not - have straps to automatically determine the ID, you can say Y - here and add a file named 'board_id' to CBFS. If you don't know - what this is about, say N. - config BOARD_ID_STRING string "Board ID" # Default value set at the end of the file @@ -1166,7 +1069,10 @@ config DEBUG_ADA_CODE endmenu -# These probably belong somewhere else, but they are needed somewhere. + +############################################################################### +# Set variables with no prompt - these can be set anywhere, and putting at +# the end of this file gives the most flexibility. config ENABLE_APIC_EXT_ID bool default n @@ -1272,6 +1178,96 @@ config RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y +config UNCOMPRESSED_RAMSTAGE + bool + +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + help + Identify if early stages are eXecute-In-Place(XIP). + +config EARLY_CBMEM_INIT + def_bool !LATE_CBMEM_INIT + +config EARLY_CBMEM_LIST + bool + default n + help + Enable display of CBMEM during romstage and postcar. + +config RELOCATABLE_MODULES + bool + help + If RELOCATABLE_MODULES is selected then support is enabled for + building relocatable modules in the RAM stage. Those modules can be + loaded anywhere and all the relocations are handled automatically. + +config NO_STAGE_CACHE + bool + help + Do not save any component in stage cache for resume path. On resume, + all components would be read back from CBFS again. + +config GENERIC_GPIO_LIB + bool + help + If enabled, compile the generic GPIO library. A "generic" GPIO + implies configurability usually found on SoCs, particularly the + ability to control internal pull resistors. + +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 4 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config BOARD_ID_AUTO + bool + default n + help + Mainboards that can read a board ID from the hardware straps + (ie. GPIO) select this configuration option. + +config BOARD_ID_MANUAL + bool + default n + depends on !BOARD_ID_AUTO + help + If you want to maintain a board ID, but the hardware does not + have straps to automatically determine the ID, you can say Y + here and add a file named 'board_id' to CBFS. If you don't know + what this is about, say N. + +config BOOTBLOCK_CUSTOM + # To be selected by arch, SoC or mainboard if it does not want use the normal + # src/lib/bootblock.c#main() C entry point. + bool + +config C_ENVIRONMENT_BOOTBLOCK + # To be selected by arch or platform if a C environment is available during the + # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). + bool + ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in

1 0

Patch set updated for coreboot: src/Kconfig: Move options with no prompt towards the end of the file
by Martin Roth 03 Feb '17

03 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17907 -gerrit commit 01308459c8ce9f9a0dd63c38a8f8ec11c329c04c Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:25:15 2016 -0700 src/Kconfig: Move options with no prompt towards the end of the file Options with no prompt can go anywhere in the tree with the same dependencies and they have the same effect. Moving them lower in the tree allows the default values to be overridden by other Kconfig files. This patch just moves options with default values. Options without default values are moved in a follow-on. Verified that this makes no significant changes to any config file. Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 192 +++++++++++++++++++++++++++++------------------------------- 1 file changed, 94 insertions(+), 98 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f6c3ff7..7e473f3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -126,10 +126,6 @@ config STATIC_OPTION_TABLE every boot. Use this if you want the NVRAM configuration to never be modified from its default values. -config UNCOMPRESSED_RAMSTAGE - bool - default n - config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" # Default value set at the end of the file @@ -181,22 +177,6 @@ config INCLUDE_CONFIG_FILE config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 -config NO_XIP_EARLY_STAGES - bool - default n if ARCH_X86 - default y - help - Identify if early stages are eXecute-In-Place(XIP). - -config EARLY_CBMEM_INIT - def_bool !LATE_CBMEM_INIT - -config EARLY_CBMEM_LIST - bool - default n - help - Enable display of CBMEM during romstage and postcar. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -221,14 +201,6 @@ config COVERAGE coverage information in CBMEM for extraction from user space. If unsure, say N. -config RELOCATABLE_MODULES - bool - default n - help - If RELOCATABLE_MODULES is selected then support is enabled for - building relocatable modules in the RAM stage. Those modules can be - loaded anywhere and all the relocations are handled automatically. - config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." @@ -249,13 +221,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -config NO_STAGE_CACHE - bool - default n - help - Do not save any component in stage cache for resume path. On resume, - all components would be read back from CBFS again. - # TODO: This doesn't belong here, move to src/arch/x86/Kconfig choice prompt "Bootblock behaviour" @@ -269,23 +234,11 @@ config BOOTBLOCK_NORMAL endchoice -# To be selected by arch, SoC or mainboard if it does not want use the normal -# src/lib/bootblock.c#main() C entry point. -config BOOTBLOCK_CUSTOM - bool - default n - config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if BOOTBLOCK_SIMPLE default "bootblock_normal.c" if BOOTBLOCK_NORMAL -# To be selected by arch or platform if a C environment is available during the -# bootblock. Normally this signifies availability of RW memory (e.g. SRAM). -config C_ENVIRONMENT_BOOTBLOCK - bool - default n - config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n @@ -307,56 +260,6 @@ config UPDATE_IMAGE If unsure, select 'N' -config GENERIC_GPIO_LIB - bool - default n - help - If enabled, compile the generic GPIO library. A "generic" GPIO - implies configurability usually found on SoCs, particularly the - ability to control internal pull resistors. - -config GENERIC_SPD_BIN - bool - default n - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - depends on GENERIC_SPD_BIN - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - depends on GENERIC_SPD_BIN - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config BOARD_ID_AUTO - bool - default n - help - Mainboards that can read a board ID from the hardware straps - (ie. GPIO) select this configuration option. - -config BOARD_ID_MANUAL - bool - default n - depends on !BOARD_ID_AUTO - help - If you want to maintain a board ID, but the hardware does not - have straps to automatically determine the ID, you can say Y - here and add a file named 'board_id' to CBFS. If you don't know - what this is about, say N. - config BOARD_ID_STRING string "Board ID" # Default value set at the end of the file @@ -1166,7 +1069,10 @@ config DEBUG_ADA_CODE endmenu -# These probably belong somewhere else, but they are needed somewhere. + +############################################################################### +# Set variables with no prompt - these can be set anywhere, and putting at +# the end of this file gives the most flexibility. config ENABLE_APIC_EXT_ID bool default n @@ -1272,6 +1178,96 @@ config RAMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y +config UNCOMPRESSED_RAMSTAGE + bool + +config NO_XIP_EARLY_STAGES + bool + default n if ARCH_X86 + default y + help + Identify if early stages are eXecute-In-Place(XIP). + +config EARLY_CBMEM_INIT + def_bool !LATE_CBMEM_INIT + +config EARLY_CBMEM_LIST + bool + default n + help + Enable display of CBMEM during romstage and postcar. + +config RELOCATABLE_MODULES + bool + help + If RELOCATABLE_MODULES is selected then support is enabled for + building relocatable modules in the RAM stage. Those modules can be + loaded anywhere and all the relocations are handled automatically. + +config NO_STAGE_CACHE + bool + help + Do not save any component in stage cache for resume path. On resume, + all components would be read back from CBFS again. + +config GENERIC_GPIO_LIB + bool + help + If enabled, compile the generic GPIO library. A "generic" GPIO + implies configurability usually found on SoCs, particularly the + ability to control internal pull resistors. + +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 4 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config BOARD_ID_AUTO + bool + default n + help + Mainboards that can read a board ID from the hardware straps + (ie. GPIO) select this configuration option. + +config BOARD_ID_MANUAL + bool + default n + depends on !BOARD_ID_AUTO + help + If you want to maintain a board ID, but the hardware does not + have straps to automatically determine the ID, you can say Y + here and add a file named 'board_id' to CBFS. If you don't know + what this is about, say N. + +config BOOTBLOCK_CUSTOM + # To be selected by arch, SoC or mainboard if it does not want use the normal + # src/lib/bootblock.c#main() C entry point. + bool + +config C_ENVIRONMENT_BOOTBLOCK + # To be selected by arch or platform if a C environment is available during the + # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). + bool + ############################################################################### # Set default values for symbols created before mainboards. This allows the # option to be displayed in the general menu, but the default to be loaded in

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coreboot-gerrit February 2017