coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: google/eve: Fix keyboard backlight enable in wake from G3
by gerrit＠coreboot.org 05 Feb '17

05 Feb '17

the following patch was just integrated into master: commit 649100ad202f681632c6c1a949cb65cbe3fca482 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 31 15:10:10 2017 -0800 google/eve: Fix keyboard backlight enable in wake from G3 The WAK_STS bit is not set in a wake from G3, so the check for this bit needs to only be done when checking for a wake from S3. This change correctly enables the keyboard backlight in wake from G3 and only does not enable it during a wake from S3. BUG=chrome-os-partner:58666 TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard backlight turns on like it does when waking from S5. Also force enter hibernate with Alt+VolumeUp+H and then power back up and ensure that the keyboard backlight is enabled when booting. Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18280 for details. -gerrit

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Patch set updated for coreboot: board-status/to-wiki: Add freedom level to table
by Timothy Pearson 04 Feb '17

04 Feb '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18169 -gerrit commit 0f03bc866471b0e69ffa806b78f890a2f095a6dd Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed Jan 18 16:13:18 2017 -0600 board-status/to-wiki: Add freedom level to table Add a freedom level column to the board-status table on the Wiki Change-Id: I88b04159cfe51fd056bfe9cdbf11af43c71374e4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- util/board_status/to-wiki/towiki.sh | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 8b2d1af..e9edd6f 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -56,7 +56,8 @@ cat <<EOF ! align="left" | P 2 ! align="left" | S 3 ! align="left" | F 4 -! align="left" | VCS5 +! align="left" | FL5 +! align="left" | VCS6 EOF for category in laptop server desktop half mini settop "eval" sbc emulation misc unclass; do @@ -173,6 +174,7 @@ EOF rom_protocol="$(sed -n "/^[[:space:]]*ROM protocol:/ s,^[[:space:]]*ROM protocol:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" rom_socketed="$(sed -n "/^[[:space:]]*ROM socketed:/ s,^[[:space:]]*ROM socketed:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" flashrom_support="$(sed -n "/^[[:space:]]*Flashrom support:/ s,^[[:space:]]*Flashrom support:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" + freedom_level="$(sed -n "/^[[:space:]]*Freedom level:/ s,^[[:space:]]*Freedom level:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" vendor_cooperation_score="$(sed -n "/^[[:space:]]*Vendor cooperation score:/ s,^[[:space:]]*Vendor cooperation score:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" vendor_cooperation_page="$(sed -n "/^[[:space:]]*Vendor cooperation page:/ s,^[[:space:]]*Vendor cooperation page:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" board_url="$(sed -n "/^[[:space:]]*Board URL:/ s,^[[:space:]]*Board URL:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" @@ -184,6 +186,7 @@ EOF rom_protocol= rom_socketed= flashrom_support= + freedom_level= vendor_cooperation_score= vendor_cooperation_page= board_url= @@ -457,7 +460,7 @@ EOF elif [ "$rom_socketed" = "n" ]; then echo "| style=\"background:red\" | N" elif [ "$flashrom_support" = "variable" ]; then - echo "| ...7" + echo "| ...8" elif [ "$rom_socketed" = "" ]; then echo "| ?" else @@ -468,12 +471,27 @@ EOF elif [ "$flashrom_support" = "n" ]; then echo "| style=\"background:red\" | N" elif [ "$flashrom_support" = "coreboot-only" ]; then - echo "| style=\"background:yellow\" | ...6" + echo "| style=\"background:yellow\" | ...7" elif [ "$flashrom_support" = "" ]; then echo "| ?" else echo "| $flashrom_support" fi + if [ "$freedom_level" = "platinum" ]; then + echo "| style=\"background:white\" | Platinum" + elif [ "$freedom_level" = "gold" ]; then + echo "| style=\"background:#ffd700\" | Gold" + elif [ "$freedom_level" = "silver" ]; then + echo "| style=\"background:#c0c0c0\" | Silver" + elif [ "$freedom_level" = "bronze" ]; then + echo "| style=\"background:#dca570\" | Bronze" + elif [ "$freedom_level" = "vendorlock" ]; then + echo "| style=\"background:red\" | Vendor Controlled" + elif [ "$freedom_level" = "" ]; then + echo "| ?" + else + echo "| $freedom_level" + fi if [ "$vendor_cooperation_score" = "4" ]; then echo -n "| style=\"background:lime\"" elif [ "$vendor_cooperatio_scoren" = "3" ]; then @@ -497,9 +515,10 @@ cat <<EOF 2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 3 ROM chip socketed (Y/N)? 4 Board supported by [http://www.flashrom.org flashrom] (Y/N)? -5 Vendor Cooperation Score. -6 [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot. -7 Some boards have ROM sockets, others are soldered. +5 [[Board_freedom_levels|Freedom Level]]. +6 Vendor Cooperation Score. +7 [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot. +8 Some boards have ROM sockets, others are soldered. EOF

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Patch set updated for coreboot: board-info: Add initial freedom levels for select boards
by Timothy Pearson 04 Feb '17

04 Feb '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18168 -gerrit commit da0753a7eb0ef3575b95ce51d459c50191c223e7 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed Jan 18 16:02:10 2017 -0600 board-info: Add initial freedom levels for select boards Coreboot supports a wide variety of hardware, some that allows fully libre fimware to be used, and some where coreboot is a simple shim on top of signed vendor-controlled firmware blobs. An initial ranking system has been created here: https://www.coreboot.org/Board_freedom_levels These mainboards have been ranked according to the criteria in that list. Change-Id: If694825a704ee8ac5d12aa023471c88d845f7a25 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/asus/kcma-d8/board_info.txt | 1 + src/mainboard/asus/kfsn4-dre/board_info.txt | 1 + src/mainboard/asus/kgpe-d16/board_info.txt | 1 + src/mainboard/google/slippy/board_info.txt | 1 + src/mainboard/google/veyron/board_info.txt | 1 + src/mainboard/lenovo/t400/board_info.txt | 1 + src/mainboard/lenovo/t500/board_info.txt | 1 + src/mainboard/lenovo/x200/board_info.txt | 1 + 8 files changed, 8 insertions(+) diff --git a/src/mainboard/asus/kcma-d8/board_info.txt b/src/mainboard/asus/kcma-d8/board_info.txt index e69d31a..0f0045d 100644 --- a/src/mainboard/asus/kcma-d8/board_info.txt +++ b/src/mainboard/asus/kcma-d8/board_info.txt @@ -3,3 +3,4 @@ ROM package: DIP-8 ROM protocol: SPI ROM socketed: y Flashrom support: y +Freedom level: gold diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt index 678373a..c3f32b5 100644 --- a/src/mainboard/asus/kfsn4-dre/board_info.txt +++ b/src/mainboard/asus/kfsn4-dre/board_info.txt @@ -3,4 +3,5 @@ ROM package: PLCC-32 ROM protocol: LPC ROM socketed: y Flashrom support: y +Freedom level: gold Release year: 2007 diff --git a/src/mainboard/asus/kgpe-d16/board_info.txt b/src/mainboard/asus/kgpe-d16/board_info.txt index e69d31a..0f0045d 100644 --- a/src/mainboard/asus/kgpe-d16/board_info.txt +++ b/src/mainboard/asus/kgpe-d16/board_info.txt @@ -3,3 +3,4 @@ ROM package: DIP-8 ROM protocol: SPI ROM socketed: y Flashrom support: y +Freedom level: gold diff --git a/src/mainboard/google/slippy/board_info.txt b/src/mainboard/google/slippy/board_info.txt index 4e2fd7d..0e26a82 100644 --- a/src/mainboard/google/slippy/board_info.txt +++ b/src/mainboard/google/slippy/board_info.txt @@ -5,3 +5,4 @@ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: y +Freedom level: vendorlock diff --git a/src/mainboard/google/veyron/board_info.txt b/src/mainboard/google/veyron/board_info.txt index 5ee07fb..0904de3 100644 --- a/src/mainboard/google/veyron/board_info.txt +++ b/src/mainboard/google/veyron/board_info.txt @@ -4,3 +4,4 @@ Category: misc ROM protocol: SPI ROM socketed: n Flashrom support: y +Freedom level: gold diff --git a/src/mainboard/lenovo/t400/board_info.txt b/src/mainboard/lenovo/t400/board_info.txt index a78a21b..f92fe7f 100644 --- a/src/mainboard/lenovo/t400/board_info.txt +++ b/src/mainboard/lenovo/t400/board_info.txt @@ -4,3 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: n Release year: 2008 +Freedom level: bronze diff --git a/src/mainboard/lenovo/t500/board_info.txt b/src/mainboard/lenovo/t500/board_info.txt index 007ec6c..656fe7f 100644 --- a/src/mainboard/lenovo/t500/board_info.txt +++ b/src/mainboard/lenovo/t500/board_info.txt @@ -4,3 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: n Clone of: lenovo/t400 +Freedom level: silver diff --git a/src/mainboard/lenovo/x200/board_info.txt b/src/mainboard/lenovo/x200/board_info.txt index c9cc003..0c83fbe 100644 --- a/src/mainboard/lenovo/x200/board_info.txt +++ b/src/mainboard/lenovo/x200/board_info.txt @@ -4,3 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: n Release year: 2008 +Freedom level: bronze

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Patch merged into coreboot/master: src/Kconfig: Move early defaults to the end of the file
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit 75e5cb7a74b037ba725480191c683cd8e5fab662 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:05:37 2016 -0700 src/Kconfig: Move early defaults to the end of the file For Kconfig options that we might want to override the default, move the fallback default to the bottom of the file. This allows the default to be set anywhere else, without requiring a select. This is especially important for non-boolean symbols, which can't have their defaults overridden in the Kconfig. Those can only be updated in a saved config file. Verified that this makes no significant changes to any config file. Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17906 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/17906 for details. -gerrit

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Patch merged into coreboot/master: util/blobtool: Add new tool for compiling/decompiling data blobs
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit 0685322f4a718f8302827d1ee073c0f891a2f713 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Nov 16 21:06:54 2016 +1100 util/blobtool: Add new tool for compiling/decompiling data blobs Given a specification of bitfields defined e.g. as follows: specfile: { "field1" : 8, "field2" : 4, "field3" : 4 } and a set of values for setting defaults: setterfile: { "field1" = 0xff, "field2" = 0xf, "field3" = 0xf } You can generate a binary packed blob as follows: ./blobtool specfile setterfile binaryoutput binaryoutput: ff ff The reverse is also possible, i.e. you can regenerate the setter: ./blobtool -d specfile binaryoutput setterorig setterorig: # AUTOGENERATED SETTER BY BLOBTOOL { "field1" = 0xff, "field2" = 0xf, "field3" = 0xf } This tool comes with spec/set files for X200 flash descriptor and ICH9M GbE region, and can be extended or used to decompile other data blobs with known specs. Change-Id: I744d6b421003feb4fc460133603af7e6bd80b1d6 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/17445 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17445 for details. -gerrit

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Patch merged into coreboot/master: google/jecht: Fix LED for guado/rikku variants
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit aaa4ae766d6bd731247c2b8bd009d1018136494f Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Jan 26 10:58:15 2017 -0600 google/jecht: Fix LED for guado/rikku variants When guado/rikku/tidus were rolled into jecht, an error was made in set_power_led() as guado/rikku set the polarity differently than tidus. Fix the power LED for guado/rikku by setting the polarity correctly. Test: boot guado/rikku and observe proper function of power LED under S0, S3, and S5 power states. Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/18249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18249 for details. -gerrit

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Patch merged into coreboot/master: lenovo/x60: use correct BLC_PWM_CTL value
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit 3054ca164e07b8f2dc2532e5672cd070e025ac70 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Mon Jun 22 17:37:06 2015 +0100 lenovo/x60: use correct BLC_PWM_CTL value Bit 16 in BLC_PWM_CTL enables brightness controls, but the current value is generic. Use the proper value, obtained by reading BLC_PWM_CTL while running the VBIOS. Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10624 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/10624 for details. -gerrit

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Patch merged into coreboot/master: Revert "google/pyro: remove Wacom touchscreen probed flag"
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit b576e6f236fd374421287f39542a9e26608406ff Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Sat Feb 4 03:55:01 2017 +0800 Revert "google/pyro: remove Wacom touchscreen probed flag" Reason for revert: Pyro has two touchscreen sources: WACOM/ELAN. It will not have both touchscreen IC in one system at the same time. So the "probed" property of WACOM i2c device is mandatory to set for kernel to know whether it exists before driver initializes it. Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF will be invoked to set GPIO#152 low to cut off power. BUG=chrome-os-partner:62371 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18291 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/18291 for details. -gerrit

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Patch merged into coreboot/master: Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit 410f256b6fa797b5046c86c91417da44b6549272 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Jan 25 15:27:52 2017 +0100 Only show CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM option when implemented This also selects RELOCATABLE_RAMSTAGE and CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell. Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18232 for details. -gerrit

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Patch merged into coreboot/master: google/eve: Fix DRAM DQS map
by gerrit＠coreboot.org 04 Feb '17

04 Feb '17

the following patch was just integrated into master: commit 9471d00a4f5acc5697d52e18dd74f909560a9031 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Feb 1 16:37:29 2017 -0800 google/eve: Fix DRAM DQS map This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18279 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18279 for details. -gerrit

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coreboot-gerrit February 2017