coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: src/Kconfig: Remove 'default n' statements from early in Kconfig
by Martin Roth 07 Feb '17

07 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17908 -gerrit commit 7c5f2b6b4621e61d5ff4d084bd16625fff24b372 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 15:35:12 2016 -0700 src/Kconfig: Remove 'default n' statements from early in Kconfig For boolean types, 'n' is the default default value - it doesn't NEED to be set. If it IS set, it prevents a later default from being set. So by removing the 'default n' statements from the early symbols, they can be overridden other places in the tree. Verified that this makes no significant changes to any config file. Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e18a1dd..d3a048c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -111,7 +111,6 @@ config SCONFIG_GENPARSER config USE_OPTION_TABLE bool "Use CMOS for configuration values" - default n depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" @@ -119,7 +118,6 @@ config USE_OPTION_TABLE config STATIC_OPTION_TABLE bool "Load default configuration values into CMOS on each boot" - default n depends on USE_OPTION_TABLE help Enable this option to reset "CMOS" NVRAM values to default on @@ -179,14 +177,12 @@ config INCLUDE_CONFIG_FILE config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. config USE_BLOBS bool "Allow use of binary-only repository" - default n help This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. @@ -195,7 +191,6 @@ config USE_BLOBS config COVERAGE bool "Code coverage support" depends on COMPILER_GCC - default n help Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. @@ -204,7 +199,6 @@ config COVERAGE config RELOCATABLE_RAMSTAGE depends on EARLY_CBMEM_INIT bool "Build the ramstage to be relocatable in 32-bit address space." - default n select RELOCATABLE_MODULES help The reloctable ramstage support allows for the ramstage to be built @@ -216,7 +210,6 @@ config RELOCATABLE_RAMSTAGE config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM depends on RELOCATABLE_RAMSTAGE bool - default n help The relocated ramstage is saved in an area specified by the by the board and/or chipset. @@ -241,7 +234,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" - default n depends on BOOTBLOCK_NORMAL help Do not clear the reboot count immediately after successful boot. @@ -251,7 +243,6 @@ config SKIP_MAX_REBOOT_CNT_CLEAR config UPDATE_IMAGE bool "Update existing coreboot.rom image" - default n help If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already @@ -270,7 +261,6 @@ config BOARD_ID_STRING config RAM_CODE_SUPPORT bool - default n help If enabled, coreboot discovers RAM configuration (value obtained by reading board straps) and stores it in coreboot table.

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Patch merged into coreboot/master: mainboards/google/reef: Add support for tablet mode switch.
by gerrit＠coreboot.org 07 Feb '17

07 Feb '17

the following patch was just integrated into master: commit 4f803ac28f4672cbf9ea8de92fb4ed680e582724 Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Wed Feb 1 12:56:24 2017 -0800 mainboards/google/reef: Add support for tablet mode switch. Reef is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I6dfddbfdb5a2ffbdfd77c5f49602bf68e9693a06 Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://review.coreboot.org/18277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18277 for details. -gerrit

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Patch merged into coreboot/master: google/eve: Add support for tablet mode switch.
by gerrit＠coreboot.org 07 Feb '17

07 Feb '17

the following patch was just integrated into master: commit fd691d48920dde7aa20d53e7c251c5f69d3b3b5a Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Wed Feb 1 12:11:27 2017 -0800 google/eve: Add support for tablet mode switch. Eve is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I35133ebc1439852d0ceb88d7d679b37356b0869d Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://review.coreboot.org/18276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18276 for details. -gerrit

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Patch merged into coreboot/master: ec/google/chromeec: Add support for tablet mode switch driver
by gerrit＠coreboot.org 07 Feb '17

07 Feb '17

the following patch was just integrated into master: commit 87d5fb89fe5224dbb743be5bffa4d3f524263f2b Author: Gwendal Grignou <gwendal(a)chromium.org> Date: Thu Jan 19 18:30:21 2017 -0800 ec/google/chromeec: Add support for tablet mode switch driver Add a new driver GOOG0006 to report tablet switch to user space. On glados based convertible, check that with a new kernel driver (cros_ec_tbmc) that evtest collects tablet switch changes. Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/430951 Reviewed-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/18173 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18173 for details. -gerrit

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Patch set updated for coreboot: car: Make CAR_GLOBALs work in romstage-linked libverstage
by Julius Werner 07 Feb '17

07 Feb '17

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18302 -gerrit commit 789f55284928ff877c64d14702e568e6e2d8550f Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Feb 6 14:24:58 2017 -0800 car: Make CAR_GLOBALs work in romstage-linked libverstage Our verstage code can currently be linked in four different ways, as controlled by chipset-selected Kconfig (excluding the extra complication from RETURN_FROM_VERSTAGE): 1. as libverstage linked directly into the bootblock 2. as a standalone stage between bootblock and romstage 3. as libverstage linked directly into the romstage 4. as a standalone stage between romstage and ramstage Unfortunately, <rules.h> defines ENV_VERSTAGE in all these cases (including 1 and 3, where it doesn't define ENV_BOOTBLOCK or ENV_ROMSTAGE, respectively), which makes it tricky to use when trying to draw any conclusions about the execution environment. The CAR_GLOBAL code seems to have only considered options 1 and 2, and unconditionally counts ENV_VERSTAGE as a pre-CAR-migration stage. This currently breaks vboot on Haswell platforms like Falco because tlcl_lib_init() never really runs. This patch fixes case 3 for those platforms. Case 4 might still be broken since it looks like vboot/Makefile.inc would incorrectly define __PRE_RAM__ for that undeniably post-RAM stage. However, I don't think any platforms actually use that configuration right now and I am not sure if it was really ever considered an intended execution mode (despite receiving some consideration in vboot_loader.c). (If it was not, it should probably be explicitly prevented by Kconfig dependencies and respective code should be removed.) Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/x86/include/arch/early_variables.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index e78b846..ca64c59 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -30,11 +30,12 @@ asm(".previous"); #endif /* __clang__ */ /* - * In stages that use CAR (verstage, C bootblock) all CAR_GLOBAL variables are - * accessed unconditionally because cbmem is never initialized until romstage - * when dram comes up. + * In stages that use CAR (early-style verstage, C bootblock) all CAR_GLOBAL + * variables are accessed unconditionally because cbmem is never initialized + * until romstage when dram comes up. */ -#if ENV_VERSTAGE || ENV_BOOTBLOCK +#if ENV_BOOTBLOCK || \ + (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) static inline void *car_get_var_ptr(void *var) { return var;

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New patch to review for coreboot: car: Make CAR_GLOBALs work in romstage-linked libverstage
by Julius Werner 07 Feb '17

07 Feb '17

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18302 -gerrit commit 2c8eac67368092ec493c3c6194bd8a38690b2777 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Feb 6 14:24:58 2017 -0800 car: Make CAR_GLOBALs work in romstage-linked libverstage Our verstage code can currently be linked in four different ways, as controlled by chipset-selected Kconfig (excluding the extra complication from RETURN_FROM_VERSTAGE): 1. as libverstage linked directly into the bootblock 2. as a standalone stage between bootblock and romstage 3. as libverstage linked directly into the romstage 4. as a standalone stage between romstage and ramstage Unfortunately, <rules.h> defines ENV_VERSTAGE in all these cases (including 1 and 3, where it doesn't define ENV_BOOTBLOCK or ENV_ROMSTAGE, respectively), which makes it tricky to use when trying to draw any conclusions about the execution environment. The CAR_GLOBAL code seems to have only considered options 1 and 2, and unconditionally counts ENV_VERSTAGE as a pre-CAR-migration stage. This currently breaks vboot on Haswell platforms like Falco because tlcl_lib_init() never really runs. This patch fixes case 3 for those platforms. Case 4 might still be broken since it looks like vboot/Makefile.inc would incorrectly define __PRE_RAM__ for that undeniably post-RAM stage. However, I don't think any platforms actually use that configuration right now and I am not sure if it was really ever considered an intended execution mode (despite receiving some consideration in vboot_loader.c). (If it was not, it should probably be explicitly prevented by Kconfig dependencies and respective code should be removed.) Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/x86/include/arch/early_variables.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index e78b846..ca64c59 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -30,11 +30,12 @@ asm(".previous"); #endif /* __clang__ */ /* - * In stages that use CAR (verstage, C bootblock) all CAR_GLOBAL variables are - * accessed unconditionally because cbmem is never initialized until romstage - * when dram comes up. + * In stages that use CAR (early-style verstage, C bootblock) all CAR_GLOBAL + * variables are accessed unconditionally because cbmem is never initialized + * until romstage when dram comes up. */ -#if ENV_VERSTAGE || ENV_BOOTBLOCK +#if ENV_BOOTBLOCK || \ + (ENV_VERSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) static inline void *car_get_var_ptr(void *var) { return var;

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New patch to review for coreboot: Turn CBMEM console into a ring buffer that can persist across reboots
by Julius Werner 07 Feb '17

07 Feb '17

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18301 -gerrit commit f76a674a3ece3f83bb274d8fde10c13a6abf2c37 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Feb 2 17:32:00 2017 -0800 Turn CBMEM console into a ring buffer that can persist across reboots This patch allows the CBMEM console to persist across reboots, which should greatly help post factum debugging of issues involving multiple reboots. In order to prevent the console from filling up, it will instead operate as a ring buffer that continues to evict the oldest lines once full. The console control structure is modified in a sorta backwards-compatible way, so that new readers can continue to work with old console buffers and vice versa. When an old reader reads a new buffer that has already once overflowed (i.e. is operating in true ring buffer mode) it will print lines out of order, but it will at least still print out the whole console content and not do any illegal memory accesses (assuming it correctly implemented cursor overflow as it was already possible before this patch). BUG=chromium:651966 TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco. Also confirmed correct behavior across suspend/resume for the latter. Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/cbmem_console.c | 26 +++- src/lib/cbmem_console.c | 202 +++++++++------------------- util/cbmem/cbmem.c | 53 ++++---- 3 files changed, 110 insertions(+), 171 deletions(-) diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c index 6873444..8e83224 100644 --- a/payloads/libpayload/drivers/cbmem_console.c +++ b/payloads/libpayload/drivers/cbmem_console.c @@ -32,7 +32,9 @@ struct cbmem_console { uint32_t size; - uint32_t cursor; + uint32_t cursor : 24; + uint32_t _reserved_flags : 7; + uint32_t overflowed : 1; uint8_t body[0]; } __attribute__ ((__packed__)); @@ -43,18 +45,30 @@ static struct console_output_driver cbmem_console_driver = .write = &cbmem_console_write, }; +static void do_write(const void *buffer, size_t count) +{ + memcpy(cbmem_console_p->body + cbmem_console_p->cursor, buffer, count); + cbmem_console_p->cursor += count; +} + void cbmem_console_init(void) { cbmem_console_p = lib_sysinfo.cbmem_cons; - if (cbmem_console_p) + if (cbmem_console_p && cbmem_console_p->size) console_add_output_driver(&cbmem_console_driver); } void cbmem_console_write(const void *buffer, size_t count) { - if (cbmem_console_p->cursor + count >= cbmem_console_p->size) - return; + while (cbmem_console_p->cursor + count >= cbmem_console_p->size) { + uint32_t still_fits = cbmem_console_p->size - + cbmem_console_p->cursor; + do_write(buffer, still_fits); + cbmem_console_p->overflowed = 1; + cbmem_console_p->cursor = 0; + buffer += still_fits; + count -= still_fits; + } - memcpy(cbmem_console_p->body + cbmem_console_p->cursor, buffer, count); - cbmem_console_p->cursor += count; + do_write(buffer, count); } diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 2845066..e6564a8 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -23,21 +23,22 @@ /* * Structure describing console buffer. It is overlaid on a flat memory area, - * with body covering the extent of the memory. Once the buffer is - * full, the cursor keeps going but the data is dropped on the floor. This - * allows to tell how much data was lost in the process. + * with body covering the extent of the memory. Once the buffer is full, + * output will wrap back around to the start of the buffer. The high bit of the + * cursor field gets set to indicate that this happened. If the underlying + * storage allows this, the buffer will persist across multiple boots and append + * to the previous log. */ struct cbmem_console { u32 size; - u32 cursor; + u32 cursor : 24; + u32 _reserved_flags : 7; + u32 overflowed : 1; u8 body[0]; } __attribute__ ((__packed__)); static struct cbmem_console *cbmem_console_p CAR_GLOBAL; -static void copy_console_buffer(struct cbmem_console *old_cons_p, - struct cbmem_console *new_cons_p); - #ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -62,21 +63,24 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, static u8 static_console[STATIC_CONSOLE_SIZE]; #endif -/* flags for init */ -#define CBMEMC_RESET (1<<0) -#define CBMEMC_APPEND (1<<1) - -static inline struct cbmem_console *current_console(void) +static struct cbmem_console *current_console(void) { return car_sync_var(cbmem_console_p); } -static inline void current_console_set(struct cbmem_console *new_console_p) +static void current_console_set(struct cbmem_console *new_console_p) { car_set_var(cbmem_console_p, new_console_p); } -static inline void init_console_ptr(void *storage, u32 total_space, int flags) +static int buffer_valid(struct cbmem_console *cbm_cons_p, u32 total_space) +{ + return cbm_cons_p->cursor < cbm_cons_p->size && + cbm_cons_p->_reserved_flags == 0 && + cbm_cons_p->size == total_space - sizeof(struct cbmem_console); +} + +static inline void init_console_ptr(void *storage, u32 total_space) { struct cbmem_console *cbm_cons_p = storage; @@ -85,14 +89,11 @@ static inline void init_console_ptr(void *storage, u32 total_space, int flags) return; } - if (flags & CBMEMC_RESET) { + if (!buffer_valid(cbm_cons_p, total_space)) { cbm_cons_p->size = total_space - sizeof(struct cbmem_console); cbm_cons_p->cursor = 0; - } - if (flags & CBMEMC_APPEND) { - struct cbmem_console *tmp_cons_p = current_console(); - if (tmp_cons_p) - copy_console_buffer(tmp_cons_p, cbm_cons_p); + cbm_cons_p->_reserved_flags = 0; + cbm_cons_p->overflowed = 0; } current_console_set(cbm_cons_p); @@ -101,149 +102,66 @@ static inline void init_console_ptr(void *storage, u32 total_space, int flags) void cbmemc_init(void) { #ifdef __PRE_RAM__ - int flags = 0; - - /* If in bootblock always initialize the console first. */ - if (ENV_BOOTBLOCK) - flags = CBMEMC_RESET; - else if (ENV_ROMSTAGE) { - /* Initialize console for the first time in romstage when - * there's no prior stage that initialized it first. */ - if (!IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && - !IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) - flags = CBMEMC_RESET; - } else if (ENV_VERSTAGE) { - /* - * Initialize console for the first time in verstage when - * there is no console in bootblock. Otherwise honor the - * bootblock console when verstage comes right after - * bootblock. - */ - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && - !IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) - flags = CBMEMC_RESET; - } - - init_console_ptr(_preram_cbmem_console, - _preram_cbmem_console_size, flags); + /* Pre-RAM environments use special buffer placed by linker script. */ + init_console_ptr(_preram_cbmem_console, _preram_cbmem_console_size); #else - /* - * Initializing before CBMEM is available, use static buffer to store - * the log. - */ - init_console_ptr(static_console, sizeof(static_console), CBMEMC_RESET); + /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ + init_console_ptr(static_console, sizeof(static_console)); #endif } void cbmemc_tx_byte(unsigned char data) { struct cbmem_console *cbm_cons_p = current_console(); - u32 cursor; - if (!cbm_cons_p) + if (!cbm_cons_p || !cbm_cons_p->size) return; - cursor = cbm_cons_p->cursor++; - if (cursor < cbm_cons_p->size) - cbm_cons_p->body[cursor] = data; + cbm_cons_p->body[cbm_cons_p->cursor++] = data; + if (cbm_cons_p->cursor >= cbm_cons_p->size) { + cbm_cons_p->overflowed = 1; + cbm_cons_p->cursor = 0; + } } /* - * Copy the current console buffer (either from the cache as RAM area, or from - * the static buffer, pointed at by cbmem_console_p) into the CBMEM console - * buffer space (pointed at by new_cons_p), concatenating the copied data with - * the CBMEM console buffer contents. - * - * If there is overflow - add to the destination area a string, reporting the - * overflow and the number of dropped characters. + * Copy the current console buffer (either from the cache as RAM area or from + * the static buffer, pointed at by cons_p) into the newly initialized CBMEM + * console. The use of cbmemc_tx_byte() ensures that all special cases for the + * target console (e.g. overflow) will be handled. If there had been an + * overflow in the source console, log a message to that effect. */ -static void copy_console_buffer(struct cbmem_console *old_cons_p, - struct cbmem_console *new_cons_p) +static void copy_console_buffer(struct cbmem_console *src_cons_p) { - u32 copy_size, dropped_chars; - u32 cursor = new_cons_p->cursor; - - if (old_cons_p->cursor < old_cons_p->size) - copy_size = old_cons_p->cursor; - else - copy_size = old_cons_p->size; - - if (cursor > new_cons_p->size) - copy_size = 0; - else if (cursor + copy_size > new_cons_p->size) - copy_size = new_cons_p->size - cursor; - - dropped_chars = old_cons_p->cursor - copy_size; - if (dropped_chars) { - /* Reserve 80 chars to report overflow, if possible. */ - if (copy_size < 80) - return; - copy_size -= 80; - dropped_chars += 80; + u32 c; + + if (src_cons_p->overflowed) { + const char overflow_warning[] = "\n*** Pre-CBMEM console " + "overflowed, log truncated ***\n"; + for (c = 0; c < sizeof(overflow_warning) - 1; c++) + cbmemc_tx_byte(overflow_warning[c]); + for (c = src_cons_p->cursor; c < src_cons_p->size; c++) + cbmemc_tx_byte(src_cons_p->body[c]); } - memcpy(new_cons_p->body + cursor, old_cons_p->body, - copy_size); - - cursor += copy_size; - - if (dropped_chars) { - const char loss_str1[] = "\n\n*** Log truncated, "; - const char loss_str2[] = " characters dropped. ***\n\n"; - - /* - * When running from ROM sprintf is not available, a simple - * itoa implementation is used instead. - */ - int got_first_digit = 0; - - /* Way more than possible number of dropped characters. */ - u32 mult = 100000; - - strcpy((char *)new_cons_p->body + cursor, loss_str1); - cursor += sizeof(loss_str1) - 1; - - while (mult) { - int digit = dropped_chars / mult; - if (got_first_digit || digit) { - new_cons_p->body[cursor++] = digit + '0'; - dropped_chars %= mult; - /* Excessive, but keeps it simple */ - got_first_digit = 1; - } - mult /= 10; - } + for (c = 0; c < src_cons_p->cursor; c++) + cbmemc_tx_byte(src_cons_p->body[c]); - strcpy((char *)new_cons_p->body + cursor, loss_str2); - cursor += sizeof(loss_str2) - 1; - } - new_cons_p->cursor = cursor; + /* Invalidate the source console, so it will be reinitialized on the + next reboot. Otherwise, we might copy the same bytes again. */ + src_cons_p->size = 0; } static void cbmemc_reinit(int is_recovery) { - struct cbmem_console *cbm_cons_p; const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; - int flags = CBMEMC_APPEND; - - /* No appending when no preram console available and adding for - * the first time. */ - if (!ENV_RAMSTAGE && !ENV_POSTCAR && _preram_cbmem_console_size == 0) - flags = CBMEMC_RESET; - - /* Need to reset the newly added cbmem console in romstage. */ - if (ENV_ROMSTAGE) - flags |= CBMEMC_RESET; + /* If CBMEM entry already existed, old contents are not altered. */ + struct cbmem_console *cbmem_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size); + struct cbmem_console *preram_cons_p = current_console(); - /* Need to reset the newly added cbmem console in ramstage - * when there was no console in preram environment. */ - if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) - flags |= CBMEMC_RESET; - - /* If CBMEM entry already existed, old contents is not altered. */ - cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size); - - init_console_ptr(cbm_cons_p, size, flags); + init_console_ptr(cbmem_cons_p, size); + if (preram_cons_p && current_console()) + copy_console_buffer(preram_cons_p); } ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) @@ -253,13 +171,17 @@ POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit) void cbmem_dump_console(void) { struct cbmem_console *cbm_cons_p; - int cursor; + u32 cursor; cbm_cons_p = current_console(); if (!cbm_cons_p) return; uart_init(0); + if (cbm_cons_p->overflowed) + for (cursor = cbm_cons_p->cursor; + cursor < cbm_cons_p->size; cursor++) + uart_tx_byte(0, cbm_cons_p->body[cursor]); for (cursor = 0; cursor < cbm_cons_p->cursor; cursor++) uart_tx_byte(0, cbm_cons_p->body[cursor]); } diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 99f25f8..b03e20c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -601,52 +601,55 @@ static void dump_timestamps(int mach_readable) unmap_memory(); } +struct cbmem_console { + u32 size; + u32 cursor : 24; + u32 _reserved_flags : 7; + u32 overflowed : 1; + u8 body[0]; +} __attribute__ ((__packed__)); + /* dump the cbmem console */ static void dump_console(void) { - void *console_p; + struct cbmem_console *console_p; char *console_c; - uint32_t size; - uint32_t cursor; + size_t size; if (console.tag != LB_TAG_CBMEM_CONSOLE) { fprintf(stderr, "No console found in coreboot table.\n"); return; } - console_p = map_memory_size((unsigned long)console.cbmem_addr, - 2 * sizeof(uint32_t), 1); - /* The in-memory format of the console area is: - * u32 size - * u32 cursor - * char console[size] - * Hence we have to add 8 to get to the actual console string. - */ - size = ((uint32_t *)console_p)[0]; - cursor = ((uint32_t *)console_p)[1]; - /* Cursor continues to go on even after no more data fits in - * the buffer but the data is dropped in this case. - */ - if (size > cursor) - size = cursor; - console_c = calloc(1, size + 1); + size = sizeof(*console_p); + console_p = map_memory_size((unsigned long)console.cbmem_addr, size, 1); + if (!console_p->overflowed && console_p->cursor < console_p->size) + size = console_p->cursor; + else + size = console_p->size; unmap_memory(); + + console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); exit(1); } + console_c[size] = '\0'; console_p = map_memory_size((unsigned long)console.cbmem_addr, - size + sizeof(size) + sizeof(cursor), 1); - aligned_memcpy(console_c, console_p + 8, size); + size + sizeof(*console_p), 1); + if (console_p->overflowed) { + aligned_memcpy(console_c, console_p->body + console_p->cursor, + console_p->size - console_p->cursor); + aligned_memcpy(console_c + console_p->size - console_p->cursor, + console_p->body, console_p->cursor); + } else { + aligned_memcpy(console_c, console_p->body, size); + } printf("%s\n", console_c); - if (size < cursor) - printf("%d %s lost\n", cursor - size, - (cursor - size) == 1 ? "byte":"bytes"); free(console_c); - unmap_memory(); }

1 0

New patch to review for coreboot: cbmem: Add custom aligned memcpy() implementation
by Julius Werner 07 Feb '17

07 Feb '17

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18300 -gerrit commit 6f195e2b8c324134b64163c92745b826e36315c6 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Feb 3 12:50:03 2017 -0800 cbmem: Add custom aligned memcpy() implementation On some architectures (like AArch64), /dev/mem mappings outside of the area marked as normal RAM use a memory type that does not support unaligned accesses. The libc memcpy() implementation on these architectures may not know or expect that and make an unaligned access for certain source/dest/length alignments. Add a custom memcpy() implementation that takes these restrictions into account and use it anywhere we copy straight out of /dev/mem memory. Change-Id: I03eece380a14a69d4be3805ed72fba640f6f7d9c Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- util/cbmem/cbmem.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 7b434d87..99f25f8 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -61,6 +61,36 @@ static uint64_t lbtable_address; static size_t lbtable_size; /* + * Some architectures map /dev/mem memory in a way that doesn't support + * unaligned accesses. Most normal libc memcpy()s aren't safe to use in this + * case, so build our own which makes sure to never do unaligned accesses on + * *src (*dest is fine since we never map /dev/mem for writing). + */ +static void *aligned_memcpy(void *dest, const void *src, size_t n) +{ + u8 *d = dest; + const u8 *s = src; + + while ((uintptr_t)s & (sizeof(size_t) - 1)) { + if (n-- == 0) + return dest; + *d++ = *s++; + } + + while (n >= sizeof(size_t)) { + *(size_t *)d = *(size_t *)s; + d += sizeof(size_t); + s += sizeof(size_t); + n -= sizeof(size_t); + } + + while (n-- > 0) + *d++ = *s++; + + return dest; +} + +/* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case * the buffer length is odd last byte is excluded from the calculation */ @@ -608,7 +638,7 @@ static void dump_console(void) console_p = map_memory_size((unsigned long)console.cbmem_addr, size + sizeof(size) + sizeof(cursor), 1); - memcpy(console_c, console_p + 8, size); + aligned_memcpy(console_c, console_p + 8, size); printf("%s\n", console_c); if (size < cursor)

1 0

New patch to review for coreboot: cbmem_console: Remove "buffer_" prefix from all structure fields
by Julius Werner 07 Feb '17

07 Feb '17

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18299 -gerrit commit 13decb4de8f922f15799ab08e1d1ad292937fbb7 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Feb 3 12:45:21 2017 -0800 cbmem_console: Remove "buffer_" prefix from all structure fields Shorten field names of struct cbmem_console since saying "buffer_" in front of everything is redundant and we can use the gained space to save some line breaks in the code later. This also aligns the definition with the version in libpayload. Change-Id: I160ad1f39b719ac7e912d0466c82a58013cca0f9 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/cbmem_console.c | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 06f34af..2845066 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -23,14 +23,14 @@ /* * Structure describing console buffer. It is overlaid on a flat memory area, - * with buffer_body covering the extent of the memory. Once the buffer is + * with body covering the extent of the memory. Once the buffer is * full, the cursor keeps going but the data is dropped on the floor. This * allows to tell how much data was lost in the process. */ struct cbmem_console { - u32 buffer_size; - u32 buffer_cursor; - u8 buffer_body[0]; + u32 size; + u32 cursor; + u8 body[0]; } __attribute__ ((__packed__)); static struct cbmem_console *cbmem_console_p CAR_GLOBAL; @@ -86,8 +86,8 @@ static inline void init_console_ptr(void *storage, u32 total_space, int flags) } if (flags & CBMEMC_RESET) { - cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); - cbm_cons_p->buffer_cursor = 0; + cbm_cons_p->size = total_space - sizeof(struct cbmem_console); + cbm_cons_p->cursor = 0; } if (flags & CBMEMC_APPEND) { struct cbmem_console *tmp_cons_p = current_console(); @@ -143,9 +143,9 @@ void cbmemc_tx_byte(unsigned char data) if (!cbm_cons_p) return; - cursor = cbm_cons_p->buffer_cursor++; - if (cursor < cbm_cons_p->buffer_size) - cbm_cons_p->buffer_body[cursor] = data; + cursor = cbm_cons_p->cursor++; + if (cursor < cbm_cons_p->size) + cbm_cons_p->body[cursor] = data; } /* @@ -161,19 +161,19 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, struct cbmem_console *new_cons_p) { u32 copy_size, dropped_chars; - u32 cursor = new_cons_p->buffer_cursor; + u32 cursor = new_cons_p->cursor; - if (old_cons_p->buffer_cursor < old_cons_p->buffer_size) - copy_size = old_cons_p->buffer_cursor; + if (old_cons_p->cursor < old_cons_p->size) + copy_size = old_cons_p->cursor; else - copy_size = old_cons_p->buffer_size; + copy_size = old_cons_p->size; - if (cursor > new_cons_p->buffer_size) + if (cursor > new_cons_p->size) copy_size = 0; - else if (cursor + copy_size > new_cons_p->buffer_size) - copy_size = new_cons_p->buffer_size - cursor; + else if (cursor + copy_size > new_cons_p->size) + copy_size = new_cons_p->size - cursor; - dropped_chars = old_cons_p->buffer_cursor - copy_size; + dropped_chars = old_cons_p->cursor - copy_size; if (dropped_chars) { /* Reserve 80 chars to report overflow, if possible. */ if (copy_size < 80) @@ -182,7 +182,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, dropped_chars += 80; } - memcpy(new_cons_p->buffer_body + cursor, old_cons_p->buffer_body, + memcpy(new_cons_p->body + cursor, old_cons_p->body, copy_size); cursor += copy_size; @@ -200,13 +200,13 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, /* Way more than possible number of dropped characters. */ u32 mult = 100000; - strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1); + strcpy((char *)new_cons_p->body + cursor, loss_str1); cursor += sizeof(loss_str1) - 1; while (mult) { int digit = dropped_chars / mult; if (got_first_digit || digit) { - new_cons_p->buffer_body[cursor++] = digit + '0'; + new_cons_p->body[cursor++] = digit + '0'; dropped_chars %= mult; /* Excessive, but keeps it simple */ got_first_digit = 1; @@ -214,10 +214,10 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, mult /= 10; } - strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2); + strcpy((char *)new_cons_p->body + cursor, loss_str2); cursor += sizeof(loss_str2) - 1; } - new_cons_p->buffer_cursor = cursor; + new_cons_p->cursor = cursor; } static void cbmemc_reinit(int is_recovery) @@ -260,7 +260,7 @@ void cbmem_dump_console(void) return; uart_init(0); - for (cursor = 0; cursor < cbm_cons_p->buffer_cursor; cursor++) - uart_tx_byte(0, cbm_cons_p->buffer_body[cursor]); + for (cursor = 0; cursor < cbm_cons_p->cursor; cursor++) + uart_tx_byte(0, cbm_cons_p->body[cursor]); } #endif

1 0

Patch set updated for coreboot: intel/minnow3: Add new mainboard
by Brenton Dong 07 Feb '17

07 Feb '17

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18298 -gerrit commit c09c17926f47a1e0d2a5a8f0c1aa0c0e8e234078 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Mon Feb 6 16:07:27 2017 -0700 intel/minnow3: Add new mainboard This commit adds the initial scaffolding for the MinnowBoard 3 with Apollo Lake silicon. This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MinnowBoard 3 mainboard will follow in separate commits. Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/minnow3/Kconfig | 20 +++ src/mainboard/intel/minnow3/Kconfig.name | 2 + src/mainboard/intel/minnow3/Makefile.inc | 3 + src/mainboard/intel/minnow3/acpi_tables.c | 3 + src/mainboard/intel/minnow3/board_info.txt | 6 + src/mainboard/intel/minnow3/bootblock.c | 22 +++ src/mainboard/intel/minnow3/brd_gpio.h | 62 ++++++++ src/mainboard/intel/minnow3/devicetree.cb | 230 +++++++++++++++++++++++++++++ src/mainboard/intel/minnow3/dsdt.asl | 42 ++++++ src/mainboard/intel/minnow3/mainboard.c | 25 ++++ src/mainboard/intel/minnow3/minnow3.fmd | 40 +++++ src/mainboard/intel/minnow3/romstage.c | 119 +++++++++++++++ 12 files changed, 574 insertions(+) diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig new file mode 100644 index 0000000..3a5f7c7 --- /dev/null +++ b/src/mainboard/intel/minnow3/Kconfig @@ -0,0 +1,20 @@ +if BOARD_INTEL_MINNOW3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES +# select HAVE_INTEL_FIRMWARE +# select HAVE_ME_BIN +# select LOCK_MANAGEMENT_ENGINE + +config MAINBOARD_DIR + string + default intel/minnow3 + +config MAINBOARD_PART_NUMBER + string + default "Minnow3" + +endif # BOARD_INTEL_MINNOW3 diff --git a/src/mainboard/intel/minnow3/Kconfig.name b/src/mainboard/intel/minnow3/Kconfig.name new file mode 100644 index 0000000..a62f36f --- /dev/null +++ b/src/mainboard/intel/minnow3/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_MINNOW3 + bool "Minnow3" diff --git a/src/mainboard/intel/minnow3/Makefile.inc b/src/mainboard/intel/minnow3/Makefile.inc new file mode 100644 index 0000000..9e3e892 --- /dev/null +++ b/src/mainboard/intel/minnow3/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/intel/minnow3/acpi_tables.c b/src/mainboard/intel/minnow3/acpi_tables.c new file mode 100644 index 0000000..e06f6a6 --- /dev/null +++ b/src/mainboard/intel/minnow3/acpi_tables.c @@ -0,0 +1,3 @@ +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/intel/minnow3/board_info.txt b/src/mainboard/intel/minnow3/board_info.txt new file mode 100644 index 0000000..e0e5501 --- /dev/null +++ b/src/mainboard/intel/minnow3/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Leafhill Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c new file mode 100644 index 0000000..3de44a8 --- /dev/null +++ b/src/mainboard/intel/minnow3/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/lpc.h> + +void bootblock_mainboard_init(void) +{ + lpc_configure_pads(); +} diff --git a/src/mainboard/intel/minnow3/brd_gpio.h b/src/mainboard/intel/minnow3/brd_gpio.h new file mode 100644 index 0000000..33b839b --- /dev/null +++ b/src/mainboard/intel/minnow3/brd_gpio.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb new file mode 100644 index 0000000..2ccf277 --- /dev/null +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -0,0 +1,230 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_122" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C0 for audio codec at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }" + + # Enable I2C2 bus early for TPM at 400kHz + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 57, + .fall_time_ns = 28, + }" + + # touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }" + + # trackpad at 400kHz + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 114, + .fall_time_ns = 164, + }" + + # digitizer at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on + chip drivers/i2c/wacom + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_DT_DESC, + .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl new file mode 100644 index 0000000..004523a --- /dev/null +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/minnow3/mainboard.c b/src/mainboard/intel/minnow3/mainboard.c new file mode 100644 index 0000000..f7a2ef1 --- /dev/null +++ b/src/mainboard/intel/minnow3/mainboard.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + /* Nothing Here Yet */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd new file mode 100644 index 0000000..0782047 --- /dev/null +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + WP_RO@0x0 0x480000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x27f000 + RO_VPD@0x280000 0x4000 + RO_SECTION@0x284000 0x1fc000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x1bb000 + RO_UNUSED@0x1bc000 0x40000 + } + } + MISC_RW@0x480000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c new file mode 100644 index 0000000..5c784ba --- /dev/null +++ b/src/mainboard/intel/minnow3/romstage.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + memupd->FspmConfig.Package = 0x1; + memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LASR = 0x0; + memupd->FspmConfig.ScramblerSupport = 0x1; + memupd->FspmConfig.ChannelHashMask = 0x36; + memupd->FspmConfig.SliceHashMask = 0x9; + memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ChannelsSlicesEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.RmtMode = 0x0; + memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.LowMemoryMaxValue = 0x0; + memupd->FspmConfig.DisableFastBoot = 0x0; + memupd->FspmConfig.HighMemoryMaxValue = 0x0; + memupd->FspmConfig.DIMM0SPDAddress = 0x0; + memupd->FspmConfig.DIMM1SPDAddress = 0x0; + memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; + memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_Option = 0x3; + memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_TristateClk1 = 0x0; + memupd->FspmConfig.Ch0_Mode2N = 0x0; + memupd->FspmConfig.Ch0_OdtLevels = 0x0; + memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; + memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_Option = 0x3; + memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_TristateClk1 = 0x0; + memupd->FspmConfig.Ch1_Mode2N = 0x0; + memupd->FspmConfig.Ch1_OdtLevels = 0x0; + memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; + memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_Option = 0x3; + memupd->FspmConfig.Ch2_OdtConfig = 0x0; + memupd->FspmConfig.Ch2_TristateClk1 = 0x0; + memupd->FspmConfig.Ch2_Mode2N = 0x0; + memupd->FspmConfig.Ch2_OdtLevels = 0x0; + memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; + memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_Option = 0x3; + memupd->FspmConfig.Ch3_OdtConfig = 0x0; + memupd->FspmConfig.Ch3_TristateClk1 = 0x0; + memupd->FspmConfig.Ch3_Mode2N = 0x0; + memupd->FspmConfig.Ch3_OdtLevels = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.MrcDataSaving = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x0; + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; +}

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coreboot-gerrit February 2017