coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/apollolake: dump CSE status
by gerrit＠coreboot.org 08 Feb '17

08 Feb '17

the following patch was just integrated into master: commit 7d14af815492d7d886244086ad24dde3d9805381 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 7 11:33:56 2017 -0600 soc/intel/apollolake: dump CSE status Dump the CSE status registers for potential debugging purposes. Explicitly call out manufacturing mode of the part since it's important shipping devices ensure manufacturing mode is locked down. Intel is planning on writing a common driver so a complete status -> string dumps was not done because (surprise surprise) not all the fields are equal with previous implementations. BUG=chrome-os-partner:62177 BRANCH=reef TEST=Booted and noted dump of CSE status registers. Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/18303 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/18303 for details. -gerrit

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Patch set updated for coreboot: nb/i945/gma.c: Refactor panel setup
by Arthur Heymans 08 Feb '17

08 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit 2d0fe59bb22b42194bc1b359084fdcfa97145f2c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 nb/i945/gma.c: Refactor panel setup This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. TESTED on Lenovo Thinkpad X60 Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/i915_reg.h | 2 +- src/mainboard/apple/macbook21/devicetree.cb | 7 ++- src/mainboard/lenovo/t60/devicetree.cb | 7 ++- src/mainboard/lenovo/x60/devicetree.cb | 7 ++- src/northbridge/intel/i945/chip.h | 10 ++++- src/northbridge/intel/i945/gma.c | 66 +++++++++++++++++++++++++++-- 6 files changed, 91 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..dee6865 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -62,7 +62,7 @@ #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..b6e61eb 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..6ad054c 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "275" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..28b63d3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..d50064e 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,16 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + /* In units of 100us timer */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + /* In units of 0.1s */ + u8 gpu_panel_power_cycle_delay; + u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index eac8717..5034b97 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -47,6 +47,8 @@ #define BASE_FREQUENCY 100000 +#define DEFAULT_BLC_PWM 180 + static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; @@ -292,9 +294,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(mmiobase + DSPPOS(0), 0); - /* Backlight init. */ - write32(mmiobase + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(mmiobase + DSPADDR(0), 0); write32(mmiobase + DSPSURF(0), 0); @@ -571,6 +570,63 @@ static int probe_edid(u8 *mmiobase, u8 slave) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + u16 gcfgc = pci_read_config16(dev, GCFGC); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { + return 133333333; + } else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_320_MHZ: + return 320000000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 200000000; + } + } +} + +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + /* Set duty cycle to 100% due to use of legacy backlight control */ + blc_mod = get_cdclk(dev) / (32 * pwm_freq); + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(u8 *mmiobase, struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Set up Panel Power On Delays */ + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + write32(mmiobase + PP_ON_DELAYS, reg32); + + /* Set up Panel Power Off Delays */ + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + write32(mmiobase + PP_OFF_DELAYS, reg32); + + /* Set up Panel Power Cycle Delay */ + reg32 = (get_cdclk(dev) / 20000 - 1) << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + write32(mmiobase + PP_DIVISOR, reg32); + + /* Backlight init. */ + if (conf->pwm_freq) + write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); + else + write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + DEFAULT_BLC_PWM)); +} static void gma_func0_init(struct device *dev) { @@ -615,6 +671,10 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + panel_setup(mmiobase, dev); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

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New patch to review for coreboot: nb/amd/amdmct: Remove two currently unused tables
by Jonathan Neuschäfer 08 Feb '17

08 Feb '17

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18308 -gerrit commit ce286bcff317eb992e9b8092af1930ba008577ca Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Feb 8 12:01:26 2017 +0100 nb/amd/amdmct: Remove two currently unused tables This fixes warnings that the new toolchain generates. Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/northbridge/amd/amdmct/mct/mctardk3.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index fe57d31..ce79a52 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -153,22 +153,6 @@ static const u8 Table_ATC_ODC_4D_D[] = { 0xFF }; -static const u8 Table_ATC_ODC_8D_D_Ax[] = { - 1,0xff,0x00,0x00,0x2F,0x0,0x22,0x12,0x11,0x00, 0xFE, - 2,0xff,0x00,0x00,0x2C,0x0,0x22,0x12,0x11,0x00, 0xFE, - 3,0xff,0x00,0x00,0x2C,0x0,0x22,0x12,0x11,0x00, 0xFE, - 4,0xff,0x00,0x33,0x2F,0x0,0x22,0x12,0x11,0x00, 0xFE, - 0xFF -}; - -static const u8 Table_ATC_ODC_4D_D_Ax[] = { - 1,0xff,0x00,0x00,0x2F,0x00,0x22,0x12,0x11,0x00, 0xFE, - 2,0xff,0x00,0x2C,0x2C,0x00,0x22,0x12,0x11,0x00, 0xFE, - 3,0xff,0x00,0x00,0x2C,0x00,0x22,0x12,0x11,0x00, 0xFE, - 4,0xff,0x00,0x33,0x2F,0x00,0x22,0x12,0x11,0x00, 0xFE, - 0xFF -}; - static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL)

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Patch set updated for coreboot: Kabylake: Set FADT.8042 flag with CONFIG_DRIVERS_PS2_KEYBOARD
by Jenny Tc 08 Feb '17

08 Feb '17

Jenny Tc (jenny.tc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18307 -gerrit commit 69388635cba5e94598930c63758ec4e567a764bf Author: Jenny TC <jenny.tc(a)intel.com> Date: Tue Feb 7 14:16:54 2017 +0530 Kabylake: Set FADT.8042 flag with CONFIG_DRIVERS_PS2_KEYBOARD Kernel relies on FADT 8042 flag to enable/disable 8042 interface. In coreboot, FADT 8042 flag cane be enabled/disabled based on the coreboot config CONFIG_DRIVERS_PS2_KEYBOARD BUG=chrome-os-partner:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- src/soc/intel/skylake/acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 54468d2..8488f52 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -268,7 +268,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + if (IS_ENABLED(CONFIG_DRIVERS_PS2_KEYBOARD)) + fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |

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New patch to review for coreboot: Skylake: Set FADT.8042 flag with CONFIG_DRIVERS_PS2_KEYBOARD
by Jenny Tc 08 Feb '17

08 Feb '17

Jenny Tc (jenny.tc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18307 -gerrit commit e03131f3dc980bf76d67ebfa76e2b3e8b705143e Author: Jenny TC <jenny.tc(a)intel.com> Date: Tue Feb 7 14:16:54 2017 +0530 Skylake: Set FADT.8042 flag with CONFIG_DRIVERS_PS2_KEYBOARD Kernel relies on FADT 8042 flag to enable/disable 8042 interface. In coreboot, FADT 8042 flag cane be enabled/disabled based on the coreboot config CONFIG_DRIVERS_PS2_KEYBOARD BUG=chromium:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- src/soc/intel/skylake/acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 54468d2..8488f52 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -268,7 +268,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + if (IS_ENABLED(CONFIG_DRIVERS_PS2_KEYBOARD)) + fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |

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Patch set updated for coreboot: siemens/mc_apl1: Make basic settings for booting the mainboard
by Mario Scheithauer 08 Feb '17

08 Feb '17

Mario Scheithauer (mario.scheithauer(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18292 -gerrit commit ca2547046e151645c55753bdb5baecf010a58535 Author: Mario Scheithauer <mario.scheithauer(a)siemens.com> Date: Mon Feb 6 13:03:52 2017 +0100 siemens/mc_apl1: Make basic settings for booting the mainboard This commit makes a basic adjustment for GPIOs, device tree, flash map and MRC settings. With these basic settings the mainboard boots into Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow. Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- src/mainboard/siemens/mc_apl1/acpi_tables.c | 4 +- src/mainboard/siemens/mc_apl1/brd_gpio.h | 38 ++--- src/mainboard/siemens/mc_apl1/devicetree.cb | 227 ++++------------------------ src/mainboard/siemens/mc_apl1/mc_apl1.fmd | 20 +-- src/mainboard/siemens/mc_apl1/romstage.c | 75 ++++----- 5 files changed, 94 insertions(+), 270 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/acpi_tables.c b/src/mainboard/siemens/mc_apl1/acpi_tables.c index e06f6a6..158af61 100644 --- a/src/mainboard/siemens/mc_apl1/acpi_tables.c +++ b/src/mainboard/siemens/mc_apl1/acpi_tables.c @@ -1,3 +1 @@ -/* - * Blank file required by build system assumptions of this file being present. - */ +/*Blank file required by build system assumptions of this file being present.*/ diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h index 33b839b..564ee69 100644 --- a/src/mainboard/siemens/mc_apl1/brd_gpio.h +++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,11 +19,7 @@ #if ENV_ROMSTAGE static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ - PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ - PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ - PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ - + /* Debug tracing. */ PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), @@ -33,30 +30,25 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ - PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), - /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ - PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - - PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* Unused */ PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index ce01a8b..c82896c 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -4,221 +4,54 @@ chip soc/intel/apollolake device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports + register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "0" # MACPHY + register "pcie_rp3_clkreq_pin" = "1" # MACPHY register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, - }" - - # digitizer at 400kHz - register "i2c[5]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - device domain 0 on device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC + device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 off end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOM50C1_HID, - .cid = PNP0C50_CID, - .desc = WCOM_DT_DESC, - .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), - }" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 5 + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 device pci 17.2 off end # - I2C 6 - device pci 17.3 off end # - I2C 7 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 - device pci 1a.0 on end # - PWM + device pci 1a.0 off end # - PWM device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on end # - LPC device pci 1f.1 on end # - SMBUS diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 3da8467..432e8de 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,15 +1,16 @@ FLASH 16M { - WP_RO@0x0 0x400000 { + WP_RO@0x0 0xe00000 { SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { + IFWI@0x1000 0x23f000 + RO_VPD@0x240000 0x4000 + RO_SECTION@0x244000 0xbbc000 { FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x1bb000 - RO_UNUSED@0x1bc000 0x40000 + RO_UNUSED_1@0x800 0x800 + COREBOOT(CBFS)@0x1000 0xbb9000 + RO_UNUSED_2@0xbba000 0x1000 } } - MISC_RW@0x400000 0x30000 { + MISC_RW@0xe00000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -23,9 +24,8 @@ FLASH 16M { RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 + BIOS_UNUSABLE@0xe30000 0xcf000 + DEVICE_EXTENSION@0xeff000 0x100000 # Currently, it is required that the BIOS region be a multiple of 8KiB. # This is required so that the recovery mechanism can find SIGN_CSE # region aligned to 4K at the center of BIOS region. Since the diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 5c784ba..9dd42bc 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2016 Google Inc. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,28 +21,28 @@ #include "brd_gpio.h" static const uint8_t Ch0_Bit_swizzling[] = { - 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, - 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, - 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, - 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch1_Bit_swizzling[] = { - 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, - 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, - 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, - 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch2_Bit_swizzling[] = { - 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, - 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, - 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, - 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch3_Bit_swizzling[] = { - 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, - 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, - 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, - 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -51,59 +52,59 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; - memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.Profile = 0x19; memupd->FspmConfig.MemoryDown = 0x1; - memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LPageSize = 0x2; memupd->FspmConfig.DDR3LASR = 0x0; - memupd->FspmConfig.ScramblerSupport = 0x1; - memupd->FspmConfig.ChannelHashMask = 0x36; - memupd->FspmConfig.SliceHashMask = 0x9; - memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ScramblerSupport = 0x0; + memupd->FspmConfig.ChannelHashMask = 0x0; + memupd->FspmConfig.SliceHashMask = 0x0; + memupd->FspmConfig.InterleavedMode = 0x0; memupd->FspmConfig.ChannelsSlicesEnable = 0x0; - memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x1; memupd->FspmConfig.DualRankSupportEnable = 0x1; memupd->FspmConfig.RmtMode = 0x0; - memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.MemorySizeLimit = 0x1000; memupd->FspmConfig.LowMemoryMaxValue = 0x0; memupd->FspmConfig.DisableFastBoot = 0x0; memupd->FspmConfig.HighMemoryMaxValue = 0x0; memupd->FspmConfig.DIMM0SPDAddress = 0x0; memupd->FspmConfig.DIMM1SPDAddress = 0x0; - memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_RankEnable = 0x1; memupd->FspmConfig.Ch0_DeviceWidth = 0x1; - memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_DramDensity = 0x0; memupd->FspmConfig.Ch0_Option = 0x3; - memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_OdtConfig = 0x1; memupd->FspmConfig.Ch0_TristateClk1 = 0x0; memupd->FspmConfig.Ch0_Mode2N = 0x0; memupd->FspmConfig.Ch0_OdtLevels = 0x0; - memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_RankEnable = 0x1; memupd->FspmConfig.Ch1_DeviceWidth = 0x1; - memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_DramDensity = 0x0; memupd->FspmConfig.Ch1_Option = 0x3; - memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_OdtConfig = 0x1; memupd->FspmConfig.Ch1_TristateClk1 = 0x0; memupd->FspmConfig.Ch1_Mode2N = 0x0; memupd->FspmConfig.Ch1_OdtLevels = 0x0; - memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_RankEnable = 0x0; memupd->FspmConfig.Ch2_DeviceWidth = 0x1; - memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_DramDensity = 0x0; memupd->FspmConfig.Ch2_Option = 0x3; memupd->FspmConfig.Ch2_OdtConfig = 0x0; memupd->FspmConfig.Ch2_TristateClk1 = 0x0; memupd->FspmConfig.Ch2_Mode2N = 0x0; memupd->FspmConfig.Ch2_OdtLevels = 0x0; - memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_RankEnable = 0x0; memupd->FspmConfig.Ch3_DeviceWidth = 0x1; - memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_DramDensity = 0x0; memupd->FspmConfig.Ch3_Option = 0x3; memupd->FspmConfig.Ch3_OdtConfig = 0x0; memupd->FspmConfig.Ch3_TristateClk1 = 0x0; memupd->FspmConfig.Ch3_Mode2N = 0x0; memupd->FspmConfig.Ch3_OdtLevels = 0x0; - memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x3; memupd->FspmConfig.MrcDataSaving = 0x0; - memupd->FspmConfig.MrcFastBoot = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x1; memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, sizeof(Ch0_Bit_swizzling)); @@ -114,6 +115,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, sizeof(Ch3_Bit_swizzling)); - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; memupd->FspmConfig.MsgLevelMask = 0x0; }

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Patch set updated for coreboot: mainboard/google/poppy: Enable Realtek 5663 support
by Rizwan Qureshi 08 Feb '17

08 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18216 -gerrit commit 7545c07e537a311d76cb7a94ac4ae124ee8bb2f6 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Feb 7 21:11:45 2017 +0530 mainboard/google/poppy: Enable Realtek 5663 support Enable Realtek RT5663 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=With required driver support in kernel verify audio on headset Change-Id: I9b9eb1e7edca56870f5be0e4fd603c9b0dc7f9de Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 88ee84f..38d58c7 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -231,6 +231,14 @@ chip soc/intel/skylake register "name" = ""MAXL"" device i2c 3A on end end + chip drivers/i2c/generic + register "hid" = ""10EC5663"" + register "name" = ""RT53"" + register "desc" = ""Realtek RT5663"" + register "irq" = "IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "probed" = "1" + device i2c 13 on end + end end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on

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Patch set updated for coreboot: mainboard/google/poppy: Enable Maxim 98927 codec
by Rizwan Qureshi 08 Feb '17

08 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18215 -gerrit commit 23a5e55f22caaa98813ba00975f860f085160b49 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:22:42 2017 +0530 mainboard/google/poppy: Enable Maxim 98927 codec Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=with required driver support in kernel verfy audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Dylan Reid <dgreid(a)chromium.org> --- src/mainboard/google/poppy/Kconfig | 3 +++ src/mainboard/google/poppy/devicetree.cb | 17 ++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index e889e01..42fdf25 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -20,6 +20,9 @@ config CHROMEOS config DRIVERS_I2C_GENERIC def_bool y +config DRIVERS_I2C_MAX98927 + def_bool y + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index a9e0cef..88ee84f 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -216,7 +216,22 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 + device pci 19.1 on + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "uid" = "0" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 39 on end + end + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "uid" = "1" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 3A on end + end + end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi

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Patch set updated for coreboot: mainboard/google/poppy: Generate required nhlt table
by Rizwan Qureshi 08 Feb '17

08 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18214 -gerrit commit cfcdedbbf0094dbf8b5f9f112c4a6c56d23911eb Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:30:01 2017 +0530 mainboard/google/poppy: Generate required nhlt table poppy board uses Maxim 98927 speaker codec and Realtek RT5663 for heaset. Select the apropriate NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for codec and the supported topology in poppy. BUG=None BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-boards mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 6 ++++ src/mainboard/google/poppy/mainboard.c | 55 ++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 742eb64..e889e01 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -41,4 +41,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH + select NHLT_DMIC_4CH + select NHLT_RT5663 + select NHLT_MAX98927 endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 29559b3..f71ba9e 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -14,19 +14,74 @@ */ #include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nhlt.h> + +static const char *oem_id_maxim = "GOOGLE"; +static const char *oem_table_id_maxim = "POPPYMAX"; static void mainboard_init(device_t dev) { mainboard_ec_init(); } + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; + uint32_t oem_revision = 0; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + /*ToDo as im getting error, i'm reverting to old codecs*/ + /* MAXIM98927 Smart Amps for left and right channel */ + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)){ + + printk(BIOS_ERR, "Couldn't add max98927\n"); + oem_id = oem_id_maxim; + oem_table_id = oem_table_id_maxim; + + } + + /* RT5663 Headset codec. */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id, oem_revision); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
by Rizwan Qureshi 08 Feb '17

08 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18213 -gerrit commit 021207d655ecc3c64aadd05cb5aeb4fd8c5b58ec Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sat Jan 14 06:08:21 2017 +0530 soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support Add APIs and required parameters for creating Maxim 98927 and Realtek 5336 SSP endpoints in NHLT table. Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> --- src/soc/intel/skylake/Kconfig | 13 ++++++ src/soc/intel/skylake/include/soc/nhlt.h | 12 ++++++ src/soc/intel/skylake/nhlt/Makefile.inc | 14 ++++++- src/soc/intel/skylake/nhlt/max98927.c | 47 +++++++++++++++++++++ src/soc/intel/skylake/nhlt/rt5663.c | 71 ++++++++++++++++++++++++++++++++ 5 files changed, 156 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24c2e30..8f29b2b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select ACPI_NHLT config MAINBOARD_USES_FSP2_0 bool @@ -227,6 +228,18 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config NHLT_RT5663 + bool + default n + help + Include DSP firmware settings for rt5663 headset codec. + +config NHLT_MAX98927 + bool + default n + help + Include DSP firmware settings for max98927 amplifier. + config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 008dd0d..7d23102 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -60,4 +60,16 @@ int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink); */ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +/* + * Add rt5663 headset codec on provided SSP link. Return 0 on succes, < 0 + * on error. + */ +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink); + +/* + * Add max98927 amplifier in stereo configuration on provide SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); + #endif diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index e022482..da71162 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -2,9 +2,11 @@ ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c ramstage-y += ssm4567.c +ramstage-y += rt5663.c +ramstage-y += max98927.c # DSP firmware settings files. -NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/kabylake/nhlt-blobs DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin @@ -13,6 +15,8 @@ NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin +RT5663 = rt5663-2ch-48khz-24b.bin +MAX98927_RENDER = max98927-render-2ch-48khz-24b.bin cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) @@ -45,3 +49,11 @@ $(SSM4567_RENDER)-type := raw cbfs-files-$(CONFIG_NHLT_SSM4567) += $(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-type := raw + +cbfs-files-$(CONFIG_NHLT_RT5663) += $(RT5663) +$(RT5663)-file := $(NHLT_BLOB_PATH)/$(RT5663) +$(RT5663)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98927) += $(MAX98927_RENDER) +$(MAX98927_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98927_RENDER) +$(MAX98927_RENDER)-type := raw diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c new file mode 100644 index 0000000..7f18657 --- /dev/null +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation.. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +static const struct nhlt_format_config max98927_render_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98927-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98927_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98927_render_formats, + .num_formats = ARRAY_SIZE(max98927_render_formats), + }, +}; + +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98927_descriptors, + ARRAY_SIZE(max98927_descriptors)); +} diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c new file mode 100644 index 0000000..603d1dd --- /dev/null +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +/* The same DSP firmware settings are used for both the capture and + * render endpoints. */ +static const struct nhlt_format_config rt5663_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "rt5663-2ch-48khz-24b.bin", + }, +}; + +/* The rt5663 just has headphones and a mic. Both the capture and render + * endpoints occupy the same virtual slot. */ +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor rt5663_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, +}; + +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5663_descriptors, + ARRAY_SIZE(rt5663_descriptors)); +}

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coreboot-gerrit February 2017