Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18310
-gerrit
commit 9a60116d749fa91ffce113b22fc1f3b5d572c16c
Author: Nicola Corna <nicola(a)corna.info>
Date: Tue Jan 24 12:42:36 2017 +0100
[RFC] Revert "drivers/pc80/tpm: Set default TPM acpi path if unset"
This reverts commit 3a1fbeaf6608d56b1fce2dfb88c76821b05849db.
Commit 3a1fbeaf6608d56b1fce2dfb88c76821b05849db introduced new bugs:
* On X220 it breaks the brightness control: GNOME is now unable to
control the brightness and the only way to control it is trough
the physical buttons (but GNOME is unaware of this, as no popup
appears).
* On X201 it breaks the CPU governor: no governors are available
in the sysfs.
Change-Id: I59de336af4cdfa5f6e8d56fa49025bc43a8264da
Signed-off-by: Nicola Corna <nicola(a)corna.info>
---
src/drivers/pc80/tpm/tpm.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index 83dc923..57ea919 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -875,10 +875,8 @@ static void lpc_tpm_fill_ssdt(struct device *dev)
struct opregion opreg = OPREGION("TREG", SYSTEMMEMORY,
CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000);
- if (!path) {
- path = "PCI0.LPCB";
- printk(BIOS_DEBUG, "Using default TPM ACPI path: '%s'\n", path);
- }
+ if (!path)
+ return;
/* Device */
acpigen_write_scope(path);
the following patch was just integrated into master:
commit d09dc6b442415d3dd0753483e4d4d72ce26ce56e
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Feb 3 12:45:21 2017 -0800
cbmem_console: Remove "buffer_" prefix from all structure fields
Shorten field names of struct cbmem_console since saying "buffer_" in
front of everything is redundant and we can use the gained space to save
some line breaks in the code later. This also aligns the definition with
the version in libpayload.
Change-Id: I160ad1f39b719ac7e912d0466c82a58013cca0f9
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/18299 for details.
-gerrit
the following patch was just integrated into master:
commit 24de3a37fb0de624817280f57756c562af888535
Author: Aamir Bohra <aamir.bohra(a)intel.com>
Date: Thu Feb 2 22:05:02 2017 +0530
vendorcode/intel/skykabylake: Update FSP UPD header files
Update FSP UPD header files as per version 1.6.0.
Below UPDs are added to FspsUpd.h:
* DelayUsbPdoProgramming
* MeUnconfigIsValid
* CpuS3ResumeDataSize
* CpuS3ResumeData
CQ-DEPEND=CL:*322871,CL:*323186,CL:*322870
BUG=None
BRANCH=None
TEST=Build and boot on RVP3 and poppy
Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
Reviewed-on: https://review.coreboot.org/18289
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/18289 for details.
-gerrit
the following patch was just integrated into master:
commit 6ff7e8f550df1ef05e93546892888b66c132ae31
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Fri Feb 3 13:28:46 2017 +0530
vendorcode/intel/skykabylake: Update CpuConfigFspData.h file
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
Reviewed-on: https://review.coreboot.org/18285
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18285 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18285
-gerrit
commit 1ca611d506a6a942723a1ede612900b2794c1211
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Fri Feb 3 13:28:46 2017 +0530
vendorcode/intel/skykabylake: Update CpuConfigFspData.h file
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
---
.../intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
index 8fd41e0..c8cdc5f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
@@ -62,9 +62,9 @@ typedef union {
UINT32 TxtEnable : 1;
UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
UINT32 RsvdBits : 15; ///< Reserved for future use
- EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
+ UINT32 Reserved;
} Bits;
- UINT32 Uint32[3];
+ UINT32 Uint32[2];
} CPU_CONFIG_FSP_DATA;
#pragma pack (pop)
Jenny Tc (jenny.tc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18307
-gerrit
commit f5e24e30a4189739bfe81713a3ea01d71a9c7a56
Author: Jenny TC <jenny.tc(a)intel.com>
Date: Tue Feb 7 14:16:54 2017 +0530
intel/skylake: Set FADT.8042 on CONFIG_DRIVERS_PS2_KEYBOARD
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, FADT 8042 flag is set only if
CONFIG_DRIVERS_PS2_KEYBOARD is enabled in the coreboot.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Signed-off-by: Jenny TC <jenny.tc(a)intel.com>
---
src/soc/intel/skylake/acpi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 54468d2..8488f52 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -268,7 +268,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+ if (IS_ENABLED(CONFIG_DRIVERS_PS2_KEYBOARD))
+ fadt->iapc_boot_arch |= ACPI_FADT_8042;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
the following patch was just integrated into master:
commit 0254c2d99fc7a5858be4826c576ca743d005b213
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Feb 3 16:09:45 2017 -0600
southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BIN
The apollolake boards don't have an me.bin proper, but they still have
descriptor regions which need to be locked down. Therefore, remove the
restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE.
BUG=chrome-os-partner:62177
TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE.
Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18304
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18304 for details.
-gerrit