coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: dump CSE status
by Aaron Durbin 07 Feb '17

07 Feb '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18303 -gerrit commit f755fe685fd1aa559e326c1aff8dc1631e36e0c5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 7 11:33:56 2017 -0600 soc/intel/apollolake: dump CSE status Dump the CSE status registers for potential debugging purposes. Explicitly call out manufacturing mode of the part since it's important shipping devices ensure manufacturing mode is locked down. Intel is planning on writing a common driver so a complete status -> string dumps was not done because (surprise surprise) not all the fields are equal with previous implementations. BUG=chrome-os-partner:62177 BRANCH=reef TEST=Booted and noted dump of CSE status registers. Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/cse.c | 57 +++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5a65f43..df93f0b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -57,6 +57,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += cse.c ramstage-y += elog.c ramstage-y += flash_ctrlr.c ramstage-y += dsp.c diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c new file mode 100644 index 0000000..b8ab1f0 --- /dev/null +++ b/src/soc/intel/apollolake/cse.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +#define PCI_ME_HFSTS1 0x40 +#define PCI_ME_HFSTS2 0x48 +#define PCI_ME_HFSTS3 0x60 +#define PCI_ME_HFSTS4 0x64 +#define PCI_ME_HFSTS5 0x68 +#define PCI_ME_HFSTS6 0x6c + +static uint32_t dump_status(int index, int reg_addr) +{ + uint32_t reg = pci_read_config32(CSE_DEV, reg_addr); + + printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); + + return reg; +} + +static void dump_cse_state(void *unused) +{ + uint32_t fwsts1; + + fwsts1 = dump_status(1, PCI_ME_HFSTS1); + dump_status(2, PCI_ME_HFSTS2); + dump_status(3, PCI_ME_HFSTS3); + dump_status(4, PCI_ME_HFSTS4); + dump_status(5, PCI_ME_HFSTS5); + dump_status(6, PCI_ME_HFSTS6); + + /* Minimal decoding is done here in order to call out most important + pieces. Manufacturing mode needs to be locked down prior to shipping + the product so it's called out explicitly. */ + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + (fwsts1 & (1 << 0x4)) ? "YES" : "NO"); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, dump_cse_state, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, dump_cse_state, NULL);

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New patch to review for coreboot: southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BIN
by Aaron Durbin 07 Feb '17

07 Feb '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18304 -gerrit commit c72149782e4c0dc54f06529bd03100f7aad2457b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 3 16:09:45 2017 -0600 southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BIN The apollolake boards don't have an me.bin proper, but they still have descriptor regions which need to be locked down. Therefore, remove the restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE. BUG=chrome-os-partner:62177 TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE. Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/common/firmware/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index af26b2d..da40db0 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -165,7 +165,6 @@ config IFD_PLATFORM_SECTION config LOCK_MANAGEMENT_ENGINE bool "Lock ME/TXE section" - depends on HAVE_ME_BIN default n help The Intel Firmware Descriptor supports preventing write accesses

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New patch to review for coreboot: soc/intel/apollolake: dump CSE status
by Aaron Durbin 07 Feb '17

07 Feb '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18303 -gerrit commit 1b5fb23f31d8a6a77bc4d12e17e31c0d288bddc6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 7 11:33:56 2017 -0600 soc/intel/apollolake: dump CSE status Dump the CSE status registers for potential debuggin purposes. Explicitly call out manufacturing mode of the part since it's important shipping devices ensure manufacturing mode is locked down. Intel is planning on writing a common driver so a complete status -> string dumps was not done because (surprise surprise) not all the fields are equal with previous implementations. BUG=chrome-os-partner:62177 BRANCH=reef TEST=Booted and noted dump of CSE status registers. Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/cse.c | 57 +++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5a65f43..df93f0b 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -57,6 +57,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += cse.c ramstage-y += elog.c ramstage-y += flash_ctrlr.c ramstage-y += dsp.c diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c new file mode 100644 index 0000000..b8ab1f0 --- /dev/null +++ b/src/soc/intel/apollolake/cse.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +#define PCI_ME_HFSTS1 0x40 +#define PCI_ME_HFSTS2 0x48 +#define PCI_ME_HFSTS3 0x60 +#define PCI_ME_HFSTS4 0x64 +#define PCI_ME_HFSTS5 0x68 +#define PCI_ME_HFSTS6 0x6c + +static uint32_t dump_status(int index, int reg_addr) +{ + uint32_t reg = pci_read_config32(CSE_DEV, reg_addr); + + printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); + + return reg; +} + +static void dump_cse_state(void *unused) +{ + uint32_t fwsts1; + + fwsts1 = dump_status(1, PCI_ME_HFSTS1); + dump_status(2, PCI_ME_HFSTS2); + dump_status(3, PCI_ME_HFSTS3); + dump_status(4, PCI_ME_HFSTS4); + dump_status(5, PCI_ME_HFSTS5); + dump_status(6, PCI_ME_HFSTS6); + + /* Minimal decoding is done here in order to call out most important + pieces. Manufacturing mode needs to be locked down prior to shipping + the product so it's called out explicitly. */ + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + (fwsts1 & (1 << 0x4)) ? "YES" : "NO"); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, dump_cse_state, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, dump_cse_state, NULL);

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Patch merged into coreboot/master: ec/google/chromeec: let platform prepare for reboot when resetting EC
by gerrit＠coreboot.org 07 Feb '17

07 Feb '17

the following patch was just integrated into master: commit 96a4317fa9543a0d07e34bae3d40da810554411f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Feb 6 10:08:45 2017 -0600 ec/google/chromeec: let platform prepare for reboot when resetting EC This fixes an issue on systems where the S3 state in the pm1 control registers are not cleared when vboot determines recovery mode is required on an S3 resume. The EC code will reboot the system knowing that the EC was in RW. However, on subsequent entry into romstage the S3 path will be taken and fails to recover cbmem -- forcing another reboot. To work around that, signal to the platform a reboot is happening and let the platform perform the necessary fix ups to the register state. BUG=chrome-os-partner:62627 Change-Id: Ic144b11b4968c92a1273b8d9eb9dc10f0056bf3d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/18295 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18295 for details. -gerrit

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Patch set updated for coreboot: vendorcode/intel/skykabylake: Update FSP UPD header files
by Aamir Bohra 07 Feb '17

07 Feb '17

Aamir Bohra (aamir.bohra(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18289 -gerrit commit 406b10d893450b674c8df1469843ddb45092ce83 Author: Aamir Bohra <aamir.bohra(a)intel.com> Date: Thu Feb 2 22:05:02 2017 +0530 vendorcode/intel/skykabylake: Update FSP UPD header files Update FSP UPD header files as per version 1.6.0. Below UPDs are added to FspsUpd.h: * DelayUsbPdoProgramming * MeUnconfigIsValid * CpuS3ResumeDataSize * CpuS3ResumeData CQ-DEPEND=CL:*322871,CL:*323186,CL:*322870 BUG=None BRANCH=None TEST=Build and boot on RVP3 and poppy Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/FspUpd.h | 2 +- .../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 5 ++- .../intel/fsp/fsp2_0/skykabylake/FspsUpd.h | 49 ++++++++++++++++------ 3 files changed, 41 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h index 4981f21..bea3509 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h index 3e65f0a..89dc419 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -773,7 +773,8 @@ typedef struct { UINT8 HyperThreading; /** Offset 0x02D4 - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. + Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. @note If disabled, + BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting. $EN_DIS **/ UINT8 CpuRatioOverride; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h index 0120cf8..f2cc9b4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -363,9 +363,16 @@ typedef struct { **/ UINT8 PchLanEnable; -/** Offset 0x00FC +/** Offset 0x00FC - Delay USB PDO Programming + Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: + disable, 1: enable + $EN_DIS +**/ + UINT8 DelayUsbPdoProgramming; + +/** Offset 0x00FD **/ - UINT8 UnusedUpdSpace3[24]; + UINT8 UnusedUpdSpace3[23]; /** Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for @@ -739,7 +746,7 @@ typedef struct { UINT8 SendVrMbxCmd1; /** Offset 0x02E4 - CpuS3ResumeMtrrData - Pointer CPU S3 Resume MTRR Data + Pointer to CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData; @@ -2041,9 +2048,15 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0779 +/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid + The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. + $EN_DIS +**/ + UINT8 MeUnconfigIsValid; + +/** Offset 0x077A **/ - UINT8 ReservedFspsUpd[7]; + UINT8 ReservedFspsUpd[6]; } FSP_S_CONFIG; /** Fsp S Test Configuration @@ -2517,14 +2530,16 @@ typedef struct { **/ UINT8 C1e; -/** Offset 0x07DA - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. Disable; 1: Enable +/** Offset 0x07DA - Enable or Disable Package C-State Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; 2: Auto + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable +/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion + Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; 2: Auto + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateUnDemotion; @@ -2772,11 +2787,21 @@ typedef struct { **/ UINT16 PsysPmax; -/** Offset 0x087E - ReservedCpuPostMemTest +/** Offset 0x087E - CpuS3ResumeDataSize + Size of CPU S3 Resume Data +**/ + UINT16 CpuS3ResumeDataSize; + +/** Offset 0x0880 - CpuS3ResumeData + Pointer to CPU S3 Resume Data +**/ + UINT32 CpuS3ResumeData; + +/** Offset 0x0884 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[12]; + UINT8 ReservedCpuPostMemTest[6]; /** Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values

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Patch set updated for coreboot: vendorcode/intel/skykabylake: Update FSP UPD header files
by Aamir Bohra 07 Feb '17

07 Feb '17

Aamir Bohra (aamir.bohra(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18289 -gerrit commit 7bd39aec4ddcf4d88ba8be35cf8622a170e2978e Author: Aamir Bohra <aamir.bohra(a)intel.com> Date: Thu Feb 2 22:05:02 2017 +0530 vendorcode/intel/skykabylake: Update FSP UPD header files Update FSP UPD header files as per version 1.6.0. Below UPDs have been added to FspsUpd.h: * DelayUsbPdoProgramming * MeUnconfigIsValid * CpuS3ResumeDataSize * CpuS3ResumeData CQ-DEPEND=CL:*322871,CL:*323186,CL:*322870 BUG=None BRANCH=None TEST=Build and boot on RVP3 and poppy Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/FspUpd.h | 2 +- .../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 5 ++- .../intel/fsp/fsp2_0/skykabylake/FspsUpd.h | 49 ++++++++++++++++------ 3 files changed, 41 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h index 4981f21..bea3509 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h index 3e65f0a..89dc419 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -773,7 +773,8 @@ typedef struct { UINT8 HyperThreading; /** Offset 0x02D4 - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. + Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. @note If disabled, + BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting. $EN_DIS **/ UINT8 CpuRatioOverride; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h index 0120cf8..f2cc9b4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved. +Copyright (c) 2017, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -363,9 +363,16 @@ typedef struct { **/ UINT8 PchLanEnable; -/** Offset 0x00FC +/** Offset 0x00FC - Delay USB PDO Programming + Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: + disable, 1: enable + $EN_DIS +**/ + UINT8 DelayUsbPdoProgramming; + +/** Offset 0x00FD **/ - UINT8 UnusedUpdSpace3[24]; + UINT8 UnusedUpdSpace3[23]; /** Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for @@ -739,7 +746,7 @@ typedef struct { UINT8 SendVrMbxCmd1; /** Offset 0x02E4 - CpuS3ResumeMtrrData - Pointer CPU S3 Resume MTRR Data + Pointer to CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData; @@ -2041,9 +2048,15 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0779 +/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid + The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. + $EN_DIS +**/ + UINT8 MeUnconfigIsValid; + +/** Offset 0x077A **/ - UINT8 ReservedFspsUpd[7]; + UINT8 ReservedFspsUpd[6]; } FSP_S_CONFIG; /** Fsp S Test Configuration @@ -2517,14 +2530,16 @@ typedef struct { **/ UINT8 C1e; -/** Offset 0x07DA - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. Disable; 1: Enable +/** Offset 0x07DA - Enable or Disable Package C-State Demotion + Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; 2: Auto + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable +/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion + Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; 2: Auto + (Auto: Enabled for Skylake; Disabled for Kabylake) $EN_DIS **/ UINT8 PkgCStateUnDemotion; @@ -2772,11 +2787,21 @@ typedef struct { **/ UINT16 PsysPmax; -/** Offset 0x087E - ReservedCpuPostMemTest +/** Offset 0x087E - CpuS3ResumeDataSize + Size of CPU S3 Resume Data +**/ + UINT16 CpuS3ResumeDataSize; + +/** Offset 0x0880 - CpuS3ResumeData + Pointer to CPU S3 Resume Data +**/ + UINT32 CpuS3ResumeData; + +/** Offset 0x0884 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[12]; + UINT8 ReservedCpuPostMemTest[6]; /** Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values

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Patch set updated for coreboot: nb/i945/gma.c: Change name and type of mmiobase in functions argument
by Arthur Heymans 07 Feb '17

07 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18293 -gerrit commit 0348a772b517799952c99fb5e0498c3fb2297887 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 6 13:47:21 2017 +0100 nb/i945/gma.c: Change name and type of mmiobase in functions argument Void pointer arithmetics are forbidden in standard C but GCC has an extension that allows it. Change-Id: I43029b2ab2f7709b8e1ba85eb05c31341b8ac16f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 270 +++++++++++++++++++-------------------- 1 file changed, 135 insertions(+), 135 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b9a37e4..0d4ca43 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -47,7 +47,7 @@ #define BASE_FREQUENCY 100000 -static int gtt_setup(void *mmiobase) +static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; unsigned long tom; // top of memory @@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) + u8 *mmiobase, unsigned int pgfx) { struct edid edid; struct edid_mode *mode; @@ -100,9 +100,9 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", - (void *)pgfx, pmmio, piobase, pphysbase); + (void *)pgfx, mmiobase, piobase, pphysbase); - intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, + intel_gmbus_read_edid(mmiobase + GMBUS0, 3, 0x50, edid_data, sizeof(edid_data)); decode_edid(edid_data, sizeof(edid_data), &edid); mode = &edid.mode; @@ -123,41 +123,41 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, for (i = 0; i < 2; i++) for (j = 0; j < 0x100; j++) /* R = j, G = j, B = j. */ - write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); + write32(mmiobase + PALETTE(i) + 4 * j, 0x10101 * j); - write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmiobase + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmiobase + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + write32(mmiobase + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); /* Clean registers. */ for (i = 0; i < 0x20; i += 4) - write32(pmmio + RENDER_RING_BASE + i, 0); + write32(mmiobase + RENDER_RING_BASE + i, 0); for (i = 0; i < 0x20; i += 4) - write32(pmmio + FENCE_REG_965_0 + i, 0); - write32(pmmio + PP_ON_DELAYS, 0); - write32(pmmio + PP_OFF_DELAYS, 0); + write32(mmiobase + FENCE_REG_965_0 + i, 0); + write32(mmiobase + PP_ON_DELAYS, 0); + write32(mmiobase + PP_OFF_DELAYS, 0); /* Disable VGA. */ - write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE); /* Disable pipes. */ - write32(pmmio + PIPECONF(0), 0); - write32(pmmio + PIPECONF(1), 0); + write32(mmiobase + PIPECONF(0), 0); + write32(mmiobase + PIPECONF(1), 0); /* Init PRB0. */ - write32(pmmio + HWS_PGA, 0x352d2000); - write32(pmmio + PRB0_CTL, 0); - write32(pmmio + PRB0_HEAD, 0); - write32(pmmio + PRB0_TAIL, 0); - write32(pmmio + PRB0_START, 0); - write32(pmmio + PRB0_CTL, 0x0001f001); - - write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF + write32(mmiobase + HWS_PGA, 0x352d2000); + write32(mmiobase + PRB0_CTL, 0); + write32(mmiobase + PRB0_HEAD, 0); + write32(mmiobase + PRB0_TAIL, 0); + write32(mmiobase + PRB0_START, 0); + write32(mmiobase + PRB0_CTL, 0x0001f001); + + write32(mmiobase + D_STATE, DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); - write32(pmmio + ECOSKPD, 0x00010000); - write32(pmmio + HWSTAM, 0xeffe); - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + write32(mmiobase + ECOSKPD, 0x00010000); + write32(mmiobase + HWSTAM, 0xeffe); + write32(mmiobase + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(mmiobase + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); /* p2 divisor must 7 for dual channel LVDS */ /* and 14 for single channel LVDS */ @@ -219,32 +219,32 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { /* Disable panel fitter (we're in native resolution). */ - write32(pmmio + PF_CTL(0), 0); - write32(pmmio + PF_WIN_SZ(0), 0); - write32(pmmio + PF_WIN_POS(0), 0); - write32(pmmio + PFIT_PGM_RATIOS, 0); - write32(pmmio + PFIT_CONTROL, 0); + write32(mmiobase + PF_CTL(0), 0); + write32(mmiobase + PF_WIN_SZ(0), 0); + write32(mmiobase + PF_WIN_POS(0), 0); + write32(mmiobase + PFIT_PGM_RATIOS, 0); + write32(mmiobase + PFIT_CONTROL, 0); } else { - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(pmmio + PF_WIN_POS(0), 0); - write32(pmmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(pmmio + PFIT_CONTROL, PFIT_ENABLE + write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmiobase + PF_WIN_POS(0), 0); + write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmiobase + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE); } mdelay(1); - write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + write32(mmiobase + DSPCNTR(0), DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), + write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmiobase + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmiobase + FP0(1), (pixel_n << 16) | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), + write32(mmiobase + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 @@ -254,7 +254,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, : 0) | (0x10000 << (pixel_p1 - 1))); mdelay(1); - write32(pmmio + DPLL(1), + write32(mmiobase + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 @@ -262,88 +262,88 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) | (0x10000 << (pixel_p1 - 1))); mdelay(1); - write32(pmmio + HTOTAL(1), + write32(mmiobase + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); - write32(pmmio + HBLANK(1), + write32(mmiobase + HBLANK(1), ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1)); - write32(pmmio + HSYNC(1), + write32(mmiobase + HSYNC(1), ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1)); - write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) + write32(mmiobase + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); - write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) + write32(mmiobase + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1)); - write32(pmmio + VSYNC(1), + write32(mmiobase + VSYNC(1), ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { - write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) + write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); } else { - write32(pmmio + PIPESRC(1), (639 << 16) | 399); + write32(mmiobase + PIPESRC(1), (639 << 16) | 399); } mdelay(1); - write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); - write32(pmmio + DSPPOS(0), 0); + write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(mmiobase + DSPPOS(0), 0); /* Backlight init. */ - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC, 0x011d011a); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + FW_BLC_SELF, 0x0001003f); - write32(pmmio + FW_BLC, 0x011d0109); - write32(pmmio + FW_BLC2, 0x00000102); - write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); + write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(mmiobase + FW_BLC, 0x011d011a); + write32(mmiobase + FW_BLC2, 0x00000102); + write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(mmiobase + FW_BLC_SELF, 0x0001003f); + write32(mmiobase + FW_BLC, 0x011d0109); + write32(mmiobase + FW_BLC2, 0x00000102); + write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(mmiobase + BLC_PWM_CTL, conf->gpu_backlight); edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - write32(pmmio + DSPADDR(0), 0); - write32(pmmio + DSPSURF(0), 0); - write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + write32(mmiobase + DSPADDR(0), 0); + write32(mmiobase + DSPSURF(0), 0); + write32(mmiobase + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); - write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); - write32(pmmio + LVDS, LVDS_ON + write32(mmiobase + PIPECONF(1), PIPECONF_ENABLE); + write32(mmiobase + LVDS, LVDS_ON | (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_A_POWERUP_ALL | LVDS_PIPE(1)); - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); mdelay(1); - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET); printk (BIOS_DEBUG, "waiting for panel powerup\n"); while (1) { u32 reg32; - reg32 = read32(pmmio + PP_STATUS); + reg32 = read32(mmiobase + PP_STATUS); if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) break; } printk (BIOS_DEBUG, "panel powered up\n"); - write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + write32(mmiobase + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); /* Clear interrupts. */ - write32(pmmio + DEIIR, 0xffffffff); - write32(pmmio + SDEIIR, 0xffffffff); - write32(pmmio + IIR, 0xffffffff); - write32(pmmio + IMR, 0xffffffff); - write32(pmmio + EIR, 0xffffffff); + write32(mmiobase + DEIIR, 0xffffffff); + write32(mmiobase + SDEIIR, 0xffffffff); + write32(mmiobase + IIR, 0xffffffff); + write32(mmiobase + IMR, 0xffffffff); + write32(mmiobase + EIR, 0xffffffff); - if (gtt_setup(pmmio)) { + if (gtt_setup(mmiobase)) { printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); return 0; } @@ -363,7 +363,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, outl(pphysbase + (i << 12) + 1, piobase + 4); } - temp = read32(pmmio + PGETBL_CTL); + temp = read32(mmiobase + PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); if (temp & 1) @@ -380,8 +380,8 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, } else { vga_misc_write(0x67); - write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); - write32(pmmio + VGACNTRL, 0x02c4008e + write32(mmiobase + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); + write32(mmiobase + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT); vga_textmode_init(); @@ -391,38 +391,38 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) + u8 *mmiobase, unsigned int pgfx) { int i; u32 hactive, vactive; u16 reg16; u32 uma_size; - printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", - (u32)pmmio, piobase, pphysbase); + printk(BIOS_SPEW, "mmiobase %x addrport %x physbase %x\n", + (u32)mmiobase, piobase, pphysbase); - gtt_setup(pmmio); + gtt_setup(mmiobase); /* Disable VGA. */ - write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE); /* Disable pipes. */ - write32(pmmio + PIPECONF(0), 0); - write32(pmmio + PIPECONF(1), 0); + write32(mmiobase + PIPECONF(0), 0); + write32(mmiobase + PIPECONF(1), 0); - write32(pmmio + INSTPM, 0x800); + write32(mmiobase + INSTPM, 0x800); vga_gr_write(0x18, 0); - write32(pmmio + VGA0, 0x200074); - write32(pmmio + VGA1, 0x200074); + write32(mmiobase + VGA0, 0x200074); + write32(mmiobase + VGA1, 0x200074); - write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); - write32(pmmio + DSPCLK_GATE_D, 0); - write32(pmmio + FW_BLC, 0x03060106); - write32(pmmio + FW_BLC2, 0x00000306); + write32(mmiobase + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); + write32(mmiobase + DSPCLK_GATE_D, 0); + write32(mmiobase + FW_BLC, 0x03060106); + write32(mmiobase + FW_BLC2, 0x00000306); - write32(pmmio + ADPA, ADPA_DAC_ENABLE + write32(mmiobase + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE @@ -430,12 +430,12 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, | ADPA_DPMS_ON ); - write32(pmmio + 0x7041c, 0x0); + write32(mmiobase + 0x7041c, 0x0); - write32(pmmio + DPLL_MD(0), 0x3); - write32(pmmio + DPLL_MD(1), 0x3); - write32(pmmio + DSPCNTR(1), 0x1000000); - write32(pmmio + PIPESRC(1), 0x027f01df); + write32(mmiobase + DPLL_MD(0), 0x3); + write32(mmiobase + DPLL_MD(1), 0x3); + write32(mmiobase + DSPCNTR(1), 0x1000000); + write32(mmiobase + PIPESRC(1), 0x027f01df); vga_misc_write(0x67); const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, @@ -454,21 +454,21 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, vactive = 400; mdelay(1); - write32(pmmio + DPLL(0), + write32(mmiobase + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 | 0x400601 ); mdelay(1); - write32(pmmio + DPLL(0), + write32(mmiobase + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 | 0x400601 ); - write32(pmmio + ADPA, ADPA_DAC_ENABLE + write32(mmiobase + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE @@ -476,46 +476,46 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, | ADPA_DPMS_ON ); - write32(pmmio + HTOTAL(0), + write32(mmiobase + HTOTAL(0), ((hactive - 1) << 16) | (hactive - 1)); - write32(pmmio + HBLANK(0), + write32(mmiobase + HBLANK(0), ((hactive - 1) << 16) | (hactive - 1)); - write32(pmmio + HSYNC(0), + write32(mmiobase + HSYNC(0), ((hactive - 1) << 16) | (hactive - 1)); - write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) + write32(mmiobase + VTOTAL(0), ((vactive - 1) << 16) | (vactive - 1)); - write32(pmmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmiobase + VBLANK(0), ((vactive - 1) << 16) | (vactive - 1)); - write32(pmmio + VSYNC(0), + write32(mmiobase + VSYNC(0), ((vactive - 1) << 16) | (vactive - 1)); - write32(pmmio + PF_WIN_POS(0), 0); + write32(mmiobase + PF_WIN_POS(0), 0); - write32(pmmio + PIPESRC(0), (639 << 16) | 399); - write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(pmmio + PFIT_CONTROL, 0x0); + write32(mmiobase + PIPESRC(0), (639 << 16) | 399); + write32(mmiobase + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmiobase + PFIT_CONTROL, 0x0); mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x00002040); + write32(mmiobase + FDI_RX_CTL(0), 0x00002040); mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x80002050); - write32(pmmio + FDI_TX_CTL(0), 0x00044000); + write32(mmiobase + FDI_RX_CTL(0), 0x80002050); + write32(mmiobase + FDI_TX_CTL(0), 0x00044000); mdelay(1); - write32(pmmio + FDI_TX_CTL(0), 0x80044000); - write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmiobase + FDI_TX_CTL(0), 0x80044000); + write32(mmiobase + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(pmmio + VGACNTRL, 0x0); - write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + write32(mmiobase + VGACNTRL, 0x0); + write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); mdelay(1); - write32(pmmio + ADPA, ADPA_DAC_ENABLE + write32(mmiobase + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE @@ -523,10 +523,10 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, | ADPA_DPMS_ON ); - write32(pmmio + DSPFW3, 0x7f3f00c1); - write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); - write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); - write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); + write32(mmiobase + DSPFW3, 0x7f3f00c1); + write32(mmiobase + MI_MODE, 0x200 | VS_TIMER_DISPATCH); + write32(mmiobase + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); + write32(mmiobase + CACHE_MODE_1, 0x380 & ~(1 << 9)); /* Set up GTT. */ @@ -544,11 +544,11 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, } /* Clear interrupts. */ - write32(pmmio + DEIIR, 0xffffffff); - write32(pmmio + SDEIIR, 0xffffffff); - write32(pmmio + IIR, 0xffffffff); - write32(pmmio + IMR, 0xffffffff); - write32(pmmio + EIR, 0xffffffff); + write32(mmiobase + DEIIR, 0xffffffff); + write32(mmiobase + SDEIIR, 0xffffffff); + write32(mmiobase + IIR, 0xffffffff); + write32(mmiobase + IMR, 0xffffffff); + write32(mmiobase + EIR, 0xffffffff); vga_textmode_init(); @@ -561,13 +561,13 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, /* compare the header of the vga edid header */ /* if vga is not connected it should have a correct header */ -static int probe_edid(u8 *pmmio, u8 slave) +static int probe_edid(u8 *mmiobase, u8 slave) { int i; u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(pmmio + GMBUS0, slave, 0x50, vga_edid, 128); - intel_gmbus_stop(pmmio + GMBUS0); + intel_gmbus_read_edid(mmiobase + GMBUS0, slave, 0x50, vga_edid, 128); + intel_gmbus_stop(mmiobase + GMBUS0); for (i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "No display connected on slave %d\n",

1 0

Patch set updated for coreboot: siemens/mc_apl1: Make basic settings for booting the mainboard
by Mario Scheithauer 07 Feb '17

07 Feb '17

Mario Scheithauer (mario.scheithauer(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18292 -gerrit commit 882ccfd215b04fd9bb5e92d4a13bcd6ef4b89674 Author: Mario Scheithauer <mario.scheithauer(a)siemens.com> Date: Mon Feb 6 13:03:52 2017 +0100 siemens/mc_apl1: Make basic settings for booting the mainboard This commit makes a basic adjustment for GPIOs, device tree, flash map and MRC settings. With these basic settings the mainboard boots into Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow. Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- src/mainboard/siemens/mc_apl1/brd_gpio.h | 38 ++--- src/mainboard/siemens/mc_apl1/devicetree.cb | 227 ++++------------------------ src/mainboard/siemens/mc_apl1/mc_apl1.fmd | 20 +-- src/mainboard/siemens/mc_apl1/romstage.c | 75 ++++----- 4 files changed, 93 insertions(+), 267 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h index 33b839b..564ee69 100644 --- a/src/mainboard/siemens/mc_apl1/brd_gpio.h +++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,11 +19,7 @@ #if ENV_ROMSTAGE static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ - PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ - PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ - PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ - + /* Debug tracing. */ PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), @@ -33,30 +30,25 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ - PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), - /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ - PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - - PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* Unused */ PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index ce01a8b..c82896c 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -4,221 +4,54 @@ chip soc/intel/apollolake device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports + register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "0" # MACPHY + register "pcie_rp3_clkreq_pin" = "1" # MACPHY register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, - }" - - # digitizer at 400kHz - register "i2c[5]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - device domain 0 on device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC + device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 off end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOM50C1_HID, - .cid = PNP0C50_CID, - .desc = WCOM_DT_DESC, - .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), - }" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 5 + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 device pci 17.2 off end # - I2C 6 - device pci 17.3 off end # - I2C 7 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 - device pci 1a.0 on end # - PWM + device pci 1a.0 off end # - PWM device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on end # - LPC device pci 1f.1 on end # - SMBUS diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 3da8467..432e8de 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,15 +1,16 @@ FLASH 16M { - WP_RO@0x0 0x400000 { + WP_RO@0x0 0xe00000 { SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { + IFWI@0x1000 0x23f000 + RO_VPD@0x240000 0x4000 + RO_SECTION@0x244000 0xbbc000 { FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x1bb000 - RO_UNUSED@0x1bc000 0x40000 + RO_UNUSED_1@0x800 0x800 + COREBOOT(CBFS)@0x1000 0xbb9000 + RO_UNUSED_2@0xbba000 0x1000 } } - MISC_RW@0x400000 0x30000 { + MISC_RW@0xe00000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -23,9 +24,8 @@ FLASH 16M { RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 + BIOS_UNUSABLE@0xe30000 0xcf000 + DEVICE_EXTENSION@0xeff000 0x100000 # Currently, it is required that the BIOS region be a multiple of 8KiB. # This is required so that the recovery mechanism can find SIGN_CSE # region aligned to 4K at the center of BIOS region. Since the diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 5c784ba..9dd42bc 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2016 Google Inc. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,28 +21,28 @@ #include "brd_gpio.h" static const uint8_t Ch0_Bit_swizzling[] = { - 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, - 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, - 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, - 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch1_Bit_swizzling[] = { - 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, - 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, - 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, - 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch2_Bit_swizzling[] = { - 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, - 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, - 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, - 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch3_Bit_swizzling[] = { - 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, - 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, - 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, - 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -51,59 +52,59 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; - memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.Profile = 0x19; memupd->FspmConfig.MemoryDown = 0x1; - memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LPageSize = 0x2; memupd->FspmConfig.DDR3LASR = 0x0; - memupd->FspmConfig.ScramblerSupport = 0x1; - memupd->FspmConfig.ChannelHashMask = 0x36; - memupd->FspmConfig.SliceHashMask = 0x9; - memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ScramblerSupport = 0x0; + memupd->FspmConfig.ChannelHashMask = 0x0; + memupd->FspmConfig.SliceHashMask = 0x0; + memupd->FspmConfig.InterleavedMode = 0x0; memupd->FspmConfig.ChannelsSlicesEnable = 0x0; - memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x1; memupd->FspmConfig.DualRankSupportEnable = 0x1; memupd->FspmConfig.RmtMode = 0x0; - memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.MemorySizeLimit = 0x1000; memupd->FspmConfig.LowMemoryMaxValue = 0x0; memupd->FspmConfig.DisableFastBoot = 0x0; memupd->FspmConfig.HighMemoryMaxValue = 0x0; memupd->FspmConfig.DIMM0SPDAddress = 0x0; memupd->FspmConfig.DIMM1SPDAddress = 0x0; - memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_RankEnable = 0x1; memupd->FspmConfig.Ch0_DeviceWidth = 0x1; - memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_DramDensity = 0x0; memupd->FspmConfig.Ch0_Option = 0x3; - memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_OdtConfig = 0x1; memupd->FspmConfig.Ch0_TristateClk1 = 0x0; memupd->FspmConfig.Ch0_Mode2N = 0x0; memupd->FspmConfig.Ch0_OdtLevels = 0x0; - memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_RankEnable = 0x1; memupd->FspmConfig.Ch1_DeviceWidth = 0x1; - memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_DramDensity = 0x0; memupd->FspmConfig.Ch1_Option = 0x3; - memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_OdtConfig = 0x1; memupd->FspmConfig.Ch1_TristateClk1 = 0x0; memupd->FspmConfig.Ch1_Mode2N = 0x0; memupd->FspmConfig.Ch1_OdtLevels = 0x0; - memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_RankEnable = 0x0; memupd->FspmConfig.Ch2_DeviceWidth = 0x1; - memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_DramDensity = 0x0; memupd->FspmConfig.Ch2_Option = 0x3; memupd->FspmConfig.Ch2_OdtConfig = 0x0; memupd->FspmConfig.Ch2_TristateClk1 = 0x0; memupd->FspmConfig.Ch2_Mode2N = 0x0; memupd->FspmConfig.Ch2_OdtLevels = 0x0; - memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_RankEnable = 0x0; memupd->FspmConfig.Ch3_DeviceWidth = 0x1; - memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_DramDensity = 0x0; memupd->FspmConfig.Ch3_Option = 0x3; memupd->FspmConfig.Ch3_OdtConfig = 0x0; memupd->FspmConfig.Ch3_TristateClk1 = 0x0; memupd->FspmConfig.Ch3_Mode2N = 0x0; memupd->FspmConfig.Ch3_OdtLevels = 0x0; - memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x3; memupd->FspmConfig.MrcDataSaving = 0x0; - memupd->FspmConfig.MrcFastBoot = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x1; memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, sizeof(Ch0_Bit_swizzling)); @@ -114,6 +115,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, sizeof(Ch3_Bit_swizzling)); - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; memupd->FspmConfig.MsgLevelMask = 0x0; }

1 0

Patch set updated for coreboot: siemens/mc_apl1: Make basic settings for booting the mainboard
by Mario Scheithauer 07 Feb '17

07 Feb '17

Mario Scheithauer (mario.scheithauer(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18292 -gerrit commit a2f89c8121049f892bebf0d132c4c2598d04dd11 Author: Mario Scheithauer <mario.scheithauer(a)siemens.com> Date: Mon Feb 6 13:03:52 2017 +0100 siemens/mc_apl1: Make basic settings for booting the mainboard This commit makes a basic adjustment for GPIOs, device tree, flash map and MRC settings. With these basic settings the mainboard boots into Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow. Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- src/mainboard/siemens/mc_apl1/brd_gpio.h | 37 ++--- src/mainboard/siemens/mc_apl1/devicetree.cb | 227 ++++------------------------ src/mainboard/siemens/mc_apl1/mc_apl1.fmd | 20 +-- src/mainboard/siemens/mc_apl1/romstage.c | 74 ++++----- 4 files changed, 91 insertions(+), 267 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h index 33b839b..91990e9 100644 --- a/src/mainboard/siemens/mc_apl1/brd_gpio.h +++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h @@ -18,11 +18,7 @@ #if ENV_ROMSTAGE static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ - PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ - PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ - PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ - + /* Debug tracing. */ PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), @@ -33,30 +29,25 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ - PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), - /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ - PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - - PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* Unused */ + PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* Unused */ PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), }; #endif diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index ce01a8b..c82896c 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -4,221 +4,54 @@ chip soc/intel/apollolake device lapic 0 on end end - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports + register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "0" # MACPHY + register "pcie_rp3_clkreq_pin" = "1" # MACPHY register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, - }" - - # digitizer at 400kHz - register "i2c[5]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" - device domain 0 on device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC + device pci 0d.1 off end # - PMC device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 off end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOM50C1_HID, - .cid = PNP0C50_CID, - .desc = WCOM_DT_DESC, - .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), - }" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 5 + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 device pci 17.2 off end # - I2C 6 - device pci 17.3 off end # - I2C 7 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 - device pci 1a.0 on end # - PWM + device pci 1a.0 off end # - PWM device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO device pci 1f.0 on end # - LPC device pci 1f.1 on end # - SMBUS diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 3da8467..432e8de 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,15 +1,16 @@ FLASH 16M { - WP_RO@0x0 0x400000 { + WP_RO@0x0 0xe00000 { SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { + IFWI@0x1000 0x23f000 + RO_VPD@0x240000 0x4000 + RO_SECTION@0x244000 0xbbc000 { FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x1bb000 - RO_UNUSED@0x1bc000 0x40000 + RO_UNUSED_1@0x800 0x800 + COREBOOT(CBFS)@0x1000 0xbb9000 + RO_UNUSED_2@0xbba000 0x1000 } } - MISC_RW@0x400000 0x30000 { + MISC_RW@0xe00000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -23,9 +24,8 @@ FLASH 16M { RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 + BIOS_UNUSABLE@0xe30000 0xcf000 + DEVICE_EXTENSION@0xeff000 0x100000 # Currently, it is required that the BIOS region be a multiple of 8KiB. # This is required so that the recovery mechanism can find SIGN_CSE # region aligned to 4K at the center of BIOS region. Since the diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 5c784ba..344007e 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -20,28 +20,28 @@ #include "brd_gpio.h" static const uint8_t Ch0_Bit_swizzling[] = { - 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, - 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, - 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, - 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch1_Bit_swizzling[] = { - 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, - 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, - 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, - 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch2_Bit_swizzling[] = { - 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, - 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, - 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, - 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const uint8_t Ch3_Bit_swizzling[] = { - 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, - 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, - 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, - 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -51,59 +51,59 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; - memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.Profile = 0x19; memupd->FspmConfig.MemoryDown = 0x1; - memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LPageSize = 0x2; memupd->FspmConfig.DDR3LASR = 0x0; - memupd->FspmConfig.ScramblerSupport = 0x1; - memupd->FspmConfig.ChannelHashMask = 0x36; - memupd->FspmConfig.SliceHashMask = 0x9; - memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ScramblerSupport = 0x0; + memupd->FspmConfig.ChannelHashMask = 0x0; + memupd->FspmConfig.SliceHashMask = 0x0; + memupd->FspmConfig.InterleavedMode = 0x0; memupd->FspmConfig.ChannelsSlicesEnable = 0x0; - memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x1; memupd->FspmConfig.DualRankSupportEnable = 0x1; memupd->FspmConfig.RmtMode = 0x0; - memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.MemorySizeLimit = 0x1000; memupd->FspmConfig.LowMemoryMaxValue = 0x0; memupd->FspmConfig.DisableFastBoot = 0x0; memupd->FspmConfig.HighMemoryMaxValue = 0x0; memupd->FspmConfig.DIMM0SPDAddress = 0x0; memupd->FspmConfig.DIMM1SPDAddress = 0x0; - memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_RankEnable = 0x1; memupd->FspmConfig.Ch0_DeviceWidth = 0x1; - memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_DramDensity = 0x0; memupd->FspmConfig.Ch0_Option = 0x3; - memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_OdtConfig = 0x1; memupd->FspmConfig.Ch0_TristateClk1 = 0x0; memupd->FspmConfig.Ch0_Mode2N = 0x0; memupd->FspmConfig.Ch0_OdtLevels = 0x0; - memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_RankEnable = 0x1; memupd->FspmConfig.Ch1_DeviceWidth = 0x1; - memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_DramDensity = 0x0; memupd->FspmConfig.Ch1_Option = 0x3; - memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_OdtConfig = 0x1; memupd->FspmConfig.Ch1_TristateClk1 = 0x0; memupd->FspmConfig.Ch1_Mode2N = 0x0; memupd->FspmConfig.Ch1_OdtLevels = 0x0; - memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_RankEnable = 0x0; memupd->FspmConfig.Ch2_DeviceWidth = 0x1; - memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_DramDensity = 0x0; memupd->FspmConfig.Ch2_Option = 0x3; memupd->FspmConfig.Ch2_OdtConfig = 0x0; memupd->FspmConfig.Ch2_TristateClk1 = 0x0; memupd->FspmConfig.Ch2_Mode2N = 0x0; memupd->FspmConfig.Ch2_OdtLevels = 0x0; - memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_RankEnable = 0x0; memupd->FspmConfig.Ch3_DeviceWidth = 0x1; - memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_DramDensity = 0x0; memupd->FspmConfig.Ch3_Option = 0x3; memupd->FspmConfig.Ch3_OdtConfig = 0x0; memupd->FspmConfig.Ch3_TristateClk1 = 0x0; memupd->FspmConfig.Ch3_Mode2N = 0x0; memupd->FspmConfig.Ch3_OdtLevels = 0x0; - memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x3; memupd->FspmConfig.MrcDataSaving = 0x0; - memupd->FspmConfig.MrcFastBoot = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x1; memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, sizeof(Ch0_Bit_swizzling)); @@ -114,6 +114,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, sizeof(Ch3_Bit_swizzling)); - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; memupd->FspmConfig.MsgLevelMask = 0x0; }

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Patch set updated for coreboot: src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested
by Martin Roth 07 Feb '17

07 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17909 -gerrit commit fdcb0772e12b03e5e43bfd84c69354b7ddb7e623 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 15 16:04:55 2016 -0700 src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested The four options are only used in X86: - BOOTBLOCK_SIMPLE - BOOTBLOCK_NORMAL - BOOTBLOCK_SOURCE - SKIP_MAX_REBOOT_CNT_CLEAR Move them all into src/arch/x86/Kconfig - this puts them in the chipset menu instead of general setup. Verified that this makes no significant changes to any config file. Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 27 --------------------------- src/arch/x86/Kconfig | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 27 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index d3a048c..bfa1832 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -214,33 +214,6 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM The relocated ramstage is saved in an area specified by the by the board and/or chipset. -# TODO: This doesn't belong here, move to src/arch/x86/Kconfig -choice - prompt "Bootblock behaviour" - default BOOTBLOCK_SIMPLE - -config BOOTBLOCK_SIMPLE - bool "Always load fallback" - -config BOOTBLOCK_NORMAL - bool "Switch to normal if CMOS says so" - -endchoice - -config BOOTBLOCK_SOURCE - string - default "bootblock_simple.c" if BOOTBLOCK_SIMPLE - default "bootblock_normal.c" if BOOTBLOCK_NORMAL - -config SKIP_MAX_REBOOT_CNT_CLEAR - bool "Do not clear reboot count after successful boot" - depends on BOOTBLOCK_NORMAL - help - Do not clear the reboot count immediately after successful boot. - Set to allow the payload to control normal/fallback image recovery. - Note that it is the responsibility of the payload to reset the - normal boot bit to 1 after each successsful boot. - config UPDATE_IMAGE bool "Update existing coreboot.rom image" help diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6280024..c153a74 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -214,3 +214,29 @@ config ROMSTAGE_DEBUG_SPINLOOP help Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence. + +choice + prompt "Bootblock behaviour" + default BOOTBLOCK_SIMPLE + +config BOOTBLOCK_SIMPLE + bool "Always load fallback" + +config BOOTBLOCK_NORMAL + bool "Switch to normal if CMOS says so" + +endchoice + +config BOOTBLOCK_SOURCE + string + default "bootblock_simple.c" if BOOTBLOCK_SIMPLE + default "bootblock_normal.c" if BOOTBLOCK_NORMAL + +config SKIP_MAX_REBOOT_CNT_CLEAR + bool "Do not clear reboot count after successful boot" + depends on BOOTBLOCK_NORMAL + help + Do not clear the reboot count immediately after successful boot. + Set to allow the payload to control normal/fallback image recovery. + Note that it is the responsibility of the payload to reset the + normal boot bit to 1 after each successsful boot.

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coreboot-gerrit February 2017