coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: b8e96ed Kconfig: Fix comments on endif to match the corresponding if
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit b8e96ed7b81c2d1816814a2a89cf79a5abc4c28f Author: Daniele Forsi <dforsi(a)gmail.com> Date: Tue Jul 29 12:13:12 2014 +0200 Kconfig: Fix comments on endif to match the corresponding if Change-Id: I5c40de41a01d9c558f6c2795e19e643009804e70 Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Reviewed-on: http://review.coreboot.org/6397 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6397 for details. -gerrit

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Patch merged into coreboot/master: 76a1437 cpu/intel/model_2065x/model_2065x_init.c: Remove dead code
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 76a1437dbe7fae07a5054971adadb703c19f5885 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jun 26 22:34:59 2014 +1000 cpu/intel/model_2065x/model_2065x_init.c: Remove dead code Unused array is dead code. Spotted by Clang build. Change-Id: I11397716b39de08f1226413019e3beeeeaac6149 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6131 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6131 for details. -gerrit

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Patch merged into coreboot/master: 787cbae i82801ix: Enable usbdebug options.
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 787cbaeedb4159c43e5e0875d9b7dbfc8a09ed8c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:40:05 2014 +0200 i82801ix: Enable usbdebug options. Needed to be able to choose convenient usbdebug port. Change-Id: I84b304f0f8fa79cc8d4a136ee6d78dc7659601c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6410 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/6410 for details. -gerrit

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New patch to review for coreboot: c14ad07 libpayload: provide missing cbfs symbol
by Isaac Christensen 30 Jul '14

30 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6411 -gerrit commit c14ad073f8afb85008178802046d31d3f8cda95e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 09:25:32 2013 -0500 libpayload: provide missing cbfs symbol The generic cbfs code relies on the libpayload_init_default_cbfs_media symbol. However, none was provided for ARM. Provide an empty implementation that returns an error as there is no generic way to locate the default cbfs media. Old-Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56805 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit d3410c28ef9f37b832e2fa2d18351dda332bc9f7) libpayload: place dummy_media.c in correct object list The commit introducing dummy_media.c was placed in the libc object list. This wasn't correct. It should be in the libcbfs object list as well as guarded by CONFIG_CBFS. Old-Change-Id: Iace43fff8f85f60ecac5e6eb8350cd1f3ee9d35e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56925 (cherry picked from commit 7937c7c5e95a934593bc0cedd5f4496b4770c303) Squashed two related commits. Change-Id: I84cd132b44cc2ea5b29acf109a3562baaeede9c6 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/armv7/Makefile.inc | 1 + payloads/libpayload/arch/armv7/dummy_media.c | 42 ++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index 2c7c9e9..a27fdd4 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -36,3 +36,4 @@ libc-y += virtual.c libc-y += memcpy.S memset.S libc-y += exception_asm.S exception.c libc-y += cache.c +libcbfs-$(CONFIG_CBFS) += dummy_media.c diff --git a/payloads/libpayload/arch/armv7/dummy_media.c b/payloads/libpayload/arch/armv7/dummy_media.c new file mode 100644 index 0000000..7926976 --- /dev/null +++ b/payloads/libpayload/arch/armv7/dummy_media.c @@ -0,0 +1,42 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define LIBPAYLOAD + +#include <cbfs.h> +#include <string.h> + +/* The generic cbfs code relies on the libpayload_init_default_cbfs_media + * symbol. Therefore, provide an implementation that just throws an error. */ + +int libpayload_init_default_cbfs_media(struct cbfs_media *media); + +int libpayload_init_default_cbfs_media(struct cbfs_media *media) +{ + return -1; +}

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Patch set updated for coreboot: e20422c i82801ix: Allow configuration of SATA mode in CMOS.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6409 -gerrit commit e20422c371d1c7ad580b7ecba64a53127e0bfa98 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:35:45 2014 +0200 i82801ix: Allow configuration of SATA mode in CMOS. Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/emulation/qemu-q35/devicetree.cb | 2 -- src/mainboard/roda/rk9/cmos.layout | 5 ++++- src/mainboard/roda/rk9/devicetree.cb | 1 - src/southbridge/intel/i82801ix/chip.h | 2 -- src/southbridge/intel/i82801ix/sata.c | 23 ++++++++++++++++------- 5 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb index 1ac55a0..671a2d6 100644 --- a/src/mainboard/emulation/qemu-q35/devicetree.cb +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -7,8 +7,6 @@ chip mainboard/emulation/qemu-q35 device domain 0 on device pci 0.0 on end # northbridge (q35) chip southbridge/intel/i82801ix - register "sata_ahci" = "1" - # present unconditionally device pci 1f.0 on end # LPC device pci 1f.2 on end # SATA diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index 8f12ef4..ca439c9 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -85,7 +85,8 @@ entries #400 8 r 0 unused # coreboot config options: southbridge -#408 8 r 0 unused +408 1 e 9 sata_mode +#409 7 r 0 unused # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -133,6 +134,8 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 5989278..deece86 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/gm45 register "alt_gp_smi_en" = "0x0002" # Set AHCI mode, enable ports 1 and 2. - register "sata_ahci" = "1" register "sata_port_map" = "0x03" register "sata_clock_request" = "0" register "sata_traffic_monitor" = "0" diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 222cfb5..5e1221d 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -70,8 +70,6 @@ struct southbridge_intel_i82801ix_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; /* If enabled, keep bit 2 of sata_enabled unset. */ uint8_t sata_port_map : 6; int sata_clock_request : 1; int sata_traffic_monitor : 1; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 02f6d53..10c8a2b 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "i82801ix.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_i82801ix_config config_t; @@ -149,6 +150,7 @@ static void sata_init(struct device *const dev) const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); const int is_mobile = (devid == 0x2928) || (devid == 0x2929); + u8 sata_mode; printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); @@ -158,6 +160,10 @@ static void sata_init(struct device *const dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * TODO: In contrast to ICH7 and PCH code we don't set * timings, dma and IDE-I/O settings here. Looks like they @@ -171,13 +177,11 @@ static void sata_init(struct device *const dev) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); - if (!config->sata_ahci) + if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); - } else if (config->sata_ahci) { + if (sata_mode == 0) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); } else { printk(BIOS_DEBUG, "SATA controller in native mode.\n"); @@ -193,7 +197,7 @@ static void sata_init(struct device *const dev) /* Port enable. For AHCI, it's managed in memory mapped space. */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; - reg16 |= (1 << 15) | (config->sata_ahci ? 0x3f : config->sata_port_map); + reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map); pci_write_config16(dev, 0x92, reg16); /* SATA clock settings */ @@ -218,7 +222,7 @@ static void sata_init(struct device *const dev) } } - if (config->sata_ahci) + if (sata_mode == 0) sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); sata_program_indexed(dev, is_mobile); @@ -230,15 +234,20 @@ static void sata_enable(device_t dev) const config_t *const config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */ map |= (config->sata_port_map ^ 0x3f) << 8;

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Patch set updated for coreboot: eb873c3 i82801ix: Enable usbdebug options.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6410 -gerrit commit eb873c3bddc04b6a427179c8e4dd5e204dc088f0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:40:05 2014 +0200 i82801ix: Enable usbdebug options. Needed to be able to choose convenient usbdebug port. Change-Id: I84b304f0f8fa79cc8d4a136ee6d78dc7659601c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801ix/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 493be60..92e7f41 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -26,6 +26,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS if SOUTHBRIDGE_INTEL_I82801IX

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New patch to review for coreboot: f58a1ea i82801ix: Enable usbdebug options.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6410 -gerrit commit f58a1ea42a8219d30e59b815dc2cd6fdff9f67bd Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:40:05 2014 +0200 i82801ix: Enable usbdebug options. Needed to be able to choose convenient usbdebug port. Change-Id: I84b304f0f8fa79cc8d4a136ee6d78dc7659601c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/i82801ix/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 493be60..92e7f41 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -26,6 +26,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS if SOUTHBRIDGE_INTEL_I82801IX

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Patch set updated for coreboot: da8eb7d i82801ix: Allow configuration of SATA mode in CMOS.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6409 -gerrit commit da8eb7d4e61188862c9e5eab783ba88fcda09859 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:35:45 2014 +0200 i82801ix: Allow configuration of SATA mode in CMOS. Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/roda/rk9/cmos.layout | 5 ++++- src/mainboard/roda/rk9/devicetree.cb | 1 - src/southbridge/intel/i82801ix/chip.h | 2 -- src/southbridge/intel/i82801ix/sata.c | 23 ++++++++++++++++------- 4 files changed, 20 insertions(+), 11 deletions(-) diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index 8f12ef4..ca439c9 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -85,7 +85,8 @@ entries #400 8 r 0 unused # coreboot config options: southbridge -#408 8 r 0 unused +408 1 e 9 sata_mode +#409 7 r 0 unused # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -133,6 +134,8 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 5989278..deece86 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/gm45 register "alt_gp_smi_en" = "0x0002" # Set AHCI mode, enable ports 1 and 2. - register "sata_ahci" = "1" register "sata_port_map" = "0x03" register "sata_clock_request" = "0" register "sata_traffic_monitor" = "0" diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 222cfb5..5e1221d 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -70,8 +70,6 @@ struct southbridge_intel_i82801ix_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; /* If enabled, keep bit 2 of sata_enabled unset. */ uint8_t sata_port_map : 6; int sata_clock_request : 1; int sata_traffic_monitor : 1; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 02f6d53..10c8a2b 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "i82801ix.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_i82801ix_config config_t; @@ -149,6 +150,7 @@ static void sata_init(struct device *const dev) const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); const int is_mobile = (devid == 0x2928) || (devid == 0x2929); + u8 sata_mode; printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); @@ -158,6 +160,10 @@ static void sata_init(struct device *const dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * TODO: In contrast to ICH7 and PCH code we don't set * timings, dma and IDE-I/O settings here. Looks like they @@ -171,13 +177,11 @@ static void sata_init(struct device *const dev) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); - if (!config->sata_ahci) + if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); - } else if (config->sata_ahci) { + if (sata_mode == 0) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); } else { printk(BIOS_DEBUG, "SATA controller in native mode.\n"); @@ -193,7 +197,7 @@ static void sata_init(struct device *const dev) /* Port enable. For AHCI, it's managed in memory mapped space. */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; - reg16 |= (1 << 15) | (config->sata_ahci ? 0x3f : config->sata_port_map); + reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map); pci_write_config16(dev, 0x92, reg16); /* SATA clock settings */ @@ -218,7 +222,7 @@ static void sata_init(struct device *const dev) } } - if (config->sata_ahci) + if (sata_mode == 0) sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); sata_program_indexed(dev, is_mobile); @@ -230,15 +234,20 @@ static void sata_enable(device_t dev) const config_t *const config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */ map |= (config->sata_port_map ^ 0x3f) << 8;

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Patch merged into coreboot/master: c4d8948 gm45: Move spd address map to board-specific config.
by gerrit＠coreboot.org 29 Jul '14

29 Jul '14

the following patch was just integrated into master: commit c4d894879775f66bdfe0a8f00fa847ab40fbe885 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jun 5 09:14:48 2014 +0200 gm45: Move spd address map to board-specific config. Change-Id: I8f45a821ecd414dbd0129ae6d583d4e7dc06bc5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/5931 Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5931 for details. -gerrit

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Patch merged into coreboot/master: a838aaf northbridge/intel/sandybridge/raminit_native: Remove stale FIXME.
by gerrit＠coreboot.org 29 Jul '14

29 Jul '14

the following patch was just integrated into master: commit a838aafc63171cef3e3139228541eb785faf6f57 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:07:59 2014 +0200 northbridge/intel/sandybridge/raminit_native: Remove stale FIXME. S3 works just fine. Change-Id: Icd7ae5ad8941bf749a4450efc61e7cede52bf5ef Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6407 Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/6407 for details. -gerrit

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coreboot-gerrit July 2014