coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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861 discussions

Patch set updated for coreboot: eab5cb5 build system: remove duplicate architecture list
by Patrick Georgi 30 Jul '14

30 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6254 -gerrit commit eab5cb5bff567e72d541ff9851b4597870853263 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 20:38:21 2014 +0200 build system: remove duplicate architecture list Let xcompile pass the list of architectures, given that it already has it. Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- toolchain.inc | 2 -- util/xcompile/xcompile | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index b5b4fe0..842473b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -17,8 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ARCH_SUPPORTED := armv7 x86_32 - # ccache integration ifeq ($(CONFIG_CCACHE),y) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 8239243..01d75bf 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -145,6 +145,7 @@ detect_special_flags() { report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) +ARCH_SUPPORTED+=${TARCH} CC_${TARCH}:=${GCCPREFIX}gcc CFLAGS_${TARCH}:=${CFLAGS} CPP_${TARCH}:=${GCCPREFIX}cpp

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Patch set updated for coreboot: 652de37 northbridge/amd/agesa/agesawrapper_call.h: Decode status codes
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6402 -gerrit commit 652de37a7bf77666b5d1316ea1506f137d3a0215 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 02:19:25 2014 +1000 northbridge/amd/agesa/agesawrapper_call.h: Decode status codes Decode obscure AGESA status codes into their respective string forms. Change-Id: Iccf175ef62e5005af6ebbfb1bd0acec8aedc2eaa Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/agesawrapper_call.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index e654b8a..0acbeee 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -22,12 +22,36 @@ #include <console/console.h> #include "AGESA.h" +/* + * Possible AGESA_STATUS values: + * + * 0x0 = AGESA_SUCCESS + * 0x1 = AGESA_UNSUPPORTED + * 0x2 = AGESA_BOUNDS_CHK + * 0x3 = AGESA_ALERT + * 0x4 = AGESA_WARNING + * 0x5 = AGESA_ERROR + * 0x6 = AGESA_CRITICAL + * 0x7 = AGESA_FATAL + */ +static const char * decodeAGESA_STATUS(AGESA_STATUS sret) +{ + const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", + "AGESA_BOUNDS_CHK", "AGESA_ALERT", + "AGESA_WARNING", "AGESA_ERROR", + "AGESA_CRITICAL", "AGESA_FATAL" + }; + if (sret > 7) return "unknown"; /* Non-AGESA error code */ + return statusStrings[sret]; +} + static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) { AGESA_STATUS ret; printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); ret = func(); - printk(BIOS_DEBUG, "agesawrapper_%s() AGESA_STATUS = %x\n", name, ret); + printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", + name, decodeAGESA_STATUS(ret)); return (u32)ret; }

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New patch to review for coreboot: a48e6fc device/oprom/realmode: Sanitize header inclusion
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6415 -gerrit commit a48e6fcc29084b9e51f7bced3cd3d9243c00e521 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 13:53:04 2014 +1000 device/oprom/realmode: Sanitize header inclusion Alphabetise includes to avoid duplication. Change-Id: I7fa6998cd736bad2bab4a6b1a65d48a21d6220d9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/oprom/realmode/x86.c | 22 +++++++++++----------- src/device/oprom/realmode/x86.h | 2 +- src/device/oprom/realmode/x86_interrupts.c | 10 ++++++---- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 7dec258..fc3c40c 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -18,26 +18,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ -#include <device/pci.h> -#include <string.h> - #include <arch/io.h> +#include <arch/interrupt.h> #include <arch/registers.h> -#include <cpu/amd/lxdef.h> -#include <cpu/amd/vr.h> +#include <boot/coreboot_tables.h> #include <cbfs.h> #include <console/console.h> -#include <arch/interrupt.h> -#include <cbfs.h> +#include <cpu/amd/lxdef.h> +#include <cpu/amd/vr.h> #include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <lib/jpeg.h> #include <pc80/i8259.h> -#include "x86.h" +#include <string.h> #include <vbe.h> -#include <lib/jpeg.h> + /* we use x86emu's register file representation */ #include <x86emu/regs.h> -#include <boot/coreboot_tables.h> -#include <device/pci_ids.h> + +#include "x86.h" /* The following symbols cannot be used directly. They need to be fixed up * to point to the correct address location after the code has been copied diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index a811a56..a0c7a90 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -52,4 +52,4 @@ int int12_handler(void); int int16_handler(void); int int1a_handler(void); -#endif +#endif /* __DEVICE_OPROM_REALMODE_X86_H__ */ diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 1ee6979..56a9b1b 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -19,17 +19,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ +#include <arch/io.h> +#include <arch/registers.h> +#include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> -#include <console/console.h> -#include <arch/io.h> -#include <arch/registers.h> -#include "x86.h" + /* we use x86emu's register file representation */ #include <x86emu/regs.h> +#include "x86.h" + // errors go in AH. Just set these up so that word assigns // will work. KISS. enum {

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Patch set updated for coreboot: 8a00d1c arch/x86/include/arch/interrupt.h: Add header guards
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6400 -gerrit commit 8a00d1cde0b800bd5db6df9eebf03c8364f39dc4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 22:27:51 2014 +1000 arch/x86/include/arch/interrupt.h: Add header guards Change-Id: I34c27bbce3ce958a33d547c727d9733d3b2d1670 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/include/arch/interrupt.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 9753c50..e3322bb 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef INTERRUPT_H +#define INTERRUPT_H + #include "registers.h" /* setup interrupt handlers for mainboard */ @@ -29,3 +32,5 @@ extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)); #else static inline void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)) { } #endif + +#endif /* INTERRUPT_H */

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Patch set updated for coreboot: 309cc24 device/oprom/realmode/x86.c: Move includes to top of file
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6401 -gerrit commit 309cc24f2bafc19baa0e4e92e8511a17091bc637 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 22:28:19 2014 +1000 device/oprom/realmode/x86.c: Move includes to top of file Change-Id: Ib68e1f570092a69447d307c33b98f70b817f0ec1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/oprom/realmode/x86.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 4338e6e..7dec258 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -23,6 +23,9 @@ #include <arch/io.h> #include <arch/registers.h> +#include <cpu/amd/lxdef.h> +#include <cpu/amd/vr.h> +#include <cbfs.h> #include <console/console.h> #include <arch/interrupt.h> #include <cbfs.h> @@ -350,9 +353,6 @@ void run_bios(struct device *dev, unsigned long addr) } #if CONFIG_GEODE_VSA -#include <cpu/amd/lxdef.h> -#include <cpu/amd/vr.h> -#include <cbfs.h> #define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020

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New patch to review for coreboot: 8082a10 cpu/intel: Rename 'enable_vmx()' func to 'toggle_vmx()'
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6414 -gerrit commit 8082a10d92c8351683f60c264f55e3ba84ca90d7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 12:44:35 2014 +1000 cpu/intel: Rename 'enable_vmx()' func to 'toggle_vmx()' In preparation for introduce runtime configurable VMX feature bit setting in cmos.layout. Change-Id: I3997348fdf2d66f2ea7c9b6e64c8ab98f1cd7858 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++-- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++-- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index c2f9f19..55e0d4c 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -36,7 +36,7 @@ #include "model_206ax.h" #include "chip.h" -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -373,7 +373,7 @@ static void model_206ax_init(device_t cpu) setup_lapic(); /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + toggle_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 043ba3a..162f802 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,7 +150,7 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -745,7 +745,7 @@ static void haswell_init(device_t cpu) setup_lapic(); /* Enable virtualization if Kconfig option is set */ - enable_vmx(); + toggle_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 4779a51..2e2f569 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -51,7 +51,7 @@ static void init_timer(void) #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -333,7 +333,7 @@ static void model_1067x_init(device_t cpu) init_timer(); /* Enable virtualization */ - enable_vmx(); + toggle_vmx(); /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 73ee5cd..2e76927 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -34,7 +34,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -132,7 +132,7 @@ static void model_106cx_init(device_t cpu) setup_lapic(); /* Enable virtualization */ - enable_vmx(); + toggle_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 9a2afa4..2cff908 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -114,7 +114,7 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -369,7 +369,7 @@ static void model_2065x_init(device_t cpu) setup_lapic(); /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + toggle_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4e56414..892d0d2 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -114,7 +114,7 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -562,7 +562,7 @@ static void model_206ax_init(device_t cpu) setup_lapic(); /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + toggle_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 8f9fbf8..6bc1f05 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -37,7 +37,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -163,7 +163,7 @@ static void model_6ex_init(device_t cpu) setup_lapic(); /* Enable virtualization */ - enable_vmx(); + toggle_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 93635d4..a7f6bde 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -36,7 +36,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -186,7 +186,7 @@ static void model_6fx_init(device_t cpu) setup_lapic(); /* Enable virtualization */ - enable_vmx(); + toggle_vmx(); /* Configure C States */ configure_c_states();

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Patch set updated for coreboot: 3e00f10 cpu/intel: Make VMX bit configurable in CMOS
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6413 -gerrit commit 3e00f10fe3e10e0bef421f1af82695353392bfac Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 11:45:10 2014 +1000 cpu/intel: Make VMX bit configurable in CMOS Use cmos.layout over Kconfig variable to make VMX setting runtime configurable. Fix the following boards cmos.layout to match: * intel/cougar_canyon2 * kontron/ktqm77 Change-Id: I097b708fa22c735e962556e5d9e57caa322e0b24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 6 +----- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 9 ++++++--- src/cpu/intel/haswell/Kconfig | 4 ---- src/cpu/intel/haswell/haswell_init.c | 10 +++++++--- src/cpu/intel/model_2065x/Kconfig | 6 +----- src/cpu/intel/model_2065x/model_2065x_init.c | 10 +++++++--- src/cpu/intel/model_206ax/Kconfig | 6 +----- src/cpu/intel/model_206ax/model_206ax_init.c | 10 +++++++--- src/mainboard/intel/cougar_canyon2/Kconfig | 1 - src/mainboard/intel/cougar_canyon2/cmos.layout | 3 ++- src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/kontron/ktqm77/cmos.layout | 3 ++- 12 files changed, 34 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 043320c..b642e18 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -49,10 +49,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config CPU_MICROCODE_CBFS_LOC hex depends on SUPPORT_CPU_UCODE_IN_CBFS @@ -69,4 +65,4 @@ config MICROCODE_INCLUDE_PATH default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX -endif +endif # CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index 55e0d4c..fc5e729 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -40,7 +40,10 @@ static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -62,9 +65,9 @@ static void toggle_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9e62ae5..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,10 +34,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 162f802..f98c691 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,11 +150,15 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +/* Enable VMX for virtualization in cmos.layout */ static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -176,9 +180,9 @@ static void toggle_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 8185d3a..7bd6f88 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -28,12 +28,8 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config XIP_ROM_SIZE hex default 0x20000 -endif +endif # CPU_INTEL_MODEL_2065X diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 2cff908..2b7ab46 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -114,11 +114,15 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +/* Enable VMX for virtualization in cmos.layout */ static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -140,7 +144,7 @@ static void toggle_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); /* Even though the Intel manual says you must set the lock bit in addition * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave @@ -155,7 +159,7 @@ static void toggle_vmx(void) * By leaving this to the OS (e.g. Linux), people can do exactly what they * want on the fly, and do it correctly (e.g. across multiple cores). */ - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index afd155a..8a6cc65 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -29,8 +29,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - -endif +endif # CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 892d0d2..590e086 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -114,11 +114,15 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +/* Enable VMX for virtualization in cmos.layout */ static void toggle_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -140,7 +144,7 @@ static void toggle_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); /* Even though the Intel manual says you must set the lock bit in addition * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave @@ -155,7 +159,7 @@ static void toggle_vmx(void) * By leaving this to the OS (e.g. Linux), people can do exactly what they * want on the fly, and do it correctly (e.g. across multiple cores). */ - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 389a13c..4b0927f 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select SUPERIO_SMSC_SIO1007 - select ENABLE_VMX select EARLY_CBMEM_INIT select BROKEN_CAR_MIGRATE select VGA diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index 2dfa156..b8d50a3 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -63,7 +63,8 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused +120 1 e 1 enable_vmx +#121 263 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index d1a7d42..226368f 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select ENABLE_VMX select HAVE_MRC config MAINBOARD_DIR diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 245b47e..b9577e0 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -63,7 +63,8 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused +120 1 e 1 enable_vmx +#121 263 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded)

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New patch to review for coreboot: f2da826 cpu/intel: Make VMX bit configurable in CMOS
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6413 -gerrit commit f2da826f049a6dd7e67fe6fd5ff50636560d1f01 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 11:45:10 2014 +1000 cpu/intel: Make VMX bit configurable in CMOS Use cmos.layout over Kconfig variable to make VMX setting runtime configurable. Fix the following boards cmos.layout to match: * intel/cougar_canyon2 * kontron/ktqm77 Change-Id: I097b708fa22c735e962556e5d9e57caa322e0b24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 6 +----- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 9 ++++++--- src/cpu/intel/haswell/Kconfig | 4 ---- src/cpu/intel/haswell/haswell_init.c | 10 +++++++--- src/cpu/intel/model_2065x/Kconfig | 6 +----- src/cpu/intel/model_2065x/model_2065x_init.c | 10 +++++++--- src/cpu/intel/model_206ax/Kconfig | 6 +----- src/cpu/intel/model_206ax/model_206ax_init.c | 10 +++++++--- src/mainboard/intel/cougar_canyon2/Kconfig | 1 - src/mainboard/intel/cougar_canyon2/cmos.layout | 3 ++- src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/kontron/ktqm77/cmos.layout | 3 ++- 12 files changed, 34 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 043320c..b642e18 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -49,10 +49,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config CPU_MICROCODE_CBFS_LOC hex depends on SUPPORT_CPU_UCODE_IN_CBFS @@ -69,4 +65,4 @@ config MICROCODE_INCLUDE_PATH default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX -endif +endif # CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index c2f9f19..7f1ceeb 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -40,7 +40,10 @@ static void enable_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -62,9 +65,9 @@ static void enable_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9e62ae5..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,10 +34,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 043ba3a..a64a8c4 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,11 +150,15 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +/* Enable VMX for virtualization in cmos.layout */ static void enable_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -176,9 +180,9 @@ static void enable_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 8185d3a..7bd6f88 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -28,12 +28,8 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config XIP_ROM_SIZE hex default 0x20000 -endif +endif # CPU_INTEL_MODEL_2065X diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 9a2afa4..b84ab9d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -114,11 +114,15 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +/* Enable VMX for virtualization in cmos.layout */ static void enable_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -140,7 +144,7 @@ static void enable_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); /* Even though the Intel manual says you must set the lock bit in addition * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave @@ -155,7 +159,7 @@ static void enable_vmx(void) * By leaving this to the OS (e.g. Linux), people can do exactly what they * want on the fly, and do it correctly (e.g. across multiple cores). */ - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index afd155a..8a6cc65 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -29,8 +29,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - -endif +endif # CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4e56414..f29cc0c 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -114,11 +114,15 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +/* Enable VMX for virtualization in cmos.layout */ static void enable_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -140,7 +144,7 @@ static void enable_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); /* Even though the Intel manual says you must set the lock bit in addition * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave @@ -155,7 +159,7 @@ static void enable_vmx(void) * By leaving this to the OS (e.g. Linux), people can do exactly what they * want on the fly, and do it correctly (e.g. across multiple cores). */ - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 389a13c..4b0927f 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select SUPERIO_SMSC_SIO1007 - select ENABLE_VMX select EARLY_CBMEM_INIT select BROKEN_CAR_MIGRATE select VGA diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index 2dfa156..b8d50a3 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -63,7 +63,8 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused +120 1 e 1 enable_vmx +#121 263 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index d1a7d42..226368f 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select ENABLE_VMX select HAVE_MRC config MAINBOARD_DIR diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 245b47e..b9577e0 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -63,7 +63,8 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused +120 1 e 1 enable_vmx +#121 263 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded)

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New patch to review for coreboot: 26654cf model_206ax_init.c: Trivial - fix indent
by Edward O'Callaghan 30 Jul '14

30 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6412 -gerrit commit 26654cff9781d773a997c045dbed96e32b58c068 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 11:44:29 2014 +1000 model_206ax_init.c: Trivial - fix indent Change-Id: I84876c95522fca5560bcbc8e81dfcb09faf3b326 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index d0b2d3d..c2f9f19 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -65,9 +65,9 @@ static void enable_vmx(void) printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); if (enable) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); } wrmsr(IA32_FEATURE_CONTROL, msr);

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Patch merged into coreboot/master: abb3816 artecgroup/Kconfig, linutop/Kconfig: Add comment to endif
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit abb381607fabcea0a101273c29a42280064b5f9b Author: Daniele Forsi <dforsi(a)gmail.com> Date: Tue Jul 29 12:09:39 2014 +0200 artecgroup/Kconfig, linutop/Kconfig: Add comment to endif All other Kconfig files at the mainboard vendor level have a comment on "endif" matching the corresponding "if", except these two. Change-Id: Ib03c4552c670178d6b09a2ca3037ee29e3524a2f Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Reviewed-on: http://review.coreboot.org/6396 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6396 for details. -gerrit

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coreboot-gerrit July 2014