coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c3fda41 northbridge/amd/agesa/agesawrapper_call.h: Decode status codes
by gerrit＠coreboot.org 31 Jul '14

31 Jul '14

the following patch was just integrated into master: commit c3fda416a7e71eae4803c07f0fae4b0b931d1ca8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 02:19:25 2014 +1000 northbridge/amd/agesa/agesawrapper_call.h: Decode status codes Decode obscure AGESA status codes into their respective string forms. Change-Id: Iccf175ef62e5005af6ebbfb1bd0acec8aedc2eaa Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6402 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/6402 for details. -gerrit

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Patch set updated for coreboot: 4ac9e05 superio/winbond/w83627ehg: Remove pnp_enter symbol from global
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5871 -gerrit commit 4ac9e05732da1b716291fa9779a346b3a15ecd00 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 26 04:35:48 2014 +1000 superio/winbond/w83627ehg: Remove pnp_enter symbol from global Part 2/2: Break this poor relationship between boards and Super I/O support to be more well-defined. The Super I/O pnp_entry/exit functions should not be exposed into the global name-space, rather should be static-local. Provide Winbond w83627eh(f/g) input clock rate selection. This is selected by bit 6 of CR 24h by mask & 0xbf map (1 = 48MHz default) -> (0 = 24MHz), see data-sheet page 98. Change-Id: Ie39235f2926a2165092319a6b1375e505b7dac14 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 17 ++++++++++++++--- src/mainboard/asus/a8v-e_se/romstage.c | 17 ++++++++++++++--- src/mainboard/ibase/mb899/romstage.c | 13 +++++++++++++ src/mainboard/msi/ms7260/romstage.c | 5 +---- src/mainboard/msi/ms9652_fam10/romstage.c | 7 +------ src/mainboard/nvidia/l1_2pvv/romstage.c | 4 +--- src/superio/winbond/w83627ehg/early_serial.c | 17 +++++++++++++---- src/superio/winbond/w83627ehg/w83627ehg.h | 6 ++++-- 8 files changed, 61 insertions(+), 25 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..25169c0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -97,14 +97,24 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* We have GPIO for KB/MS pin. */ reg = pnp_read_config(SERIAL_DEV, 0x2a); pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); @@ -154,6 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..a11403a 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -97,14 +97,24 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* We have GPIO for KB/MS pin. */ reg = pnp_read_config(SERIAL_DEV, 0x2a); pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); @@ -154,6 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0e74418..24238b3 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -70,6 +70,19 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..072bae9 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -119,12 +119,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ - pnp_write_config(SERIAL_DEV, 0x24, 0); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..eff291b 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -103,7 +103,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; - u8 reg; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -121,11 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c..75bdb6f 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -118,9 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..dce18cf 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,15 +23,24 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } + +void w83627ehg_serial_clk(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + /* We have 24MHz input. */ + u8 reg = pnp_read_config(dev, 0x24); + pnp_write_config(dev, 0x24, (reg & 0xbf)); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..b514488 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,9 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +#include <arch/io.h> +#include <device/pnp.h> + +void w83627ehg_serial_clk(device_t); #endif /* SUPERIO_WINBOND_W83627EHG_H */

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New patch to review for coreboot: 8bc71b8 northbridge/intel: Trivial fsp_rangeley northbridge cleanups
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6420 -gerrit commit 8bc71b81a58392226ccc2141243be0fbcd61611c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 09:07:38 2014 +1000 northbridge/intel: Trivial fsp_rangeley northbridge cleanups Introduced in: 2963ae7 northbridge/intel: Add fsp_rangeley northbridge support Change-Id: I13f2c46aa2bcedb9d1c66c485bf48ed7bc95d9c7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_rangeley/chip.h | 2 +- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 6 ++---- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h | 2 +- src/northbridge/intel/fsp_rangeley/port_access.c | 11 +++++------ 4 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 24609a1..0d19aa7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -60,4 +60,4 @@ struct northbridge_intel_fsp_rangeley_config { uint8_t Bifurcation; }; -#endif +#endif /* _FSP_RANGELEY_CHIP_H_ */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index bd196a5..de60c5c 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -29,11 +29,9 @@ #include <fspvpd.h> #include <fspbootmode.h> #include <reset.h> -#include "../chip.h" - -#ifdef __PRE_RAM__ #include <southbridge/intel/fsp_rangeley/romstage.h> -#endif + +#include "../chip.h" #ifdef __PRE_RAM__ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..845f9a2 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -42,7 +42,7 @@ } /* - *The FSP Image ID is different for each platform's FSP and + * The FSP Image ID is different for each platform's FSP and * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index 508630e..9dabd9f 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -18,17 +18,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif - -#include <stdint.h> #include <arch/io.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> +#include <stdint.h> + #include "northbridge.h" +#define __PRE_RAM__ // Use simple device model for this file even in ramstage + /* * Restricted Access Regions: *

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Patch set updated for coreboot: ea2dbdf cpu/intel: Make VMX bit configurable in CMOS
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6413 -gerrit commit ea2dbdf2e84ff28b67c591ce880cb93b082f83e9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 11:45:10 2014 +1000 cpu/intel: Make VMX bit configurable in CMOS Use cmos.layout over Kconfig variable to make VMX setting runtime configurable. Fix the following boards cmos.layout to match: * intel/cougar_canyon2 * kontron/ktqm77 Change-Id: I097b708fa22c735e962556e5d9e57caa322e0b24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 6 +----- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 9 ++++++--- src/cpu/intel/haswell/Kconfig | 4 ---- src/cpu/intel/haswell/haswell_init.c | 10 +++++++--- src/cpu/intel/model_2065x/Kconfig | 6 +----- src/cpu/intel/model_2065x/model_2065x_init.c | 10 +++++++--- src/cpu/intel/model_206ax/Kconfig | 6 +----- src/cpu/intel/model_206ax/model_206ax_init.c | 10 +++++++--- src/mainboard/intel/cougar_canyon2/Kconfig | 1 - src/mainboard/intel/cougar_canyon2/cmos.layout | 3 ++- src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/kontron/ktqm77/cmos.layout | 3 ++- 12 files changed, 34 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 043320c..b642e18 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -49,10 +49,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config CPU_MICROCODE_CBFS_LOC hex depends on SUPPORT_CPU_UCODE_IN_CBFS @@ -69,4 +65,4 @@ config MICROCODE_INCLUDE_PATH default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX -endif +endif # CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index b375d60..e1b04ff 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -40,7 +40,10 @@ static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -62,9 +65,9 @@ static void configure_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9e62ae5..9cda140 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,10 +34,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 1d1fef4..3bda6fd 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,11 +150,15 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +/* Enable VMX for virtualization in cmos.layout */ static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -176,9 +180,9 @@ static void configure_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 8185d3a..7bd6f88 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -28,12 +28,8 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - config XIP_ROM_SIZE hex default 0x20000 -endif +endif # CPU_INTEL_MODEL_2065X diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d1ec124..ec1b61a 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -114,11 +114,15 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +/* Enable VMX for virtualization in cmos.layout */ static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -140,7 +144,7 @@ static void configure_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); /* Even though the Intel manual says you must set the lock bit in addition * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave @@ -155,7 +159,7 @@ static void configure_vmx(void) * By leaving this to the OS (e.g. Linux), people can do exactly what they * want on the fly, and do it correctly (e.g. across multiple cores). */ - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index afd155a..8a6cc65 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -29,8 +29,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config ENABLE_VMX - bool "Enable VMX for virtualization" - default n - -endif +endif # CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 6debf3a..8864a24 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -114,11 +114,15 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +/* Enable VMX for virtualization in cmos.layout */ static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + u8 enable_vmx; + + if (get_option(&enable_vmx, "enable_vmx") != CB_SUCCESS) + enable_vmx = 0; /* Default to disable VMX */ regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -140,7 +144,7 @@ static void configure_vmx(void) */ msr.hi = msr.lo = 0; - printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + printk(BIOS_DEBUG, "%s VMX\n", enable_vmx ? "Enabling" : "Disabling"); /* Even though the Intel manual says you must set the lock bit in addition * to the VMX bit in order for VMX to work, it is incorrect. Thus we leave @@ -155,7 +159,7 @@ static void configure_vmx(void) * By leaving this to the OS (e.g. Linux), people can do exactly what they * want on the fly, and do it correctly (e.g. across multiple cores). */ - if (enable) { + if (enable_vmx) { msr.lo |= (1 << 2); if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 389a13c..4b0927f 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select MMCONF_SUPPORT select SUPERIO_SMSC_SIO1007 - select ENABLE_VMX select EARLY_CBMEM_INIT select BROKEN_CAR_MIGRATE select VGA diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index 2dfa156..b8d50a3 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -63,7 +63,8 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused +120 1 e 1 enable_vmx +#121 263 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index d1a7d42..226368f 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select ENABLE_VMX select HAVE_MRC config MAINBOARD_DIR diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 245b47e..b9577e0 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -63,7 +63,8 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused +120 1 e 1 enable_vmx +#121 263 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded)

1 0

Patch set updated for coreboot: c474867 cpu/intel: Rename 'enable_vmx()' func to 'configure_vmx()'
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6414 -gerrit commit c474867e5a28cd5e2931d3e0f4c3d12e5c505435 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 12:44:35 2014 +1000 cpu/intel: Rename 'enable_vmx()' func to 'configure_vmx()' In preparation for introduce runtime configurable VMX feature bit setting in cmos.layout. Change-Id: I3997348fdf2d66f2ea7c9b6e64c8ab98f1cd7858 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++-- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++-- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index c2f9f19..b375d60 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -36,7 +36,7 @@ #include "model_206ax.h" #include "chip.h" -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -373,7 +373,7 @@ static void model_206ax_init(device_t cpu) setup_lapic(); /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + configure_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 043ba3a..1d1fef4 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,7 +150,7 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -745,7 +745,7 @@ static void haswell_init(device_t cpu) setup_lapic(); /* Enable virtualization if Kconfig option is set */ - enable_vmx(); + configure_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 4779a51..88c506e 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -51,7 +51,7 @@ static void init_timer(void) #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -333,7 +333,7 @@ static void model_1067x_init(device_t cpu) init_timer(); /* Enable virtualization */ - enable_vmx(); + configure_vmx(); /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 73ee5cd..d44b538 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -34,7 +34,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -132,7 +132,7 @@ static void model_106cx_init(device_t cpu) setup_lapic(); /* Enable virtualization */ - enable_vmx(); + configure_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 9a2afa4..d1ec124 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -114,7 +114,7 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -369,7 +369,7 @@ static void model_2065x_init(device_t cpu) setup_lapic(); /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + configure_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4e56414..6debf3a 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -114,7 +114,7 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -562,7 +562,7 @@ static void model_206ax_init(device_t cpu) setup_lapic(); /* Enable virtualization if enabled in CMOS */ - enable_vmx(); + configure_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 8f9fbf8..4697b17 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -37,7 +37,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -163,7 +163,7 @@ static void model_6ex_init(device_t cpu) setup_lapic(); /* Enable virtualization */ - enable_vmx(); + configure_vmx(); /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 93635d4..1db70b9 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -36,7 +36,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) -static void enable_vmx(void) +static void configure_vmx(void) { struct cpuid_result regs; msr_t msr; @@ -186,7 +186,7 @@ static void model_6fx_init(device_t cpu) setup_lapic(); /* Enable virtualization */ - enable_vmx(); + configure_vmx(); /* Configure C States */ configure_c_states();

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Patch set updated for coreboot: beda287 lenovo/t530/mainboard.c: Include header `h8.h` for prototype
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6398 -gerrit commit beda287e72322186c98adc2057deddb0ee8d428a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 20:49:55 2014 +1000 lenovo/t530/mainboard.c: Include header `h8.h` for prototype Change-Id: I05cea020e77051bd3bc0e93b0c70e12b9b985d05 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/mainboard.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 6d21b31..325f90f 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -39,6 +39,7 @@ #include <device/pci.h> #include <cbfs.h> #include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> void mainboard_suspend_resume(void) { @@ -185,8 +186,6 @@ static void mainboard_enable(device_t dev) verb_setup(); } -void h8_mainboard_init_dock (void); - void h8_mainboard_init_dock (void) { }

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Patch set updated for coreboot: 0aa14d5 northbridge/intel/*/gma.c: Remove dead code
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6130 -gerrit commit 0aa14d5ed03ad15e2bb413e1a306661f5998571d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jun 26 22:33:03 2014 +1000 northbridge/intel/*/gma.c: Remove dead code Remove some dead coded spotted in Clang builds. Change-Id: Ia23e16eae76593eee249e0894ef1d704a274616f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/nehalem/gma.c | 56 --------------------------------- src/northbridge/intel/sandybridge/gma.c | 56 --------------------------------- 2 files changed, 112 deletions(-) diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index bc4c74d..2470b0f 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -144,62 +144,6 @@ static const struct gt_powermeter ivb_pm_gt1[] = { {0} }; -static const struct gt_powermeter ivb_pm_gt2[] = { - {0xa800, 0x10000000}, - {0xa804, 0x00033800}, - {0xa808, 0x00000902}, - {0xa80c, 0x0c002f00}, - {0xa810, 0x12000400}, - {0xa814, 0x00000000}, - {0xa818, 0x00d20800}, - {0xa81c, 0x00000002}, - {0xa820, 0x03004b02}, - {0xa824, 0x00000600}, - {0xa828, 0x07000773}, - {0xa82c, 0x00000000}, - {0xa830, 0x00010032}, - {0xa834, 0x1520040d}, - {0xa838, 0x00020105}, - {0xa83c, 0x00083700}, - {0xa840, 0x0000151d}, - {0xa844, 0x00000000}, - {0xa848, 0x20001b00}, - {0xa84c, 0x0a000010}, - {0xa850, 0x00000000}, - {0xa854, 0x00000008}, - {0xa858, 0x00000008}, - {0xa85c, 0x00000000}, - {0xa860, 0x00020000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00003500}, - {0xa908, 0x00000000}, - {0xa90c, 0x0c000000}, - {0xa910, 0x12000500}, - {0xa914, 0x00000000}, - {0xa918, 0x00b20000}, - {0xa91c, 0x00000000}, - {0xa920, 0x08004b02}, - {0xa924, 0x00000200}, - {0xa928, 0x07000820}, - {0xa92c, 0x00000000}, - {0xa930, 0x00030000}, - {0xa934, 0x050f020d}, - {0xa938, 0x00020300}, - {0xa93c, 0x00903900}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x20001b00}, - {0xa94c, 0x0a000010}, - {0xa950, 0x00000000}, - {0xa954, 0x00000008}, - {0xa960, 0x00110000}, - {0xaa3c, 0x00003900}, - {0xaa54, 0x00000008}, - {0xaa60, 0x00110000}, - {0} -}; - static const struct gt_powermeter ivb_pm_gt2_17w[] = { {0xa800, 0x20000000}, {0xa804, 0x000e3800}, diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index a01fe9f..0add055 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -139,62 +139,6 @@ static const struct gt_powermeter ivb_pm_gt1[] = { { 0 } }; -static const struct gt_powermeter ivb_pm_gt2[] = { - { 0xa800, 0x10000000 }, - { 0xa804, 0x00033800 }, - { 0xa808, 0x00000902 }, - { 0xa80c, 0x0c002f00 }, - { 0xa810, 0x12000400 }, - { 0xa814, 0x00000000 }, - { 0xa818, 0x00d20800 }, - { 0xa81c, 0x00000002 }, - { 0xa820, 0x03004b02 }, - { 0xa824, 0x00000600 }, - { 0xa828, 0x07000773 }, - { 0xa82c, 0x00000000 }, - { 0xa830, 0x00010032 }, - { 0xa834, 0x1520040d }, - { 0xa838, 0x00020105 }, - { 0xa83c, 0x00083700 }, - { 0xa840, 0x0000151d }, - { 0xa844, 0x00000000 }, - { 0xa848, 0x20001b00 }, - { 0xa84c, 0x0a000010 }, - { 0xa850, 0x00000000 }, - { 0xa854, 0x00000008 }, - { 0xa858, 0x00000008 }, - { 0xa85c, 0x00000000 }, - { 0xa860, 0x00020000 }, - { 0xa248, 0x0000221e }, - { 0xa900, 0x00000000 }, - { 0xa904, 0x00003500 }, - { 0xa908, 0x00000000 }, - { 0xa90c, 0x0c000000 }, - { 0xa910, 0x12000500 }, - { 0xa914, 0x00000000 }, - { 0xa918, 0x00b20000 }, - { 0xa91c, 0x00000000 }, - { 0xa920, 0x08004b02 }, - { 0xa924, 0x00000200 }, - { 0xa928, 0x07000820 }, - { 0xa92c, 0x00000000 }, - { 0xa930, 0x00030000 }, - { 0xa934, 0x050f020d }, - { 0xa938, 0x00020300 }, - { 0xa93c, 0x00903900 }, - { 0xa940, 0x00000000 }, - { 0xa944, 0x00000000 }, - { 0xa948, 0x20001b00 }, - { 0xa94c, 0x0a000010 }, - { 0xa950, 0x00000000 }, - { 0xa954, 0x00000008 }, - { 0xa960, 0x00110000 }, - { 0xaa3c, 0x00003900 }, - { 0xaa54, 0x00000008 }, - { 0xaa60, 0x00110000 }, - { 0 } -}; - static const struct gt_powermeter ivb_pm_gt2_17w[] = { { 0xa800, 0x20000000 }, { 0xa804, 0x000e3800 },

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Patch set updated for coreboot: 7b40d11 device/oprom/realmode: Sanitize header inclusion
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6415 -gerrit commit 7b40d118a087a1d72f1b8d5beb027cf30cef71ba Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 13:53:04 2014 +1000 device/oprom/realmode: Sanitize header inclusion Alphabetise includes to avoid duplication. Change-Id: I7fa6998cd736bad2bab4a6b1a65d48a21d6220d9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/oprom/realmode/x86.c | 22 +++++++++++----------- src/device/oprom/realmode/x86.h | 2 +- src/device/oprom/realmode/x86_interrupts.c | 10 ++++++---- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 7dec258..fc3c40c 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -18,26 +18,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ -#include <device/pci.h> -#include <string.h> - #include <arch/io.h> +#include <arch/interrupt.h> #include <arch/registers.h> -#include <cpu/amd/lxdef.h> -#include <cpu/amd/vr.h> +#include <boot/coreboot_tables.h> #include <cbfs.h> #include <console/console.h> -#include <arch/interrupt.h> -#include <cbfs.h> +#include <cpu/amd/lxdef.h> +#include <cpu/amd/vr.h> #include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <lib/jpeg.h> #include <pc80/i8259.h> -#include "x86.h" +#include <string.h> #include <vbe.h> -#include <lib/jpeg.h> + /* we use x86emu's register file representation */ #include <x86emu/regs.h> -#include <boot/coreboot_tables.h> -#include <device/pci_ids.h> + +#include "x86.h" /* The following symbols cannot be used directly. They need to be fixed up * to point to the correct address location after the code has been copied diff --git a/src/device/oprom/realmode/x86.h b/src/device/oprom/realmode/x86.h index a811a56..a0c7a90 100644 --- a/src/device/oprom/realmode/x86.h +++ b/src/device/oprom/realmode/x86.h @@ -52,4 +52,4 @@ int int12_handler(void); int int16_handler(void); int int1a_handler(void); -#endif +#endif /* __DEVICE_OPROM_REALMODE_X86_H__ */ diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 1ee6979..56a9b1b 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -19,17 +19,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ +#include <arch/io.h> +#include <arch/registers.h> +#include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> -#include <console/console.h> -#include <arch/io.h> -#include <arch/registers.h> -#include "x86.h" + /* we use x86emu's register file representation */ #include <x86emu/regs.h> +#include "x86.h" + // errors go in AH. Just set these up so that word assigns // will work. KISS. enum {

1 0

Patch merged into coreboot/master: 7842eb2 device/oprom/realmode/x86.c: Move includes to top of file
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 7842eb29972e8665da723566a2395e41621aedac Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 22:28:19 2014 +1000 device/oprom/realmode/x86.c: Move includes to top of file Change-Id: Ib68e1f570092a69447d307c33b98f70b817f0ec1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6401 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/6401 for details. -gerrit

1 0

Patch merged into coreboot/master: 51ca10f arch/x86/include/arch/interrupt.h: Add header guards
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 51ca10f54837c0e6f08561c6f85dd0d766622a82 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 22:27:51 2014 +1000 arch/x86/include/arch/interrupt.h: Add header guards Change-Id: I34c27bbce3ce958a33d547c727d9733d3b2d1670 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6400 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/6400 for details. -gerrit

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coreboot-gerrit July 2014