coreboot-gerrit July 2014

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Patch merged into coreboot/master: 9780452 payloads/external/SeaBIOS: Update makefile for olddefconfig
by gerrit＠coreboot.org 31 Jul '14

31 Jul '14

the following patch was just integrated into master: commit 97804520bdf63816a71663824b8c514f949a0225 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:24:32 2014 -0600 payloads/external/SeaBIOS: Update makefile for olddefconfig Instead of creating the SeaBIOS .config file for QEMU, then changing things to be coreboot specific, create a default config for coreboot, then run olddefconfig to use the SeaBIOS defaults as they're set for coreboot. This leads to a cleaner config. Note that CONFIG_THREAD_OPTIONROMS defaults to enabled for SeaBIOS if we're building for coreboot, so I reversed the logic. I *ASSUMED* that leaving CONFIG_QEMU_HARDWARE=y and CONFIG_DEBUG_IO=y previously was an oversight. If this is not correct, please let me know and I'll add them it back in. SeaBIOS disables these by default if building for coreboot. Change-Id: I42c6a56205bb15c6693a5f3a716b7876a4d78abe Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6362 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6362 for details. -gerrit

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New patch to review for coreboot: dc6ca4a exynos5420: get rid of old exynos5420_config_l2_cache()
by Isaac Christensen 31 Jul '14

31 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6425 -gerrit commit dc6ca4a0c4a4921bfa87ceb75cd2eccb4b4c5a40 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 9 18:19:29 2013 -0700 exynos5420: get rid of old exynos5420_config_l2_cache() We set up L2 cache early in romstage now so the old function is now redundant. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef Reviewed-on: https://gerrit.chromium.org/gerrit/65428 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f) exynos: stack size: Increase the stack size to 16KB. The lzma decoding function in the RAM stage allocates nearly 16KB on the stack which is shared between the bootblock, rom stage, and ram stage. The stack had been much too small and needed to be expanded. Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65937 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b) exynos: gpio: add a bigger delay when reading board strappings Z-state pins were not reading reliably with a 5us delay, so increase it to 15us. This is ported from https://gerrit.chromium.org/gerrit/64338 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35 Reviewed-on: https://gerrit.chromium.org/gerrit/65727 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084) exynos5420: enable DMC internal clock gating lets enable memory controller internal clock gating for ddr3. with these bits enabled we save some power out of ddr3. This is ported from https://gerrit.chromium.org/gerrit/#/c/60774 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f Reviewed-on: https://gerrit.chromium.org/gerrit/65728 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781) exynos5420: Correct the 600MHz PMS value In UM ver0.02, 600MHz clock PMS values differs from what is programed currently. Though this also results in 600MHz clock, but it is better to match what UM says. This patch chnage this as per UM This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3 (Note: we already used the correct 600MHz value for KPLL) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5 Reviewed-on: https://gerrit.chromium.org/gerrit/65726 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f) Squashed five commits pertaining to exynos. Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/samsung/exynos5250/Kconfig | 8 ++++---- src/cpu/samsung/exynos5420/Kconfig | 18 +++++++++--------- src/cpu/samsung/exynos5420/clock_init.c | 2 +- src/cpu/samsung/exynos5420/cpu.c | 30 ------------------------------ src/cpu/samsung/exynos5420/cpu.h | 1 - src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 8 ++++++++ src/cpu/samsung/exynos5420/gpio.c | 4 ++-- src/cpu/samsung/exynos5420/setup.h | 8 ++++++++ src/cpu/samsung/exynos5420/smp.c | 5 ++++- src/mainboard/google/pit/mainboard.c | 1 - 10 files changed, 36 insertions(+), 49 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 91b691d..e0e179d 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -69,21 +69,21 @@ config STACK_TOP config STACK_BOTTOM hex - default 0x02077000 + default 0x02074000 config STACK_SIZE hex - default 0x1000 + default 0x4000 # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" - default 0x02060000 + default 0x0205c000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x000017000 + default 0x00018000 config SYS_SDRAM_BASE hex diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 6066040..d3eafcb 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -46,12 +46,12 @@ config CBFS_ROM_OFFSET # 0x0202_4400: variable length bootblock checksum header. # 0x0202_4410: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. -# 0x0206_0000: cache for CBFS data. +# 0x0205_c000: cache for CBFS data. +# 0x0206_f000: stack bottom +# 0x0207_3000: stack pointer # 0x0207_3000: shared (with kernel) page for cpu & secondary core states. # the shared data is currently only <0x50 bytes so we can share # this page with stack. -# 0x0207_3100: stack bottom -# 0x0207_4000: stack pointer config BOOTBLOCK_BASE hex @@ -63,7 +63,7 @@ config ROMSTAGE_BASE config ROMSTAGE_SIZE hex - default 0x10000 + default 0x20000 # Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. @@ -72,25 +72,25 @@ config ROMSTAGE_SIZE # consecutive memory locations ending just below SP config STACK_TOP hex - default 0x02074000 + default 0x02073000 config STACK_BOTTOM hex - default 0x02073100 + default 0x0206f000 config STACK_SIZE hex - default 0x0f00 + default 0x4000 # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" - default 0x02060000 + default 0x0205c000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x000013000 + default 0x00013000 config SYS_SDRAM_BASE hex diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 658b255..eeeda90 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -81,7 +81,7 @@ void system_clock_init(void) /* Set KPLL*/ writel(KPLL_CON1_VAL, &clk->kpll_con1); - val = set_pll(0xc8, 0x2, 0x2); + val = set_pll(0x190, 0x4, 0x2); writel(val, &clk->kpll_con0); while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) ; diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 176a3f2..3b87c6e 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -206,33 +206,3 @@ struct chip_operations cpu_samsung_exynos5420_ops = { CHIP_NAME("CPU Samsung Exynos 5420") .enable_dev = enable_exynos5420_dev, }; - -void exynos5420_config_l2_cache(void) -{ - uint32_t val; - - /* - * Bit 9 - L2 tag RAM setup (1 cycle) - * Bits 8:6 - L2 tag RAM latency (3 cycles) - * Bit 5 - L2 data RAM setup (1 cycle) - * Bits 2:0 - L2 data RAM latency (3 cycles) - */ - val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); - write_l2ctlr(val); - - val = read_l2actlr(); - - /* L2ACTLR[3]: Disable clean/evict push to external */ - val |= (1 << 3); - - /* L2ACTLR[7]: Enable hazard detect timeout for A15 */ - val |= (1 << 7); - - /* L2ACTLR[27]: Prevents stopping the L2 logic clock */ - val |= (1 << 27); - - write_l2actlr(val); - - /* Read the l2 control register to force things to take effect? */ - val = read_l2ctlr(); -} diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 08f315a..8d3d48b 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -263,7 +263,6 @@ static inline u32 get_fb_base_kb(void) } /* Procedures to setup Exynos5420 CPU */ -void exynos5420_config_l2_cache(void); void exynos5420_config_smp(void); #endif /* _EXYNOS5420_CPU_H */ diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index ebfe1e1..6c431f3 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -376,5 +376,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), &drex1->concontrol); + + /* Enable Clock Gating Control for DMC + * this saves around 25 mw dmc power as compared to the power + * consumption without these bits enabled + */ + setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); + setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + return 0; } diff --git a/src/cpu/samsung/exynos5420/gpio.c b/src/cpu/samsung/exynos5420/gpio.c index 2a93328..b17ff40 100644 --- a/src/cpu/samsung/exynos5420/gpio.c +++ b/src/cpu/samsung/exynos5420/gpio.c @@ -206,10 +206,10 @@ int gpio_set_value(unsigned gpio, int value) /* * Add a delay here to give the lines time to settle - * TODO(sjg): 1us does not always work, 2 is stable, so use 5 to be safe + * TODO(dianders): 5us does not always work, 10 is stable, so use 15 to be safe * Come back to this and sort out what the datasheet says */ -#define GPIO_DELAY_US 5 +#define GPIO_DELAY_US 15 #ifndef __BOOT_BLOCK__ /* diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 794d4e1..8f14a91 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -791,6 +791,14 @@ struct exynos5_phy_control; #define BRBRSVCONTROL_VAL 0x00000033 #define BRBRSVCONFIG_VAL 0x88778877 +/* Clock Gating Control (CGCONTROL) register */ +#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */ +#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */ +#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ +#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */ +#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \ + BUSIF_WR_CG_EN | BUSIF_RD_CG_EN) + /* DMC PHY Control0 register */ #define PHY_CONTROL0_RESET_VAL 0x0 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ diff --git a/src/cpu/samsung/exynos5420/smp.c b/src/cpu/samsung/exynos5420/smp.c index 392f82d..2a0656b 100644 --- a/src/cpu/samsung/exynos5420/smp.c +++ b/src/cpu/samsung/exynos5420/smp.c @@ -271,7 +271,10 @@ static void power_down_core(void) /* Configures the CPU states shard memory page and then shutdown all cores. */ static void configure_secondary_cores(void) { - configure_l2ctlr(); + if (get_bits(read_midr(), 4, 12) == PART_NUMBER_CORTEX_A15) { + configure_l2ctlr(); + configure_l2actlr(); + } /* Currently we use power_down_core as callback for each core to * shutdown itself, but it is also ok to directly set ARM_CORE*_CONFIG diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 190ad23..e453e67 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -434,7 +434,6 @@ static void mainboard_enable(device_t dev) /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ - exynos5420_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);

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Patch merged into coreboot/master: 6ccc45d timer: Add functions to initialize absolute timer structures.
by gerrit＠coreboot.org 31 Jul '14

31 Jul '14

the following patch was just integrated into master: commit 6ccc45d7d57056c2b9f172859894739d94cc723e Author: Gabe Black <gabeblack(a)google.com> Date: Fri Aug 9 00:48:06 2013 -0700 timer: Add functions to initialize absolute timer structures. Otherwise there's no good way to create an absolute timer structure without fiddling with its internal structure or assuming a zero initialized structure has a value of zero. Old-Change-Id: Iffe3b6b25ed7963fcfb66f749c531ea445ea4aeb Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65301 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit e2e5c1ef3bb2df95fdf0e33cb2d975a990d07a4a) exynos: Simplify the monotonic timer implementation. The previous implementation was overly complicated, and when used in the timestamp implementation produced some weird and broken results. Old-Change-Id: I3048028ddea0657b01b0c94f312764b38d1397e4 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65302 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit 6a3fde9a5b80cdac76d79c65d20d7dd1f1d9e557) Squashed two closely related commits. Change-Id: Ifc32d773f4f93d34275a81781001d080357fe8ef Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6406 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6406 for details. -gerrit

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Patch merged into coreboot/master: 82683ab libpayload: provide missing cbfs symbol
by gerrit＠coreboot.org 31 Jul '14

31 Jul '14

the following patch was just integrated into master: commit 82683ab9d4435d46d4d61cf58de32d405cbda84f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 28 09:25:32 2013 -0500 libpayload: provide missing cbfs symbol The generic cbfs code relies on the libpayload_init_default_cbfs_media symbol. However, none was provided for ARM. Provide an empty implementation that returns an error as there is no generic way to locate the default cbfs media. Old-Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56805 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit d3410c28ef9f37b832e2fa2d18351dda332bc9f7) libpayload: place dummy_media.c in correct object list The commit introducing dummy_media.c was placed in the libc object list. This wasn't correct. It should be in the libcbfs object list as well as guarded by CONFIG_CBFS. Old-Change-Id: Iace43fff8f85f60ecac5e6eb8350cd1f3ee9d35e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56925 (cherry picked from commit 7937c7c5e95a934593bc0cedd5f4496b4770c303) Squashed two related commits. Change-Id: I84cd132b44cc2ea5b29acf109a3562baaeede9c6 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6411 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6411 for details. -gerrit

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Patch merged into coreboot/master: 0682cfe armv7/exynos5420: Configure CPU cores for kernel to enable SMP.
by gerrit＠coreboot.org 31 Jul '14

31 Jul '14

the following patch was just integrated into master: commit 0682cfefdb888807bef6ee7f3bb81615282e0390 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Aug 6 20:37:55 2013 +0800 armv7/exynos5420: Configure CPU cores for kernel to enable SMP. The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6405 for details. -gerrit

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Patch set updated for coreboot: 408b748 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)
by HAOUAS Elyes 31 Jul '14

31 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6310 -gerrit commit 408b748b97722441914d6febbe71f03f3418b867 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 31 14:57:07 2014 +0200 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg) raminit failed.... Change-Id: I5e890bede569176c86cb3f6d6bd735c7736e852d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nec/945g-m4/Kconfig | 42 ++++ src/mainboard/nec/945g-m4/acpi/ec.asl | 49 +++++ src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 83 ++++++++ src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 ++++++++++ src/mainboard/nec/945g-m4/acpi/platform.asl | 90 +++++++++ src/mainboard/nec/945g-m4/acpi/superio.asl | 92 +++++++++ src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++++ src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++++ src/mainboard/nec/945g-m4/acpi_tables.c | 230 ++++++++++++++++++++++ src/mainboard/nec/945g-m4/board_info.txt | 7 + src/mainboard/nec/945g-m4/cmos.layout | 194 +++++++++++++++++++ src/mainboard/nec/945g-m4/devicetree.cb | 116 +++++++++++ src/mainboard/nec/945g-m4/dsdt.asl | 43 +++++ src/mainboard/nec/945g-m4/fadt.c | 155 +++++++++++++++ src/mainboard/nec/945g-m4/irq_tables.c | 61 ++++++ src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++++ src/mainboard/nec/945g-m4/mptable.c | 106 ++++++++++ src/mainboard/nec/945g-m4/romstage.c | 235 +++++++++++++++++++++++ src/mainboard/nec/945g-m4/smihandler.c | 49 +++++ src/mainboard/nec/945g-m4/superio_hwm.c | 161 ++++++++++++++++ src/mainboard/nec/945g-m4/superio_hwm.h | 25 +++ src/mainboard/nec/Kconfig | 4 + 22 files changed, 2076 insertions(+) diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl new file mode 100644 index 0000000..e6c30a0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ec.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..fb57b5e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for i945G */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 10 }, + Package() { 0x0001ffff, 1, 0, 11 }, + Package() { 0x0001ffff, 2, 0, 12 }, + Package() { 0x0001ffff, 3, 0, 13 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 10 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 10 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 10 }, + Package() { 0x001cffff, 1, 0, 11 }, + Package() { 0x001cffff, 2, 0, 12 }, + Package() { 0x001cffff, 3, 0, 13 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 17 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 13 }, + Package() { 0x001dffff, 3, 0, 12 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 11 }, + Package() { 0x001effff, 1, 0, 24 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 12 }, + Package() { 0x001fffff, 1, 0, 13 }, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..c108d3f --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl new file mode 100644 index 0000000..6770348 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/platform.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl new file mode 100644 index 0000000..997a33a --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/superio.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl new file mode 100644 index 0000000..d1774d4 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c new file mode 100644 index 0000000..e6a517e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi_tables.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801gx/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt new file mode 100644 index 0000000..8c6f8c8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/board_info.txt @@ -0,0 +1,7 @@ +Board name:945G-M4 (Rev: B) +Category: µATX 24.4 cm x 24.4 cm Form Factor +Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d… +ROM package: PLCC +ROM protocol: FWH +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout new file mode 100644 index 0000000..b3e8c4e --- /dev/null +++ b/src/mainboard/nec/945g-m4/cmos.layout @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb new file mode 100644 index 0000000..9978fcf --- /dev/null +++ b/src/mainboard/nec/945g-m4/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + end + device domain 0 on + device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770] + device pci 02.0 off end # 82945G/GZ Integrated Graphics Controller [8086:2772] + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8a" + register "pirqb_routing" = "0x85" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x87" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168] + device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] + device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] + device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] + device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] + device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] + device pci 1e.0 on end # 82801 PCI Bridge [8086:244e] + device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de] + device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] + + chip superio/winbond/w83627ehg # Super I/O Winbond + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + end + + device pnp 2e.106 on # Serial flash interface + io 0x60 = 0x100 + end + + device pnp 2e.007 on # GPIO 1 + end + + device pnp 2e.107 off # Game port + io 0x60 = 0x201 + end + + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + + device pnp 2e.307 on # GPIO 6 + end + + device pnp 2e.8 off # WDTO#, PLED + end + + device pnp 2e.009 on # GPIO 2 + end + + device pnp 2e.109 on # GPIO 3 + end + + device pnp 2e.209 on # GPIO 4 + end + + device pnp 2e.309 on # GPIO 5 + end + + device pnp 2e.a on # ACPI + end + + device pnp 2e.b on # Hardware monitor + io 0x60 = 0xa10 + irq 0x70 = 0 + end + + end # Winbond + end # LPC + + device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df] + device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0] + device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da] + end # i82801gx + end # domain 0 +end diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl new file mode 100644 index 0000000..f30c12d --- /dev/null +++ b/src/mainboard/nec/945g-m4/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/nec/945g-m4/fadt.c b/src/mainboard/nec/945g-m4/fadt.c new file mode 100644 index 0000000..b55f628 --- /dev/null +++ b/src/mainboard/nec/945g-m4/fadt.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 2; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c new file mode 100644 index 0000000..4b050fe --- /dev/null +++ b/src/mainboard/nec/945g-m4/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 14, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, + {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0}, + {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0}, + {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0}, + {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0}, + {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c new file mode 100644 index 0000000..d872d95 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include "superio_hwm.h" + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +// hwm_setup(); /* commented while debugging */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c new file mode 100644 index 0000000..aaa3069 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mptable.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + smp_write_processors(mc); + /* Bus: Bus ID Type */ + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 2, "PCI "); + my_smp_write_bus(mc, 3, "PCI "); + my_smp_write_bus(mc, 4, "ISA "); + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x1, 0x20, 0xfec00000); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13); + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); +/* mptable_lintsrc(mc, isa_bus); */ + /* Compute the checksums */ + return mptable_finalize(mc); +} +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 1); + return (unsigned long)smp_write_config_table(v); +} +/*MP Config Extended Table Entries: +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x600000000000 + address range: 0x148000000000 +Extended Table HOSED! +*/ diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..0ada1ef --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +//#include <cpu/intel/car.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ +/* values found unsing ./inteltool -g on nec bios */ + printk(BIOS_DEBUG, "GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, 0x64, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, 0x80, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, 0x82, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); + +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + +/* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ +// RCBA32(0x3110) = 0x00000001; + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + /* Enable IOAPIC */ + RCBA8(0x31ff)= 0x03; /* |= 3 << 24*/ + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + /*./inteltool -r on vendor bios*/ + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + int cbmem_was_initted; + if (bist == 0) + enable_lapic(); + ich7_enable_lpc(); + /* Set up the console */ + winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE /*0x3f8*/); + console_init(); + + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(boot_mode, NULL); + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + /* Chipset Errata! */ + fixup_i945_errata(); + +// u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); +// printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); +// ram_check(0x00000000, 0x000a0000); +// ram_check(0x100000, 0x0); + +//dump_pci_devices(); +//ram_check_nodie(0<<20,0); +//ram_check_nodie(2<<20,0); +//ram_check_nodie(1<<20,0); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); +dump_pci_devices(); +ram_check_nodie(0<<20,0); +ram_check_nodie(2<<20,0); +ram_check_nodie(1<<20,0); +// quick_ram_check(); + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode==2); +#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */ + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); + } +#endif /* CONFIG_HAVE_ACPI_RESUME */ +} diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c new file mode 100644 index 0000000..d1f4f7b --- /dev/null +++ b/src/mainboard/nec/945g-m4/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c new file mode 100644 index 0000000..e7a922b --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); // Index port + outb(value, HWM_BASE + 0x06); // Data port +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */ diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig index 525121f..b8bb2d6 100644 --- a/src/mainboard/nec/Kconfig +++ b/src/mainboard/nec/Kconfig @@ -24,9 +24,13 @@ choice config BOARD_NEC_POWERMATE_2000 bool "PowerMate 2000" +config BOARD_NEC_945G_M4 + bool "945g-m4" + endchoice source "src/mainboard/nec/powermate2000/Kconfig" +source "src/mainboard/nec/945g-m4/Kconfig" config MAINBOARD_VENDOR string

1 0

Patch set updated for coreboot: 4b50e35 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg)
by HAOUAS Elyes 31 Jul '14

31 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6310 -gerrit commit 4b50e35729eb0cc9b45e76640887d36fd00d513a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 31 14:57:07 2014 +0200 Add new board: 945g-m4 (LGA775 i945GC i82801gx w83627ehg) raminit failed.... Change-Id: I5e890bede569176c86cb3f6d6bd735c7736e852d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nec/945g-m4/Kconfig | 42 ++++ src/mainboard/nec/945g-m4/acpi/ec.asl | 49 +++++ src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 83 ++++++++ src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 ++++++++++ src/mainboard/nec/945g-m4/acpi/platform.asl | 90 +++++++++ src/mainboard/nec/945g-m4/acpi/superio.asl | 92 +++++++++ src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++++ src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++++ src/mainboard/nec/945g-m4/acpi_tables.c | 230 ++++++++++++++++++++++ src/mainboard/nec/945g-m4/board_info.txt | 7 + src/mainboard/nec/945g-m4/cmos.layout | 194 +++++++++++++++++++ src/mainboard/nec/945g-m4/devicetree.cb | 116 +++++++++++ src/mainboard/nec/945g-m4/dsdt.asl | 43 +++++ src/mainboard/nec/945g-m4/fadt.c | 155 +++++++++++++++ src/mainboard/nec/945g-m4/irq_tables.c | 61 ++++++ src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++++ src/mainboard/nec/945g-m4/mptable.c | 106 ++++++++++ src/mainboard/nec/945g-m4/romstage.c | 235 +++++++++++++++++++++++ src/mainboard/nec/945g-m4/smihandler.c | 49 +++++ src/mainboard/nec/945g-m4/superio_hwm.c | 161 ++++++++++++++++ src/mainboard/nec/945g-m4/superio_hwm.h | 25 +++ src/mainboard/nec/Kconfig | 4 + 22 files changed, 2076 insertions(+) diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl new file mode 100644 index 0000000..e6c30a0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ec.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..fb57b5e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for i945G */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 10 }, + Package() { 0x0001ffff, 1, 0, 11 }, + Package() { 0x0001ffff, 2, 0, 12 }, + Package() { 0x0001ffff, 3, 0, 13 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 10 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 10 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 10 }, + Package() { 0x001cffff, 1, 0, 11 }, + Package() { 0x001cffff, 2, 0, 12 }, + Package() { 0x001cffff, 3, 0, 13 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 17 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 13 }, + Package() { 0x001dffff, 3, 0, 12 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 11 }, + Package() { 0x001effff, 1, 0, 24 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 12 }, + Package() { 0x001fffff, 1, 0, 13 }, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..c108d3f --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl new file mode 100644 index 0000000..6770348 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/platform.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl new file mode 100644 index 0000000..997a33a --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/superio.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl new file mode 100644 index 0000000..d1774d4 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c new file mode 100644 index 0000000..e6a517e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi_tables.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801gx/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + current += 0x100; + ALIGN_CURRENT; + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt new file mode 100644 index 0000000..8c6f8c8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/board_info.txt @@ -0,0 +1,7 @@ +Board name:945G-M4 (Rev: B) +Category: µATX 24.4 cm x 24.4 cm Form Factor +Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d… +ROM package: PLCC +ROM protocol: FWH +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout new file mode 100644 index 0000000..b3e8c4e --- /dev/null +++ b/src/mainboard/nec/945g-m4/cmos.layout @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb new file mode 100644 index 0000000..9978fcf --- /dev/null +++ b/src/mainboard/nec/945g-m4/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + end + device domain 0 on + device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770] + device pci 02.0 off end # 82945G/GZ Integrated Graphics Controller [8086:2772] + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8a" + register "pirqb_routing" = "0x85" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x87" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168] + device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] + device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] + device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] + device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] + device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] + device pci 1e.0 on end # 82801 PCI Bridge [8086:244e] + device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de] + device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] + + chip superio/winbond/w83627ehg # Super I/O Winbond + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + end + + device pnp 2e.106 on # Serial flash interface + io 0x60 = 0x100 + end + + device pnp 2e.007 on # GPIO 1 + end + + device pnp 2e.107 off # Game port + io 0x60 = 0x201 + end + + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + + device pnp 2e.307 on # GPIO 6 + end + + device pnp 2e.8 off # WDTO#, PLED + end + + device pnp 2e.009 on # GPIO 2 + end + + device pnp 2e.109 on # GPIO 3 + end + + device pnp 2e.209 on # GPIO 4 + end + + device pnp 2e.309 on # GPIO 5 + end + + device pnp 2e.a on # ACPI + end + + device pnp 2e.b on # Hardware monitor + io 0x60 = 0xa10 + irq 0x70 = 0 + end + + end # Winbond + end # LPC + + device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df] + device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0] + device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da] + end # i82801gx + end # domain 0 +end diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl new file mode 100644 index 0000000..f30c12d --- /dev/null +++ b/src/mainboard/nec/945g-m4/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/nec/945g-m4/fadt.c b/src/mainboard/nec/945g-m4/fadt.c new file mode 100644 index 0000000..b55f628 --- /dev/null +++ b/src/mainboard/nec/945g-m4/fadt.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x20; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 2; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c new file mode 100644 index 0000000..4b050fe --- /dev/null +++ b/src/mainboard/nec/945g-m4/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 14, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, + {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0}, + {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0}, + {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0}, + {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0}, + {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c new file mode 100644 index 0000000..d872d95 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include "superio_hwm.h" + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +// hwm_setup(); /* commented while debugging */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c new file mode 100644 index 0000000..aaa3069 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mptable.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + smp_write_processors(mc); + /* Bus: Bus ID Type */ + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 2, "PCI "); + my_smp_write_bus(mc, 3, "PCI "); + my_smp_write_bus(mc, 4, "ISA "); + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x1, 0x20, 0xfec00000); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13); + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); +/* mptable_lintsrc(mc, isa_bus); */ + /* Compute the checksums */ + return mptable_finalize(mc); +} +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 1); + return (unsigned long)smp_write_config_table(v); +} +/*MP Config Extended Table Entries: +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x600000000000 + address range: 0x148000000000 +Extended Table HOSED! +*/ diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..3b50079 --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/car.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ +/* values found unsing ./inteltool -g on nec bios */ + printk(BIOS_DEBUG, "GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, 0x64, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, 0x80, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, 0x82, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); + +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + +/* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ +// RCBA32(0x3110) = 0x00000001; + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + /* Enable IOAPIC */ + RCBA8(0x31ff)= 0x03; /* |= 3 << 24*/ + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + /*./inteltool -r on vendor bios*/ + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + int cbmem_was_initted; + if (bist == 0) + enable_lapic(); + ich7_enable_lpc(); + /* Set up the console */ + winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE /*0x3f8*/); + console_init(); + + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + while (1) asm("hlt"); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT....: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(boot_mode, NULL); + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + /* Chipset Errata! */ + fixup_i945_errata(); + +// u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); +// printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); +// ram_check(0x00000000, 0x000a0000); +// ram_check(0x100000, 0x0); + +//dump_pci_devices(); +//ram_check_nodie(0<<20,0); +//ram_check_nodie(2<<20,0); +//ram_check_nodie(1<<20,0); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); +dump_pci_devices(); +ram_check_nodie(0<<20,0); +ram_check_nodie(2<<20,0); +ram_check_nodie(1<<20,0); +// quick_ram_check(); + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode==2); +#if CONFIG_HAVE_ACPI_RESUME /* !CONFIG_HAVE_ACPI_RESUME */ + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); + } +#endif /* CONFIG_HAVE_ACPI_RESUME */ +} diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c new file mode 100644 index 0000000..d1f4f7b --- /dev/null +++ b/src/mainboard/nec/945g-m4/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c new file mode 100644 index 0000000..e7a922b --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); // Index port + outb(value, HWM_BASE + 0x06); // Data port +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */ diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig index 525121f..b8bb2d6 100644 --- a/src/mainboard/nec/Kconfig +++ b/src/mainboard/nec/Kconfig @@ -24,9 +24,13 @@ choice config BOARD_NEC_POWERMATE_2000 bool "PowerMate 2000" +config BOARD_NEC_945G_M4 + bool "945g-m4" + endchoice source "src/mainboard/nec/powermate2000/Kconfig" +source "src/mainboard/nec/945g-m4/Kconfig" config MAINBOARD_VENDOR string

1 0

Patch set updated for coreboot: 75bd2ad Re-structuring Payload loading
by Naman Govil 31 Jul '14

31 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6303 -gerrit commit 75bd2ad21a4b990ab5cb40a04e3447b08f30bafc Author: Naman Govil <namangov(a)gmail.com> Date: Fri Jul 18 16:20:38 2014 +0530 Re-structuring Payload loading Removing dependency for mapping entire segments for payload loading by segragating segments by reading metadata and then processing them. Change-Id: I87a52cca7f0270cf7575d2bf5133e17fbb6c9470 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/payload_loader.h | 4 + src/lib/loaders/cbfs_payload_loader.c | 15 +- src/lib/loaders/load_and_run_payload.c | 3 - src/lib/selfboot.c | 275 ++++++++++++++++++++++++++------- 4 files changed, 228 insertions(+), 69 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..cac7d27 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <stdint.h> #include <stddef.h> +#include <cbfs_core.h> struct buffer_area { void *data; @@ -32,6 +34,8 @@ struct payload { struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; + struct cbfs_media *media; + struct cbfs_file_handle f; void *entry; }; diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..f0b5bbc 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,21 +20,21 @@ #include <cbfs.h> #include <payload_loader.h> +#include <cbfs_core.h> static int cbfs_locate_payload(struct payload *payload) { - void *buffer; - size_t size; const int type = CBFS_TYPE_PAYLOAD; + struct cbfs_media default_media, *m; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + m = &default_media; + if (init_default_cbfs_media(m) != 0) + return -1; - if (buffer == NULL) + if (cbfs_find_file(m, &payload->f, payload->name, type) < 0) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + payload->media = CBFS_DEFAULT_MEDIA; return 0; } diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..0dcecfb 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,6 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); break; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..ac092d1 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> - * + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,6 +28,7 @@ #include <lib.h> #include <bootmem.h> #include <payload_loader.h> +#include <cbfs_core.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; @@ -40,9 +41,9 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; unsigned long s_filesz; + unsigned long s_offset; int compression; }; @@ -66,6 +67,102 @@ struct segment { * and much simpler than the general case implemented in kexec. */ +struct sb_helper { + int (*init)(struct sb_helper *sbh, struct payload *payload); + int (*open)(struct payload *payload); + int (*close)(struct payload *payload); + size_t (*read)(struct payload *payload, void *dest, size_t offset, size_t size); + void *(*map)(struct payload *payload, size_t offset, size_t size); + void *sb_media; +}; + +static struct cbfs_media default_media; + +static int init_cbfs(struct sb_helper *sbh, struct payload *payload) +{ + /*Backing store is in use hence no loading via cbfs + */ + if (payload->backing_store.data != NULL) + return 0; + if (payload->media == CBFS_DEFAULT_MEDIA) { + sbh->sb_media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return 0; + } + } + return 1; +} + +static size_t cbfs_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + return payload->media->read(payload->media, dest, offset, size); +} + +static void *cbfs_map(struct payload *payload, size_t offset, size_t size) +{ + return payload->media->map(payload->media, offset, size); +} + +static int cbfs_open(struct payload *payload) +{ + payload->media->open(payload->media); + return 0; +} + +static int cbfs_close(struct payload *payload) +{ + payload->media->close(payload->media); + return 0; +} + +static int init_backing_store(struct sb_helper *sbh, struct payload *payload) +{ + if (payload->backing_store.data != NULL) + return 1; + else + return 0; +} + +static size_t backing_store_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + memcpy(dest, (void *)payload->backing_store.data + offset, size); + return size; +} + +static void *backing_store_map(struct payload *payload, size_t offset, size_t size) +{ + return (void *)payload->backing_store.data + offset; +} + +static int backing_store_open(struct payload *payload) +{ + return 0; +} + +static int backing_store_close(struct payload *payload) +{ + return 0; +} + +struct sb_helper cbfs_helper = { + .init = init_cbfs, + .open = cbfs_open, + .close = cbfs_close, + .read = cbfs_read, + .map = cbfs_map, + .sb_media = &default_media, +}; + +struct sb_helper backing_store_helper = { + .init = init_backing_store, + .open = backing_store_open, + .close = backing_store_close, + .read = backing_store_read, + .map = backing_store_map, + .sb_media = NULL, +}; + static unsigned long bounce_size, bounce_buffer; static void get_bounce_buffer(unsigned long req_size) @@ -140,7 +237,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_offset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +273,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_offset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -212,68 +309,95 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) } +static struct sb_helper *get_selfboot_method(struct payload *payload) +{ + struct sb_helper sbh; + if (cbfs_helper.init(&sbh, payload)) + return &cbfs_helper; + if (backing_store_helper.init(&sbh, payload)) + return &backing_store_helper; + return NULL; +} + static int build_self_segment_list( struct segment *head, struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + struct cbfs_payload_segment segment; + unsigned long current_offset; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + + if (sbh != NULL) { + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + current_offset = payload->f.data_offset; + sbh->open(payload); + + while(sbh->read(payload, &segment, current_offset, sizeof(segment)) + == sizeof(segment)) { + + printk(BIOS_DEBUG, "Reading segment from offset 0x%lx\n", current_offset); + segment.compression = ntohl(segment.compression); + segment.offset = ntohl(segment.offset); + segment.load_addr = ntohll(segment.load_addr); + segment.mem_len = ntohl(segment.mem_len); + segment.len = ntohl(segment.len); + + switch(segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; + current_offset += sizeof(segment); continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment.type == PAYLOAD_SEGMENT_CODE ? "code" : "data", + segment.compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; + new->s_filesz = segment.len; + new->s_offset = segment.offset; + + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_offset = segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment.load_addr); + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -285,27 +409,26 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; + current_offset += sizeof(segment); - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert to the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } - + sbh->close(payload); return 1; + } + else { + printk(BIOS_ERR, "Failed to build self_segments\n"); + return -1; + } } static int load_self_segments( @@ -315,6 +438,18 @@ static int load_self_segments( struct segment *ptr; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + if (sbh != NULL) { for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -362,7 +497,7 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src; + unsigned char *dest; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -378,7 +513,8 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + size_t v_read; + void *v_map; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -388,14 +524,31 @@ static int load_self_segments( switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - len = ulzma(src, dest); + printk(BIOS_DEBUG, "need to map first\n"); + sbh->open(payload); + v_map = sbh->map(payload, payload->f.data_offset + ptr->s_offset, + len); + + sbh->close(payload); + if (v_map == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + printk(BIOS_ERR, "Failed to map\n"); + return -1; + } + len = ulzma(v_map, dest); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + printk(BIOS_DEBUG, "it's not compressed! hence read directly\n"); + sbh->open(payload); + v_read = sbh->read(payload, dest, payload->f.data_offset + ptr->s_offset, + len); + sbh->close(payload); + if (v_read != len) { + printk(BIOS_ERR, "Reading of uncompressed segments not successful\n"); + return -1; + } break; } default: @@ -404,11 +557,10 @@ static int load_self_segments( } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx )\n", (unsigned long)dest, (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)end); /* Zero the extra bytes between middle & end */ if (middle < end) { @@ -439,6 +591,11 @@ static int load_self_segments( } } return 1; + } + else { + printk(BIOS_ERR, "Failed to load self_segments\n"); + return -1; + } } void *selfload(struct payload *payload)

1 0

Patch set updated for coreboot: 30d49ec Re-structuring Payload loading
by Naman Govil 31 Jul '14

31 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6303 -gerrit commit 30d49ece727ef8251ad38422fc493aade9c0a0d7 Author: Naman Govil <namangov(a)gmail.com> Date: Fri Jul 18 16:20:38 2014 +0530 Re-structuring Payload loading Removing dependency for mapping entire segments for payload loading by segragating segments by reading metadata and then processing them. Change-Id: I87a52cca7f0270cf7575d2bf5133e17fbb6c9470 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/payload_loader.h | 4 + src/lib/loaders/cbfs_payload_loader.c | 15 +- src/lib/loaders/load_and_run_payload.c | 3 - src/lib/selfboot.c | 275 ++++++++++++++++++++++++++------- 4 files changed, 228 insertions(+), 69 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..cac7d27 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <stdint.h> #include <stddef.h> +#include <cbfs_core.h> struct buffer_area { void *data; @@ -32,6 +34,8 @@ struct payload { struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; + struct cbfs_media *media; + struct cbfs_file_handle f; void *entry; }; diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..f0b5bbc 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,21 +20,21 @@ #include <cbfs.h> #include <payload_loader.h> +#include <cbfs_core.h> static int cbfs_locate_payload(struct payload *payload) { - void *buffer; - size_t size; const int type = CBFS_TYPE_PAYLOAD; + struct cbfs_media default_media, *m; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + m = &default_media; + if (init_default_cbfs_media(m) != 0) + return -1; - if (buffer == NULL) + if (cbfs_find_file(m, &payload->f, payload->name, type) < 0) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + payload->media = CBFS_DEFAULT_MEDIA; return 0; } diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..0dcecfb 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,6 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); break; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..caa2046 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> - * + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,6 +28,7 @@ #include <lib.h> #include <bootmem.h> #include <payload_loader.h> +#include <cbfs_core.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; @@ -40,9 +41,9 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; unsigned long s_filesz; + unsigned long s_offset; int compression; }; @@ -66,6 +67,102 @@ struct segment { * and much simpler than the general case implemented in kexec. */ +struct sb_helper { + int (*init)(struct sb_helper *sbh, struct payload *payload); + int (*open)(struct payload *payload); + int (*close)(struct payload *payload); + size_t (*read)(struct payload *payload, void *dest, size_t offset, size_t size); + void *(*map)(struct payload *payload, size_t offset, size_t size); + void *sb_media; +}; + +static struct cbfs_media default_media; + +static int init_cbfs(struct sb_helper *sbh, struct payload *payload) +{ + /*Backing store is in use hence no loading via cbfs + */ + if (payload->backing_store.data != NULL) + return 0; + if (payload->media == CBFS_DEFAULT_MEDIA) { + sbh->sb_media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return 0; + } + } + return 1; +} + +static size_t cbfs_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + return payload->media->read(payload->media, dest, offset, size); +} + +static void *cbfs_map(struct payload *payload, size_t offset, size_t size) +{ + return payload->media->map(paylaod->media, offset, size); +} + +static int cbfs_open(struct payload *payload) +{ + payload->media->open(payload->media); + return 0; +} + +static int cbfs_close(struct payload *payload) +{ + payload->media->close(payload->media); + return 0; +} + +static int init_backing_store(struct sb_helper *sbh, struct payload *payload) +{ + if (payload->backing_store.data != NULL) + return 1; + else + return 0; +} + +static size_t backing_store_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + memcpy(dest, (void *)payload->backing_store.data + offset, size); + return size; +} + +static void *backing_store_map(struct payload *payload, size_t offset, size_t size) +{ + return (void *)payload->backing_store.data + offset; +} + +static int backing_store_open(struct payload *payload) +{ + return 0; +} + +static int backing_store_close(struct payload *payload) +{ + return 0; +} + +struct sb_helper cbfs_helper = { + .init = init_cbfs, + .open = cbfs_open, + .close = cbfs_close, + .read = cbfs_read, + .map = cbfs_map, + .sb_media = &default_media, +}; + +struct sb_helper backing_store_helper = { + .init = init_backing_store, + .open = backing_store_open, + .close = backing_store_close, + .read = backing_store_read, + .map = backing_store_map, + .sb_media = NULL, +}; + static unsigned long bounce_size, bounce_buffer; static void get_bounce_buffer(unsigned long req_size) @@ -140,7 +237,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_offset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +273,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_offset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -212,68 +309,95 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) } +static struct sb_helper *get_selfboot_method(struct payload *payload) +{ + struct sb_helper sbh; + if (cbfs_helper.init(&sbh, payload)) + return &cbfs_helper; + if (backing_store_helper.init(&sbh, payload)) + return &backing_store_helper; + return NULL; +} + static int build_self_segment_list( struct segment *head, struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + struct cbfs_payload_segment segment; + unsigned long current_offset; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + + if (sbh != NULL) { + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + current_offset = payload->f.data_offset; + sbh->open(payload); + + while(sbh->read(payload, &segment, current_offset, sizeof(segment)) + == sizeof(segment)) { + + printk(BIOS_DEBUG, "Reading segment from offset 0x%lx\n", current_offset); + segment.compression = ntohl(segment.compression); + segment.offset = ntohl(segment.offset); + segment.load_addr = ntohll(segment.load_addr); + segment.mem_len = ntohl(segment.mem_len); + segment.len = ntohl(segment.len); + + switch(segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; + current_offset += sizeof(segment); continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment.type == PAYLOAD_SEGMENT_CODE ? "code" : "data", + segment.compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; + new->s_filesz = segment.len; + new->s_offset = segment.offset; + + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_offset = segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment.load_addr); + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -285,27 +409,26 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; + current_offset += sizeof(segment); - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert to the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } - + sbh->close(payload); return 1; + } + else { + printk(BIOS_ERR, "Failed to build self_segments\n"); + return -1; + } } static int load_self_segments( @@ -315,6 +438,18 @@ static int load_self_segments( struct segment *ptr; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + if (sbh != NULL) { for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -362,7 +497,7 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src; + unsigned char *dest; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -378,7 +513,8 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + size_t v_read; + void *v_map; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -388,14 +524,31 @@ static int load_self_segments( switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - len = ulzma(src, dest); + printk(BIOS_DEBUG, "need to map first\n"); + sbh->open(payload); + v_map = sbh->map(payload, payload->f.data_offset + ptr->s_offset, + len); + + sbh->close(payload); + if (v_map == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + printk(BIOS_ERR, "Failed to map\n"); + return -1; + } + len = ulzma(v_map, dest); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + printk(BIOS_DEBUG, "it's not compressed! hence read directly\n"); + sbh->open(payload); + v_read = sbh->read(payload, dest, payload->f.data_offset + ptr->s_offset, + len); + sbh->close(payload); + if (v_read != len) { + printk(BIOS_ERR, "Reading of uncompressed segments not successful\n"); + return -1; + } break; } default: @@ -404,11 +557,10 @@ static int load_self_segments( } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx )\n", (unsigned long)dest, (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)end); /* Zero the extra bytes between middle & end */ if (middle < end) { @@ -439,6 +591,11 @@ static int load_self_segments( } } return 1; + } + else { + printk(BIOS_ERR, "Failed to load self_segments\n"); + return -1; + } } void *selfload(struct payload *payload)

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Patch set updated for coreboot: bfac3d9 Re-structuring Payload loading
by Naman Govil 31 Jul '14

31 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6303 -gerrit commit bfac3d9b5507f836833e6b9928a68e980337e525 Author: Naman Govil <namangov(a)gmail.com> Date: Fri Jul 18 16:20:38 2014 +0530 Re-structuring Payload loading Removing dependency for mapping entire segments for payload loading by segragating segments by reading metadata and then processing them. Change-Id: I87a52cca7f0270cf7575d2bf5133e17fbb6c9470 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/payload_loader.h | 4 + src/lib/loaders/cbfs_payload_loader.c | 15 +- src/lib/loaders/load_and_run_payload.c | 3 - src/lib/selfboot.c | 275 ++++++++++++++++++++++++++------- 4 files changed, 228 insertions(+), 69 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..cac7d27 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <stdint.h> #include <stddef.h> +#include <cbfs_core.h> struct buffer_area { void *data; @@ -32,6 +34,8 @@ struct payload { struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; + struct cbfs_media *media; + struct cbfs_file_handle f; void *entry; }; diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..f0b5bbc 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,21 +20,21 @@ #include <cbfs.h> #include <payload_loader.h> +#include <cbfs_core.h> static int cbfs_locate_payload(struct payload *payload) { - void *buffer; - size_t size; const int type = CBFS_TYPE_PAYLOAD; + struct cbfs_media default_media, *m; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + m = &default_media; + if (init_default_cbfs_media(m) != 0) + return -1; - if (buffer == NULL) + if (cbfs_find_file(m, &payload->f, payload->name, type) < 0) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + payload->media = CBFS_DEFAULT_MEDIA; return 0; } diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..0dcecfb 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,6 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); break; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..328c9ef 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> - * + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,6 +28,7 @@ #include <lib.h> #include <bootmem.h> #include <payload_loader.h> +#include <cbfs_core.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; @@ -40,9 +41,9 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; unsigned long s_filesz; + unsigned long s_offset; int compression; }; @@ -66,6 +67,102 @@ struct segment { * and much simpler than the general case implemented in kexec. */ +struct sb_helper { + int (*init)(struct sb_helper *sbh, struct payload *payload); + int (*open)(struct payload *payload); + int (*close)(struct payload *payload); + size_t (*read)(struct payload *payload, void *dest, size_t offset, size_t size); + void *(*map)(struct payload *payload, size_t offset, size_t size); + void *sb_media; +}; + +static struct cbfs_media default_media; + +static int init_cbfs(struct sb_helper *sbh, struct payload *payload) +{ + /*Backing store is in use hence no loading via cbfs + */ + if (payload->backing_store.data != NULL) + return 0; + if (payload->media == CBFS_DEFAULT_MEDIA) { + sbh->sb_media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return 0; + } + } + return 1; +} + +static size_t cbfs_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + return payload->media->read(payload->media, dest, offset, size); +} + +static void *cbfs_map(struct payload *payload, size_t offset, size_t size) +{ + return payload->media->map(paylaod->media, offset, size); +} + +static int cbfs_close(struct payload *payload) +{ + payload->media->open(payload->media); + return 0; +} + +static int cbfs_close(struct payload *payload) +{ + payload->media->close(payload->media); + return 0; +} + +static int init_backing_store(struct sb_helper *sbh, struct payload *payload) +{ + if (payload->backing_store.data != NULL) + return 1; + else + return 0; +} + +static size_t backing_store_read(struct payload *payload, void *dest, size_t offset, size_t size) +{ + memcpy(dest, (void *)payload->backing_store.data + offset, size); + return size; +} + +static void *backing_store_map(struct payload *payload, size_t offset, size_t size) +{ + return (void *)payload->backing_store.data + offset; +} + +static int backing_store_open(struct payload *payload) +{ + return 0; +} + +static int backing_store_close(struct payload *payload) +{ + return 0; +} + +struct sb_helper cbfs_helper = { + .init = init_cbfs, + .open = cbfs_open, + .close = cbfs_close, + .read = cbfs_read, + .map = cbfs_map, + .sb_media = &default_media, +}; + +struct sb_helper backing_store_helper = { + .init = init_backing_store, + .open = backing_store_open, + .close = backing_store_close, + .read = backing_store_read, + .map = backing_store_map, + .sb_media = NULL, +}; + static unsigned long bounce_size, bounce_buffer; static void get_bounce_buffer(unsigned long req_size) @@ -140,7 +237,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_offset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +273,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_offset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -212,68 +309,95 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) } +static struct sb_helper *get_selfboot_method(struct payload *payload) +{ + struct sb_helper sbh; + if (cbfs_helper.init(&sbh, payload)) + return &cbfs_helper; + if (backing_store_helper.init(&sbh, payload)) + return &backing_store_helper; + return NULL; +} + static int build_self_segment_list( struct segment *head, struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + struct cbfs_payload_segment segment; + unsigned long current_offset; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + + if (sbh != NULL) { + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + current_offset = payload->f.data_offset; + sbh->open(payload); + + while(sbh->read(sbh, &segment, current_offset, sizeof(segment)) + == sizeof(segment)) { + + printk(BIOS_DEBUG, "Reading segment from offset 0x%lx\n", current_offset); + segment.compression = ntohl(segment.compression); + segment.offset = ntohl(segment.offset); + segment.load_addr = ntohll(segment.load_addr); + segment.mem_len = ntohl(segment.mem_len); + segment.len = ntohl(segment.len); + + switch(segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; + current_offset += sizeof(segment); continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment.type == PAYLOAD_SEGMENT_CODE ? "code" : "data", + segment.compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; + new->s_filesz = segment.len; + new->s_offset = segment.offset; + + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_offset = segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment.load_addr); + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -285,27 +409,26 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; + current_offset += sizeof(segment); - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert to the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } - + sbh->close(payload); return 1; + } + else { + printk(BIOS_ERR, "Failed to build self_segments\n"); + return -1; + } } static int load_self_segments( @@ -315,6 +438,18 @@ static int load_self_segments( struct segment *ptr; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + struct sb_helper *sbh; + + if (payload->media == CBFS_DEFAULT_MEDIA) { + payload->media = &default_media; + if (init_default_cbfs_media(payload->media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + + sbh = get_selfboot_method(payload); + if (sbh != NULL) { for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -362,7 +497,7 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src; + unsigned char *dest; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -378,7 +513,8 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + size_t v_read; + void *v_map; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -388,14 +524,31 @@ static int load_self_segments( switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - len = ulzma(src, dest); + printk(BIOS_DEBUG, "need to map first\n"); + sbh->open(payload); + v_map = sbh->map(payload, payload->f.data_offset + ptr->s_offset, + len); + + sbh->close(payload); + if (v_map == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + printk(BIOS_ERR, "Failed to map\n"); + return -1; + } + len = ulzma(v_map, dest); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + printk(BIOS_DEBUG, "it's not compressed! hence read directly\n"); + sbh->open(payload); + v_read = sbh->read(payload, dest, payload->f.data_offset + ptr->s_offset, + len); + sbh->close(payload); + if (v_read != len) { + printk(BIOS_ERR, "Reading of uncompressed segments not successful\n"); + return -1; + } break; } default: @@ -404,11 +557,10 @@ static int load_self_segments( } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx )\n", (unsigned long)dest, (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)end); /* Zero the extra bytes between middle & end */ if (middle < end) { @@ -439,6 +591,11 @@ static int load_self_segments( } } return 1; + } + else { + printk(BIOS_ERR, "Failed to load self_segments\n"); + return -1; + } } void *selfload(struct payload *payload)

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coreboot-gerrit July 2014