coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 370adee model_206ax_init.c: Trivial - fix indent
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 370adeedb455a0d3880637ddfc3b8afee6080b5c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 30 11:44:29 2014 +1000 model_206ax_init.c: Trivial - fix indent Change-Id: I84876c95522fca5560bcbc8e81dfcb09faf3b326 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6412 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/6412 for details. -gerrit

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New patch to review for coreboot: c31f892 peppy: Force enable ASPM on PCIe Root Port 1
by Isaac Christensen 30 Jul '14

30 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6419 -gerrit commit c31f8920503d37274c21e156a34c42648314bd85 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Aug 21 11:47:11 2013 -0700 peppy: Force enable ASPM on PCIe Root Port 1 (Clone of Falco change Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8) Old-Change-Id: I5feba8fdbafba6d2de9f7d3de6170defc0d45a32 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66536 Reviewed-by: Dave Parker <dparker(a)chromium.org> (cherry picked from commit b78a872a6647d7bb82f6c06a75e4075e451a1622) peppy: Disable unused clocks CLKOUT for PCIE ports 2-5 and CLKOUT_XDP are not used and can be disabled. This change was modled after the change made in Falco: Falco-Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b The only difference per schematic for Peppy was PCIe 1 supports a NGFF interface. PCIe 0 is connected to WLAN. Old-Change-Id: Ib4871cb2655316cb260ab33ada6b9d81f271377f Signed-off-by: Steven Sherk <steven.sherk(a)se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66693 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 8f12335013a510dee3c21b55251ab00c0fbac609) Squashed two related commits. Change-Id: Ibc5b902018eec07fdccaa8c6cb066ce918f6a6b5 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/peppy/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index b19f04b..4c0d02d 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -78,6 +78,12 @@ chip northbridge/intel/haswell register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA

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Patch merged into coreboot/master: d11ff6b build system: remove duplicate architecture list
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit d11ff6b9dfae82266fd9862421e395f6d9c436dc Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 20:38:21 2014 +0200 build system: remove duplicate architecture list Let xcompile pass the list of architectures, given that it already has it. Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6254 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/6254 for details. -gerrit

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Patch set updated for coreboot: ac7ccc7 armv7: add wrapper for DCCSW (data cache clean by set/way)
by Isaac Christensen 30 Jul '14

30 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6418 -gerrit commit ac7ccc7ab1d52071f82dc1a3b5274597cc16ead8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 16 12:17:50 2013 -0700 armv7: add wrapper for DCCSW (data cache clean by set/way) This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/armv7/cache.c | 9 +++++++++ payloads/libpayload/include/armv7/arch/cache.h | 16 ++++++++++++++++ src/arch/armv7/cache.c | 18 ++++++++++++++++++ src/arch/armv7/include/arch/cache.h | 11 +++++++++++ src/arch/armv7/stages.c | 2 +- 5 files changed, 55 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/armv7/cache.c index efdf75e..b4a937b 100644 --- a/payloads/libpayload/arch/armv7/cache.c +++ b/payloads/libpayload/arch/armv7/cache.c @@ -76,6 +76,7 @@ void icache_invalidate_all(void) } enum dcache_op { + OP_DCCSW, OP_DCCISW, OP_DCISW, OP_DCCIMVAC, @@ -142,6 +143,9 @@ static void dcache_op_set_way(enum dcache_op op) case OP_DCISW: dcisw(val); break; + case OP_DCCSW: + dccsw(val); + break; default: break; } @@ -175,6 +179,11 @@ static void dcache_foreach(enum dcache_op op) } } +void dcache_clean_all(void) +{ + dcache_foreach(OP_DCCSW); +} + void dcache_clean_invalidate_all(void) { dcache_foreach(OP_DCCISW); diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h index 0414da3..0756f11 100644 --- a/payloads/libpayload/include/armv7/arch/cache.h +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -110,6 +110,12 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory"); } +/* invalidate unified TLB by MVA, all ASID */ +static inline void tlbimvaa(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory"); +} + /* write data access control register (DACR) */ static inline void write_dacr(uint32_t val) { @@ -164,6 +170,12 @@ static inline void dccmvac(unsigned long mva) asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory"); } +/* data cache clean by set/way */ +static inline void dccsw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory"); +} + /* data cache invalidate by MVA to PoC */ static inline void dcimvac(unsigned long mva) { @@ -286,6 +298,8 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate by modified virtual address to PoC */ void dcache_invalidate_by_mva(unsigned long addr, unsigned long len); +void dcache_clean_all(void); + /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); @@ -317,6 +331,8 @@ enum dcache_policy { DCACHE_WRITETHROUGH, }; +/* disable the mmu for a range. Primarily useful to lock out address 0. */ +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); /* mmu range configuration (set dcache policy) */ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, enum dcache_policy policy); diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c index 4046451..b4a937b 100644 --- a/src/arch/armv7/cache.c +++ b/src/arch/armv7/cache.c @@ -76,10 +76,12 @@ void icache_invalidate_all(void) } enum dcache_op { + OP_DCCSW, OP_DCCISW, OP_DCISW, OP_DCCIMVAC, OP_DCCMVAC, + OP_DCIMVAC, }; /* @@ -141,6 +143,9 @@ static void dcache_op_set_way(enum dcache_op op) case OP_DCISW: dcisw(val); break; + case OP_DCCSW: + dccsw(val); + break; default: break; } @@ -174,6 +179,11 @@ static void dcache_foreach(enum dcache_op op) } } +void dcache_clean_all(void) +{ + dcache_foreach(OP_DCCSW); +} + void dcache_clean_invalidate_all(void) { dcache_foreach(OP_DCCISW); @@ -220,6 +230,9 @@ static void dcache_op_mva(unsigned long addr, case OP_DCCMVAC: dccmvac(line); break; + case OP_DCIMVAC: + dcimvac(line); + break; default: break; } @@ -238,6 +251,11 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } +void dcache_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCIMVAC); +} + void dcache_mmu_disable(void) { uint32_t sctlr; diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 8a14ff9..0756f11 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -170,6 +170,12 @@ static inline void dccmvac(unsigned long mva) asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory"); } +/* data cache clean by set/way */ +static inline void dccsw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory"); +} + /* data cache invalidate by MVA to PoC */ static inline void dcimvac(unsigned long mva) { @@ -289,6 +295,11 @@ void dcache_clean_by_mva(unsigned long addr, unsigned long len); /* dcache clean and invalidate by modified virtual address to PoC */ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); +/* dcache invalidate by modified virtual address to PoC */ +void dcache_invalidate_by_mva(unsigned long addr, unsigned long len); + +void dcache_clean_all(void); + /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index 0d2072d..38d1b19 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -52,7 +52,7 @@ void stage_exit(void *addr) /* make sure any code we installed is written to memory. Not all ARM have * unified caches. */ - dcache_clean_invalidate_all(); + dcache_clean_all(); /* Because most stages copy code to memory, it's a safe and hygienic thing * to flush the icache here. */

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New patch to review for coreboot: 07f6c5e armv7: add wrapper for DCCSW (data cache clean by set/way)
by Isaac Christensen 30 Jul '14

30 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6418 -gerrit commit 07f6c5e2380ce3f6cb8e05ecf079cefd35efa47b Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Aug 16 12:17:50 2013 -0700 armv7: add wrapper for DCCSW (data cache clean by set/way) This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) Squashed three related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/armv7/cache.c | 6 ++++++ payloads/libpayload/include/armv7/arch/cache.h | 16 ++++++++++++++++ src/arch/armv7/cache.c | 15 +++++++++++++++ src/arch/armv7/include/arch/cache.h | 11 +++++++++++ src/arch/armv7/stages.c | 2 +- 5 files changed, 49 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/armv7/cache.c index efdf75e..644a870 100644 --- a/payloads/libpayload/arch/armv7/cache.c +++ b/payloads/libpayload/arch/armv7/cache.c @@ -76,6 +76,7 @@ void icache_invalidate_all(void) } enum dcache_op { + OP_DCCSW, OP_DCCISW, OP_DCISW, OP_DCCIMVAC, @@ -175,6 +176,11 @@ static void dcache_foreach(enum dcache_op op) } } +void dcache_clean_all(void) +{ + dcache_foreach(OP_DCCSW); +} + void dcache_clean_invalidate_all(void) { dcache_foreach(OP_DCCISW); diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h index 0414da3..0756f11 100644 --- a/payloads/libpayload/include/armv7/arch/cache.h +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -110,6 +110,12 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory"); } +/* invalidate unified TLB by MVA, all ASID */ +static inline void tlbimvaa(unsigned long mva) +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory"); +} + /* write data access control register (DACR) */ static inline void write_dacr(uint32_t val) { @@ -164,6 +170,12 @@ static inline void dccmvac(unsigned long mva) asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory"); } +/* data cache clean by set/way */ +static inline void dccsw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory"); +} + /* data cache invalidate by MVA to PoC */ static inline void dcimvac(unsigned long mva) { @@ -286,6 +298,8 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); /* dcache invalidate by modified virtual address to PoC */ void dcache_invalidate_by_mva(unsigned long addr, unsigned long len); +void dcache_clean_all(void); + /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); @@ -317,6 +331,8 @@ enum dcache_policy { DCACHE_WRITETHROUGH, }; +/* disable the mmu for a range. Primarily useful to lock out address 0. */ +void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); /* mmu range configuration (set dcache policy) */ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, enum dcache_policy policy); diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c index 4046451..644a870 100644 --- a/src/arch/armv7/cache.c +++ b/src/arch/armv7/cache.c @@ -76,10 +76,12 @@ void icache_invalidate_all(void) } enum dcache_op { + OP_DCCSW, OP_DCCISW, OP_DCISW, OP_DCCIMVAC, OP_DCCMVAC, + OP_DCIMVAC, }; /* @@ -174,6 +176,11 @@ static void dcache_foreach(enum dcache_op op) } } +void dcache_clean_all(void) +{ + dcache_foreach(OP_DCCSW); +} + void dcache_clean_invalidate_all(void) { dcache_foreach(OP_DCCISW); @@ -220,6 +227,9 @@ static void dcache_op_mva(unsigned long addr, case OP_DCCMVAC: dccmvac(line); break; + case OP_DCIMVAC: + dcimvac(line); + break; default: break; } @@ -238,6 +248,11 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len) dcache_op_mva(addr, len, OP_DCCIMVAC); } +void dcache_invalidate_by_mva(unsigned long addr, unsigned long len) +{ + dcache_op_mva(addr, len, OP_DCIMVAC); +} + void dcache_mmu_disable(void) { uint32_t sctlr; diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 8a14ff9..0756f11 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -170,6 +170,12 @@ static inline void dccmvac(unsigned long mva) asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory"); } +/* data cache clean by set/way */ +static inline void dccsw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory"); +} + /* data cache invalidate by MVA to PoC */ static inline void dcimvac(unsigned long mva) { @@ -289,6 +295,11 @@ void dcache_clean_by_mva(unsigned long addr, unsigned long len); /* dcache clean and invalidate by modified virtual address to PoC */ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len); +/* dcache invalidate by modified virtual address to PoC */ +void dcache_invalidate_by_mva(unsigned long addr, unsigned long len); + +void dcache_clean_all(void); + /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index 0d2072d..38d1b19 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -52,7 +52,7 @@ void stage_exit(void *addr) /* make sure any code we installed is written to memory. Not all ARM have * unified caches. */ - dcache_clean_invalidate_all(); + dcache_clean_all(); /* Because most stages copy code to memory, it's a safe and hygienic thing * to flush the icache here. */

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Patch merged into coreboot/master: ad488d2 src/console/Kconfig: Fix choice for showing POST codes on console
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit ad488d25b03c9abebe8187843f8d1301d242f106 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Wed Jul 30 12:23:35 2014 +0200 src/console/Kconfig: Fix choice for showing POST codes on console Use CONSOLE_POST because the preprocessor conditional in post_code() in src/console/post.c depends on it, while POST_IO is used in another conditional for sending the codes to an I/O port. Change-Id: Ia044cffb5f0aad0f8b2bb04faa12df11a705757a Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Reviewed-on: http://review.coreboot.org/6416 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/6416 for details. -gerrit

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Patch set updated for coreboot: b68f75b LZMA: Add a version of ulzma which takes the input and output buffer sizes.
by Isaac Christensen 30 Jul '14

30 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6408 -gerrit commit b68f75b82796eb5ab847c24b6e83489feaef7f1b Author: Gabe Black <gabeblack(a)google.com> Date: Sat Aug 10 09:35:56 2013 -0700 LZMA: Add a version of ulzma which takes the input and output buffer sizes. This new version is used to implement the version which doesn't take the input and output buffer sizes. Old-Change-Id: I8935024aca0849bc939263d7fc3036c586e63c68 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65510 Reviewed-by: Kees Cook <keescook(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 465d167ad2f6a67d0b2c91fb6c68c8f9a09dd395) libpayload: Make lzma truncation non-fatal. If the size the lzma header claims it needs is bigger than the space we have, print a message and continue rather than erroring out. Apparently the encoder is lazy sometimes and just puts a large value there regardless of what the actual size is. This was the original intention for this code, but an outdated version of the patch ended up being submitted. Old-Change-Id: Ibcf7ac0fd4b65ce85377421a4ee67b82d92d29d3 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66235 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 30c628eeada274fc8b94f8f69f9df4f33cbfc773) Squashed two related commits and updated the commit message to be more clear. Change-Id: I484b5c1e3809781033d146609a35a9e5e666c8ed Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/include/lzma.h | 12 ++++++++++-- payloads/libpayload/liblzma/lzma.c | 18 ++++++++++++++---- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/lzma.h b/payloads/libpayload/include/lzma.h index 818c16d..523bc8c 100644 --- a/payloads/libpayload/include/lzma.h +++ b/payloads/libpayload/include/lzma.h @@ -30,10 +30,18 @@ #ifndef _LZMA_H #define _LZMA_H -/* decompresses the data stream at src to dst, determining its length from +/* Decompresses the data stream at src to dst. The sizes of the source and + * destination buffers are in srcn and dstn. + * + * Returns the decompressed size, or 0 on error + */ +unsigned long ulzman(const unsigned char *src, unsigned long srcn, + unsigned char *dst, unsigned long dstn); + +/* Decompresses the data stream at src to dst, determining its length from * the data stream itself. * - * returns the decompressed size, or 0 on error + * Returns the decompressed size, or 0 on error */ unsigned long ulzma(const unsigned char *src, unsigned char *dst); diff --git a/payloads/libpayload/liblzma/lzma.c b/payloads/libpayload/liblzma/lzma.c index 0b97213..23c9562 100644 --- a/payloads/libpayload/liblzma/lzma.c +++ b/payloads/libpayload/liblzma/lzma.c @@ -14,9 +14,11 @@ #include <string.h> #include "lzmadecode.c" -unsigned long ulzma(const unsigned char * src, unsigned char * dst) +unsigned long ulzman(const unsigned char *src, unsigned long srcn, + unsigned char *dst, unsigned long dstn) { unsigned char properties[LZMA_PROPERTIES_SIZE]; + const int data_offset = LZMA_PROPERTIES_SIZE + 8; UInt32 outSize; SizeT inProcessed; SizeT outProcessed; @@ -27,7 +29,10 @@ unsigned long ulzma(const unsigned char * src, unsigned char * dst) memcpy(properties, src, LZMA_PROPERTIES_SIZE); memcpy(&outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize)); - if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { + if (outSize > dstn) + outSize = dstn; + if (LzmaDecodeProperties(&state.Properties, properties, + LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { printf("lzma: Incorrect stream properties.\n"); return 0; } @@ -37,11 +42,16 @@ unsigned long ulzma(const unsigned char * src, unsigned char * dst) return 0; } state.Probs = (CProb *)scratchpad; - res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed, - dst, outSize, &outProcessed); + res = LzmaDecode(&state, src + data_offset, srcn - data_offset, + &inProcessed, dst, outSize, &outProcessed); if (res != 0) { printf("lzma: Decoding error = %d\n", res); return 0; } return outSize; } + +unsigned long ulzma(const unsigned char *src, unsigned char *dst) +{ + return ulzman(src, (unsigned long)(-1), dst, (unsigned long)(-1)); +}

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Patch merged into coreboot/master: 90957f8 mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 90957f885294527ff9342f56d2e07c5a23fb1ce2 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed May 21 14:23:12 2014 -0600 mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000 Add the Mohon Peak CRB. Updates to come. Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/6371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6371 for details. -gerrit

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Patch merged into coreboot/master: 829c41d southbridge/intel: Add fsp_rangeley support
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 829c41da6cd9d8e9c9244c8c9ea2b181ea5ab930 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed May 21 14:21:22 2014 -0600 southbridge/intel: Add fsp_rangeley support This adds the southbridge initialization pieces for Intel's Atom C2000 processor (formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization. Change-Id: I416e85bd6e9c9dcf79f97785074135902fdd18b7 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/6370 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6370 for details. -gerrit

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Patch merged into coreboot/master: 2963ae7 northbridge/intel: Add fsp_rangeley northbridge support
by gerrit＠coreboot.org 30 Jul '14

30 Jul '14

the following patch was just integrated into master: commit 2963ae7fd49c7086ca9c4231f00a94e2f8a33080 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed May 21 14:20:38 2014 -0600 northbridge/intel: Add fsp_rangeley northbridge support This adds the northbridge initialization pieces for Intel's Atom C2000 processor (Formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization. Not currently supported: S3 suspend/resume CAR memory Migration (No early cbmem console) SMM Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/6369 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6369 for details. -gerrit

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