coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 1863b52 vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files
by Martin Roth 01 Aug '14

01 Aug '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6432 -gerrit commit 1863b5233055aa699008daefdf4772b98297a23d Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jul 31 16:50:18 2014 -0600 vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files The absf files contain the modifications to the default settings in the FSP. They are used as input files for Intel's 'Binary Configuration Tool' (BCT) along with the FSP.bin file to generate customized FSP binaries. The Minnow Max absf files set up the values for the soldered down memory. This requirement will go away with the release of the next Bay Trail FSP, and the memory settings will be configurable at runtime. Change-Id: Id72545d78a7e82d9a5090710a9c7a8a9b1e81208 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- .../intel/fsp/baytrail/absf/minnowmax_1gb.absf | 328 +++++++++++++++++++++ .../intel/fsp/baytrail/absf/minnowmax_2gb.absf | 328 +++++++++++++++++++++ 2 files changed, 656 insertions(+) diff --git a/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_1gb.absf b/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_1gb.absf new file mode 100755 index 0000000..66ab0d7 --- /dev/null +++ b/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_1gb.absf @@ -0,0 +1,328 @@ +// +// This file contains an 'Intel Peripheral Driver' and is +// licensed for Intel CPUs and chipsets under the terms of your +// license agreement with Intel or your vendor. This file must not +// be modified by end users or could render the generated boot loader +// inoperable. +// +// @file +// Boot Setting File for Platform: Bayley Bay Platform +// +// Copyright (c) 2010-2013 Intel Corporation. All rights reserved +// This software and associated documentation (if any) is furnished +// under a license and may only be used or copied in accordance +// with the terms of the license. Except as permitted by such +// license, no part of this software or documentation may be +// reproduced, stored in a retrieval system, or transmitted in any +// form or by any means without the express written consent of +// Intel Corporation. +// +// + + +GlobalDataDef + SKUID = 0 $_AS_BUILT_ = 0x01 , "DEFAULT" +EndGlobalData + +StructDef + + Find "VLV2UPDR" + Skip 24 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_AS_BUILT_ = 0x1, 0x0 $_DEFAULT_ = 0x0001 + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_AS_BUILT_ = 0x0, 0x8 $_DEFAULT_ = 0x0800 + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA0 + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA2 + $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdSataMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_AzaliaConfigPtr 4 bytes $_AS_BUILT_ = 0x0, 0x0, 0x0, 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + + Find "VLYVIEW1" + $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_AS_BUILT_ = 0x2, 0x3, 0x0, 0x0 $_DEFAULT_ = 0x00000302 + Skip 24 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 2 + + $DIMM_MemDown 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 + $DRAM_Speed 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 2 + $DRAM_Type 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $Rank_En_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $Rank_En_1_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $DIMM_DWidth_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 + $DIMM_Density_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $DIMM_BusWidth_0_0 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 3 + $DIMM_Sides_0_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $tCL 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 + $tRP_tRCD 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 + $tWR 1 byte $_AS_BUILT_ = 0x8 $_DEFAULT_ = 10 + $tWTR 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 + $tRRD 1 byte $_AS_BUILT_ = 0x6 $_DEFAULT_ = 4 + $tRTP 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 + $tFAW 1 byte $_AS_BUILT_ = 0x14 $_DEFAULT_ = 20 + +EndStruct + +List &DRAMSPEED + Selection 0x0 , "800 MHz" + Selection 0x1 , "1066 MHz" + Selection 0x2 , "1333 MHz" + Selection 0x3 , "1600 MHz" +EndList + +List &DRAMTYPE + Selection 0x0 , "DDR3" + Selection 0x1 , "DDR3L" + Selection 0x2 , "DDR3U" + //Selection 0x3 , "LPDDR2" + Selection 0x4 , "LPDDR2" + Selection 0x5 , "LPDDR3" + Selection 0x6 , "DDR4" +EndList + +List &DIMMDWIDTH + Selection 0x0 , "x8" + Selection 0x1 , "x16" + Selection 0x2 , "x32" +EndList + +List &DIMMDENSITY + Selection 0x0 , "1 Gbit" + Selection 0x1 , "2 Gbit" + Selection 0x2 , "4 Gbit" + Selection 0x3 , "8 Gbit" +EndList + +List &DIMMBUSWIDTH + Selection 0x0 , "8 bits" + Selection 0x1 , "16 bits" + Selection 0x2 , "32 bits" + Selection 0x3 , "64 bits" +EndList + +List &RANKPERDIMM + Selection 0x1 , "2 Ranks" + Selection 0x0 , "1 Rank" +EndList + +List &SATA_MODE + Selection 0x1 , "AHCI" + Selection 0x0 , "IDE" +EndList + +List &EMMC_MODES + Selection 0x0 , "Disabled" + Selection 0x1 , "Auto" + Selection 0x2 , "eMMC 4.1" + Selection 0x3 , "eMMC 4.5" +EndList + +List &EN_DIS + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &EN_DIS_AUTO + Selection 0x2 , "Auto" + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &MMIO_SIZES + Selection 0x400, "1.0 GB" + Selection 0x600, "1.5 GB" + Selection 0x800, "2.0 GB" +EndList + +List &TSEG_SIZES + Selection 0x01, "1 MB" + Selection 0x02, "2 MB" + Selection 0x04, "4 MB" + Selection 0x08, "8 MB" +EndList + +List &IGDPREALLOC_SIZES + Selection 0x01, "32 MB" + Selection 0x02, "64 MB" + Selection 0x03, "96 MB" + Selection 0x04, "128 MB" + Selection 0x05, "160 MB" + Selection 0x06, "192 MB" + Selection 0x07, "224 MB" + Selection 0x08, "256 MB" + Selection 0x09, "288 MB" + Selection 0x0A, "320 MB" + Selection 0x0B, "352 MB" + Selection 0x0C, "384 MB" + Selection 0x0D, "416 MB" + Selection 0x0E, "448 MB" + Selection 0x0F, "480 MB" + Selection 0x10, "512 MB" +EndList + +List &APERTURE_SIZES + Selection 0x1 , "128 MB" + Selection 0x2 , "256 MB" + Selection 0x3 , "512 MB" +EndList + +List &GTT_SIZES + Selection 0x1 , "1 MB" + Selection 0x2 , "2 MB" +EndList + +List &PCI_ACPI + Selection 0x2 , "ACPI Mode" + Selection 0x1 , "PCI Mode" + Selection 0x0 , "Disabled" +EndList + +List &PLATFORM_TYPE + Selection 0x2 , "BayleyBay Platform Type" + Selection 0x3 , "BakerSport Platform (ECC) Type" +EndList + +BeginInfoBlock + PPVer "1.0" + Description "MinnowMax" + +EndInfoBlock + +Page "Platform" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType, "Platform Type", &PLATFORM_TYPE, + Help "Select Platform Type." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, "Enable Secure Boot", &EN_DIS_AUTO, + Help "Enable/disable secure boot. Auto by default." +EndPage + +Page "North Complex" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &TSEG_SIZES, + Help "Size of memory reserved for SMRAM, in MB." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "Mmio Size", &MMIO_SIZES, + Help "Size of memory address space reserved for MMIO (Memory Mapped I/O), in GB." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory ", &IGDPREALLOC_SIZES, + Help "Size of memory preallocated for internal graphics" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &APERTURE_SIZES, + Help "Select the Aperture Size" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &GTT_SIZES, + Help "Select the GTT Size" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1, "DIMM 0 SPD SMBus Address", HEX, + Help "Address of DIMM 0. 8 bits" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2, "DIMM 1 SPD SMBus Address", HEX, + Help "Address of DIMM 1. 8 bits" +EndPage + +Page "Memory Down" + Combo $DIMM_MemDown, "Enable Memory Down", &EN_DIS, + Help "Enable = Memory Down, Disable = DIMM" + Combo $DRAM_Speed, "DRAM Speed", &DRAMSPEED, + Help "DRAM Speed" + Combo $DRAM_Type, "DRAM Type", &DRAMTYPE, + Help "DRAM Type" + Combo $Rank_En_0_0, "DIMM 0 Enable", &EN_DIS, + Help "Please populate DIMM slot 0 if only one DIMM is supported." + Combo $Rank_En_1_0, "DIMM 1 Enable", &EN_DIS, + Help "DIMM 1 has to be identical to DIMM 0." + Combo $DIMM_DWidth_0_0, "DIMM_DWidth", &DIMMDWIDTH, + Help "DRAM device data width." + Combo $DIMM_Density_0_0, "DIMM_Density", &DIMMDENSITY, + Help "DRAM device data density." + Combo $DIMM_BusWidth_0_0, "DIMM_BusWidth", &DIMMBUSWIDTH, + Help "DIMM Bus Width." + Combo $DIMM_Sides_0_0, "DIMM_Sides", &RANKPERDIMM, + Help "Ranks Per DIMM. " + EditNum $tCL, "tCL", DEC, + Help "tCL" + EditNum $tRP_tRCD, "tRP_tRCD", DEC, + Help "tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc." + EditNum $tWR, "tWR", DEC, + Help "tWR in DRAM clk" + EditNum $tWTR, "tWTR", DEC, + Help "tWTR in DRAM clk" + EditNum $tRRD, "tRRD", DEC, + Help "tRRD in DRAM clk" + EditNum $tRTP, "tRTP", DEC, + Help "tRTP in DRAM clk" + EditNum $tFAW, "tFAW", DEC, + Help "tFAW in DRAM clk" +EndPage + +Page "South Complex" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataMode, "Select SATA Mode", &SATA_MODE, + Help "Select SATA boot mode. AHCI by default." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS, + Help "Enable/disable XHCI. If enabled, all EHCI ports will be routed to XHCI and EHCI will be disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode, "eMMC Boot Mode", &EMMC_MODES, + Help "Select EMMC Mode." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio, "Enable SDIO", &EN_DIS, + Help "Enable/disable SDIO." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard, "Enable SD Card", &EN_DIS, + Help "Enable/disable the SD Card." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS, + Help "Enable/disable HSUART0." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS, + Help "Enable/disable HSUART1." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi, "Enable SPI", &EN_DIS, + Help "Enable/disable SPI." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan, "Enable LAN", &EN_DIS, + Help "Enable/disable LAN." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS_AUTO, + Help "Enable/disable Azalia. Auto by default." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS, + Help "Enable/disable SATA." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &PCI_ACPI, + Help "Choose LPE Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode, "Enable PCI mode for LPSS SIO devices", &EN_DIS, + Help "Enable PCI Mode for LPSS SIO devices. If disabled, LPSS SIO devices will run in ACPI mode." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS, + Help "Enable/disable DMA0" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS, + Help "Enable/disable DMA1" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS, + Help "Enable/disable I2C0" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS, + Help "Enable/disable I2C1" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS, + Help "Enable/disable I2C2" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS, + Help "Enable/disable I2C3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS, + Help "Enable/disable I2C4" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS, + Help "Enable/disable I2C5" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS, + Help "Enable/disable I2C6" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0, "Enable PWM0", &EN_DIS, + Help "Enable/disable PWM0" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1, "Enable PWM1", &EN_DIS, + Help "Enable/disable PWM1" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi, "Enable HSI", &EN_DIS, + Help "Enable/disable HSI" + Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS, + Help "Enable/disable ISP." +EndPage diff --git a/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_2gb.absf b/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_2gb.absf new file mode 100755 index 0000000..6992fe7 --- /dev/null +++ b/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_2gb.absf @@ -0,0 +1,328 @@ +// +// This file contains an 'Intel Peripheral Driver' and is +// licensed for Intel CPUs and chipsets under the terms of your +// license agreement with Intel or your vendor. This file must not +// be modified by end users or could render the generated boot loader +// inoperable. +// +// @file +// Boot Setting File for Platform: Bayley Bay Platform +// +// Copyright (c) 2010-2013 Intel Corporation. All rights reserved +// This software and associated documentation (if any) is furnished +// under a license and may only be used or copied in accordance +// with the terms of the license. Except as permitted by such +// license, no part of this software or documentation may be +// reproduced, stored in a retrieval system, or transmitted in any +// form or by any means without the express written consent of +// Intel Corporation. +// +// + + +GlobalDataDef + SKUID = 0 $_AS_BUILT_ = 0x01 , "DEFAULT" +EndGlobalData + +StructDef + + Find "VLV2UPDR" + Skip 24 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize 2 bytes $_AS_BUILT_ = 0x1, 0x0 $_DEFAULT_ = 0x0001 + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize 2 bytes $_AS_BUILT_ = 0x0, 0x8 $_DEFAULT_ = 0x0800 + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA0 + $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0xA2 + $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdSataMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_AzaliaConfigPtr 4 bytes $_AS_BUILT_ = 0x0, 0x0, 0x0, 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdGttSize 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_ISPEnable 1 bytes $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + + Find "VLYVIEW1" + $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision 4 bytes $_AS_BUILT_ = 0x2, 0x3, 0x0, 0x0 $_DEFAULT_ = 0x00000302 + Skip 24 bytes + $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 2 + $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 2 + + $DIMM_MemDown 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 + $DRAM_Speed 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 2 + $DRAM_Type 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $Rank_En_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 1 + $Rank_En_1_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $DIMM_DWidth_0_0 1 byte $_AS_BUILT_ = 0x1 $_DEFAULT_ = 0 + $DIMM_Density_0_0 1 byte $_AS_BUILT_ = 0x2 $_DEFAULT_ = 1 + $DIMM_BusWidth_0_0 1 byte $_AS_BUILT_ = 0x3 $_DEFAULT_ = 3 + $DIMM_Sides_0_0 1 byte $_AS_BUILT_ = 0x0 $_DEFAULT_ = 0 + $tCL 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 + $tRP_tRCD 1 byte $_AS_BUILT_ = 0x7 $_DEFAULT_ = 9 + $tWR 1 byte $_AS_BUILT_ = 0x8 $_DEFAULT_ = 10 + $tWTR 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 + $tRRD 1 byte $_AS_BUILT_ = 0x6 $_DEFAULT_ = 4 + $tRTP 1 byte $_AS_BUILT_ = 0x4 $_DEFAULT_ = 5 + $tFAW 1 byte $_AS_BUILT_ = 0x14 $_DEFAULT_ = 20 + +EndStruct + +List &DRAMSPEED + Selection 0x0 , "800 MHz" + Selection 0x1 , "1066 MHz" + Selection 0x2 , "1333 MHz" + Selection 0x3 , "1600 MHz" +EndList + +List &DRAMTYPE + Selection 0x0 , "DDR3" + Selection 0x1 , "DDR3L" + Selection 0x2 , "DDR3U" + //Selection 0x3 , "LPDDR2" + Selection 0x4 , "LPDDR2" + Selection 0x5 , "LPDDR3" + Selection 0x6 , "DDR4" +EndList + +List &DIMMDWIDTH + Selection 0x0 , "x8" + Selection 0x1 , "x16" + Selection 0x2 , "x32" +EndList + +List &DIMMDENSITY + Selection 0x0 , "1 Gbit" + Selection 0x1 , "2 Gbit" + Selection 0x2 , "4 Gbit" + Selection 0x3 , "8 Gbit" +EndList + +List &DIMMBUSWIDTH + Selection 0x0 , "8 bits" + Selection 0x1 , "16 bits" + Selection 0x2 , "32 bits" + Selection 0x3 , "64 bits" +EndList + +List &RANKPERDIMM + Selection 0x1 , "2 Ranks" + Selection 0x0 , "1 Rank" +EndList + +List &SATA_MODE + Selection 0x1 , "AHCI" + Selection 0x0 , "IDE" +EndList + +List &EMMC_MODES + Selection 0x0 , "Disabled" + Selection 0x1 , "Auto" + Selection 0x2 , "eMMC 4.1" + Selection 0x3 , "eMMC 4.5" +EndList + +List &EN_DIS + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &EN_DIS_AUTO + Selection 0x2 , "Auto" + Selection 0x1 , "Enabled" + Selection 0x0 , "Disabled" +EndList + +List &MMIO_SIZES + Selection 0x400, "1.0 GB" + Selection 0x600, "1.5 GB" + Selection 0x800, "2.0 GB" +EndList + +List &TSEG_SIZES + Selection 0x01, "1 MB" + Selection 0x02, "2 MB" + Selection 0x04, "4 MB" + Selection 0x08, "8 MB" +EndList + +List &IGDPREALLOC_SIZES + Selection 0x01, "32 MB" + Selection 0x02, "64 MB" + Selection 0x03, "96 MB" + Selection 0x04, "128 MB" + Selection 0x05, "160 MB" + Selection 0x06, "192 MB" + Selection 0x07, "224 MB" + Selection 0x08, "256 MB" + Selection 0x09, "288 MB" + Selection 0x0A, "320 MB" + Selection 0x0B, "352 MB" + Selection 0x0C, "384 MB" + Selection 0x0D, "416 MB" + Selection 0x0E, "448 MB" + Selection 0x0F, "480 MB" + Selection 0x10, "512 MB" +EndList + +List &APERTURE_SIZES + Selection 0x1 , "128 MB" + Selection 0x2 , "256 MB" + Selection 0x3 , "512 MB" +EndList + +List &GTT_SIZES + Selection 0x1 , "1 MB" + Selection 0x2 , "2 MB" +EndList + +List &PCI_ACPI + Selection 0x2 , "ACPI Mode" + Selection 0x1 , "PCI Mode" + Selection 0x0 , "Disabled" +EndList + +List &PLATFORM_TYPE + Selection 0x2 , "BayleyBay Platform Type" + Selection 0x3 , "BakerSport Platform (ECC) Type" +EndList + +BeginInfoBlock + PPVer "1.0" + Description "MinnowMax" + +EndInfoBlock + +Page "Platform" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdPlatformType, "Platform Type", &PLATFORM_TYPE, + Help "Select Platform Type." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSecureBoot, "Enable Secure Boot", &EN_DIS_AUTO, + Help "Enable/disable secure boot. Auto by default." +EndPage + +Page "North Complex" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize, "Tseg Size", &TSEG_SIZES, + Help "Size of memory reserved for SMRAM, in MB." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitMmioSize, "Mmio Size", &MMIO_SIZES, + Help "Size of memory address space reserved for MMIO (Memory Mapped I/O), in GB." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdIgdDvmt50PreAlloc, "Internal Graphics Pre-allocated Memory ", &IGDPREALLOC_SIZES, + Help "Size of memory preallocated for internal graphics" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdApertureSize, "Aperture Size", &APERTURE_SIZES, + Help "Select the Aperture Size" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdGttSize, "GTT Size", &GTT_SIZES, + Help "Select the GTT Size" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr1, "DIMM 0 SPD SMBus Address", HEX, + Help "Address of DIMM 0. 8 bits" + EditNum $gPlatformFspPkgTokenSpaceGuid_PcdMrcInitSPDAddr2, "DIMM 1 SPD SMBus Address", HEX, + Help "Address of DIMM 1. 8 bits" +EndPage + +Page "Memory Down" + Combo $DIMM_MemDown, "Enable Memory Down", &EN_DIS, + Help "Enable = Memory Down, Disable = DIMM" + Combo $DRAM_Speed, "DRAM Speed", &DRAMSPEED, + Help "DRAM Speed" + Combo $DRAM_Type, "DRAM Type", &DRAMTYPE, + Help "DRAM Type" + Combo $Rank_En_0_0, "DIMM 0 Enable", &EN_DIS, + Help "Please populate DIMM slot 0 if only one DIMM is supported." + Combo $Rank_En_1_0, "DIMM 1 Enable", &EN_DIS, + Help "DIMM 1 has to be identical to DIMM 0." + Combo $DIMM_DWidth_0_0, "DIMM_DWidth", &DIMMDWIDTH, + Help "DRAM device data width." + Combo $DIMM_Density_0_0, "DIMM_Density", &DIMMDENSITY, + Help "DRAM device data density." + Combo $DIMM_BusWidth_0_0, "DIMM_BusWidth", &DIMMBUSWIDTH, + Help "DIMM Bus Width." + Combo $DIMM_Sides_0_0, "DIMM_Sides", &RANKPERDIMM, + Help "Ranks Per DIMM. " + EditNum $tCL, "tCL", DEC, + Help "tCL" + EditNum $tRP_tRCD, "tRP_tRCD", DEC, + Help "tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc." + EditNum $tWR, "tWR", DEC, + Help "tWR in DRAM clk" + EditNum $tWTR, "tWTR", DEC, + Help "tWTR in DRAM clk" + EditNum $tRRD, "tRRD", DEC, + Help "tRRD in DRAM clk" + EditNum $tRTP, "tRTP", DEC, + Help "tRTP in DRAM clk" + EditNum $tFAW, "tFAW", DEC, + Help "tFAW in DRAM clk" +EndPage + +Page "South Complex" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdSataMode, "Select SATA Mode", &SATA_MODE, + Help "Select SATA boot mode. AHCI by default." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableXhci, "Enable XHCI", &EN_DIS, + Help "Enable/disable XHCI. If enabled, all EHCI ports will be routed to XHCI and EHCI will be disabled." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdeMMCBootMode, "eMMC Boot Mode", &EMMC_MODES, + Help "Select EMMC Mode." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdio, "Enable SDIO", &EN_DIS, + Help "Enable/disable SDIO." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSdcard, "Enable SD Card", &EN_DIS, + Help "Enable/disable the SD Card." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart0, "Enable HSUART0", &EN_DIS, + Help "Enable/disable HSUART0." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsuart1, "Enable HSUART1", &EN_DIS, + Help "Enable/disable HSUART1." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSpi, "Enable SPI", &EN_DIS, + Help "Enable/disable SPI." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLan, "Enable LAN", &EN_DIS, + Help "Enable/disable LAN." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableAzalia, "Enable Azalia", &EN_DIS_AUTO, + Help "Enable/disable Azalia. Auto by default." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableSata, "Enable SATA", &EN_DIS, + Help "Enable/disable SATA." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableLpe, "Enable LPE", &PCI_ACPI, + Help "Choose LPE Mode" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdLpssSioEnablePciMode, "Enable PCI mode for LPSS SIO devices", &EN_DIS, + Help "Enable PCI Mode for LPSS SIO devices. If disabled, LPSS SIO devices will run in ACPI mode." + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma0, "Enable DMA0", &EN_DIS, + Help "Enable/disable DMA0" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableDma1, "Enable DMA1", &EN_DIS, + Help "Enable/disable DMA1" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C0, "Enable I2C0", &EN_DIS, + Help "Enable/disable I2C0" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C1, "Enable I2C1", &EN_DIS, + Help "Enable/disable I2C1" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C2, "Enable I2C2", &EN_DIS, + Help "Enable/disable I2C2" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C3, "Enable I2C3", &EN_DIS, + Help "Enable/disable I2C3" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C4, "Enable I2C4", &EN_DIS, + Help "Enable/disable I2C4" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C5, "Enable I2C5", &EN_DIS, + Help "Enable/disable I2C5" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableI2C6, "Enable I2C6", &EN_DIS, + Help "Enable/disable I2C6" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm0, "Enable PWM0", &EN_DIS, + Help "Enable/disable PWM0" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnablePwm1, "Enable PWM1", &EN_DIS, + Help "Enable/disable PWM1" + Combo $gPlatformFspPkgTokenSpaceGuid_PcdEnableHsi, "Enable HSI", &EN_DIS, + Help "Enable/disable HSI" + Combo $gPlatformFspPkgTokenSpaceGuid_ISPEnable, "Enable ISP", &EN_DIS, + Help "Enable/disable ISP." +EndPage

1 0

Patch set updated for coreboot: 283f225 mainboard/intel/minnowmax: Add MinnowMax mainboard
by Martin Roth 01 Aug '14

01 Aug '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6429 -gerrit commit 283f225af06d1560674b99c095ab4bff8876090d Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 28 14:22:32 2014 -0600 mainboard/intel/minnowmax: Add MinnowMax mainboard MinnowMax board using Intel's Bay Trail FSP Working: - Booting from SATA / USB / (USB3 with latest SeaBIOS) Not working: - Boot from SD - S3 Suspend / Resume ***** To configure the FSP ***** Download the Bay Trail FSP and the binary config tool: Modify the standard Bay Trail FSP: run the bct tool with the command line options: bct --bin <Bay Trail FSP Binary> \ --absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \ --bout <path to save the updated FSP to> Here are the required changes for modifying the FSP manually: Enable Memory Down: Enabled DRAM Speed: 1066 MHz DIMM_DWidth: x16 DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max) tCL: 7 tRP_tRCD: 7 tWR: 8 tRRD: 6 tRTP: 4 tFAW: 27 Other FSP values can remain the same. ***** To configure the vbios ***** The vbios is in the Bay Trail FSP package. Download Intel's "Binary Modification Program" (BMP) Use it to disable all ports except HDMI on port B. Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/minnowmax/Kconfig | 127 ++++++++++ src/mainboard/intel/minnowmax/Makefile.inc | 21 ++ src/mainboard/intel/minnowmax/acpi/ec.asl | 0 src/mainboard/intel/minnowmax/acpi/mainboard.asl | 25 ++ src/mainboard/intel/minnowmax/acpi/superio.asl | 0 src/mainboard/intel/minnowmax/acpi/video.asl | 0 src/mainboard/intel/minnowmax/acpi_tables.c | 282 +++++++++++++++++++++++ src/mainboard/intel/minnowmax/cmos.layout | 139 +++++++++++ src/mainboard/intel/minnowmax/devicetree.cb | 80 +++++++ src/mainboard/intel/minnowmax/dsdt.asl | 57 +++++ src/mainboard/intel/minnowmax/fadt.c | 36 +++ src/mainboard/intel/minnowmax/gpio.c | 235 +++++++++++++++++++ src/mainboard/intel/minnowmax/irqroute.c | 22 ++ src/mainboard/intel/minnowmax/irqroute.h | 78 +++++++ src/mainboard/intel/minnowmax/mainboard.c | 57 +++++ src/mainboard/intel/minnowmax/romstage.c | 82 +++++++ 17 files changed, 1244 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4f1ff4c..9dd8a5e 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -17,6 +17,8 @@ config BOARD_INTEL_EMERALDLAKE2 bool "Emerald Lake 2 CRB" config BOARD_INTEL_JARRELL bool "Jarrell (SE7520JR2)" +config BOARD_INTEL_MINNOWMAX + bool "Minnow Max" config BOARD_INTEL_MOHONPEAK bool "Mohon Peak CRB" config BOARD_INTEL_MTARVON @@ -40,6 +42,7 @@ source "src/mainboard/intel/eagleheights/Kconfig" source "src/mainboard/intel/emeraldlake2/Kconfig" source "src/mainboard/intel/baskingridge/Kconfig" source "src/mainboard/intel/jarrell/Kconfig" +source "src/mainboard/intel/minnowmax/Kconfig" source "src/mainboard/intel/mohonpeak/Kconfig" source "src/mainboard/intel/mtarvon/Kconfig" source "src/mainboard/intel/truxton/Kconfig" diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig new file mode 100644 index 0000000..0e83d5a --- /dev/null +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -0,0 +1,127 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_INTEL_MINNOWMAX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select OVERRIDE_MRC_CACHE_LOC + select TSC_MONOTONIC_TIMER + +config MAINBOARD_DIR + string + default "intel/minnowmax" + +config INCLUDE_ME + bool + default n + +config LOCK_MANAGEMENT_ENGINE + bool + default n + +config MAINBOARD_PART_NUMBER + string + default "Minnow Max 2GB" if MINNOWMAX_2GB_SKU + default "Minnow Max 1GB" + +choice + prompt "Memory SKU to build" + default MINNOWMAX_1GB_SKU + +config MINNOWMAX_1GB_SKU + bool "1GB" + +config MINNOWMAX_2GB_SKU + bool "2GB" +endchoice + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_LOC + hex + default 0xfffc0000 + +config FSP_FILE + string + default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_2gb.bin" if MINNOWMAX_2GB_SKU + default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_1gb.bin" + +config MRC_CACHE_LOC_OVERRIDE + hex + default 0xfff90000 + depends on ENABLE_FSP_FAST_BOOT + +config CBFS_SIZE + hex + default 0x00300000 + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config CONSOLE_POST + bool + default y + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config POST_IO + bool + default n + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default n + +config VGA_BIOS_FILE + string + default "../intel/mainboard/intel/minnowmax/Vga.dat" if VGA_BIOS + +endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc new file mode 100644 index 0000000..2f7a8c5 --- /dev/null +++ b/src/mainboard/intel/minnowmax/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-y += gpio.c +ramstage-y += irqroute.c diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 0000000..c1884c5 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/minnowmax/acpi/video.asl b/src/mainboard/intel/minnowmax/acpi/video.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c new file mode 100644 index 0000000..881c143 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> // hexdump +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> +#include <baytrail/iomap.h> + + +extern const unsigned char AmlCode[]; + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* No TPM Present */ + gnvs->tpmp = 0; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, + facs->length); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + ALIGN_CURRENT; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, + dsdt->length); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, + fadt->header.length); + + /* + * We explicitly add these tables later on: + */ + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, + hpet->header.length); + + /* If we want to use HPET Timers Linux wants an MADT */ + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, + madt->header.length); + + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, + mcfg->header.length); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ +#if CONFIG_HAVE_SMI_HANDLER + smm_setup_structures(gnvs, NULL, NULL); +#endif + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + ssdt = (acpi_header_t *)current; + memset(ssdt, 0, sizeof(acpi_header_t)); + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, + ssdt->length); + ALIGN_CURRENT; + } else { + ssdt = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); + } + + ssdt2 = (acpi_header_t *)current; + memset(ssdt2, 0, sizeof(acpi_header_t)); + acpi_create_serialio_ssdt(ssdt2); + if (ssdt2->length) { + current += ssdt2->length; + acpi_add_table(rsdp, ssdt2); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, + ssdt2->length); + ALIGN_CURRENT; + } else { + ssdt2 = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); + } + + printk(BIOS_DEBUG, "current = %lx\n", current); + +#if IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) + printk(BIOS_DEBUG, "rsdp\n"); + hexdump(BIOS_DEBUG, rsdp, sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + hexdump(BIOS_DEBUG, rsdt, sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "hpet\n"); + hexdump(BIOS_DEBUG, hpet, hpet->header.length); + + printk(BIOS_DEBUG, "madt\n"); + hexdump(BIOS_DEBUG, madt, madt->header.length); + + printk(BIOS_DEBUG, "mcfg\n"); + hexdump(BIOS_DEBUG, mcfg, mcfg->header.length); + + printk(BIOS_DEBUG, "dsdt\n"); + hexdump(BIOS_DEBUG, dsdt, dsdt->length); + + if (ssdt != NULL) { + printk(BIOS_DEBUG, "ssdt\n"); + hexdump(BIOS_DEBUG, ssdt, ssdt->length); + } + + if (ssdt2 != NULL) { + printk(BIOS_DEBUG, "ssdt2\n"); + hexdump(BIOS_DEBUG, ssdt2, ssdt2->length); + } + + printk(BIOS_DEBUG, "fadt\n"); + hexdump(BIOS_DEBUG, fadt, fadt->header.length); + + printk(BIOS_DEBUG, "facs\n"); + hexdump(BIOS_DEBUG, facs, facs->length); + +#endif /* IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) */ + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout new file mode 100644 index 0000000..a668188 --- /dev/null +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1719 64 h 0 timestamp_value1 +1783 64 h 0 timestamp_value2 +1847 64 h 0 timestamp_value3 +1911 64 h 0 timestamp_value4 +1975 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb new file mode 100644 index 0000000..4e3833e --- /dev/null +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -0,0 +1,80 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/intel/fsp_baytrail + + #### ACPI Register Settings #### + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + #### FSP register settings #### + register "SataMode" = "SATA_MODE_AHCI" + register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "ApertureSize" = "APERTURE_SIZE_DEFAULT" + register "GttSize" = "GTT_SIZE_DEFAULT" + register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router - + device pci 02.0 on end # 8086 0F31 - GFX micro HDMI + device pci 03.0 off end # 8086 0F38 - MIPI - + + device pci 10.0 off end # 8086 0F14 - EMMC Port - + device pci 11.0 off end # 8086 0F15 - SDIO Port - + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI Onboard & HSEC + device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC + device pci 17.0 off end # 8086 0F50 - MMC Port - + device pci 18.0 on end # 8086 0F40 - SIO - DMA - + device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) - + device pci 18.2 off end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) - + device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) - + device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) - + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC + device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC + device pci 1a.0 on end # 8086 0F18 - TXE - + device pci 1b.0 off end # 8086 0F04 - HD Audio - + device pci 1c.0 off end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC + device pci 1d.0 off end # 8086 0F34 - USB EHCI - + device pci 1e.0 on end # 8086 0F06 - SIO - DMA - + device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC + device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC + device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC + device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC + device pci 1e.5 on end # 8086 0F0E - SPI LSEC + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000..cb2a4da --- /dev/null +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/minnowmax/fadt.c b/src/mainboard/intel/minnowmax/fadt.c new file mode 100644 index 0000000..91995f0 --- /dev/null +++ b/src/mainboard/intel/minnowmax/fadt.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <baytrail/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt,facs,dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c new file mode 100644 index 0000000..9b735cf --- /dev/null +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ + GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ + GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ + GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ + GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ + GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ + GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ + GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ + GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ + GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ + GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ + GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ + GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ + GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ + GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ + GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ + GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ + GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ + GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ + GPIO_FUNC1, /* GPIO_S0_SC[040] - TP12 (SD3_1P8EN) */ + GPIO_FUNC1, /* GPIO_S0_SC[041] - TP11 (/SD3_PWREN) */ + GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ + GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) */ + GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ + GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) */ + GPIO_FUNC0, /* GPIO_S0_SC[059] - HDMI_DCDC_ENB */ + GPIO_FUNC0, /* GPIO_S0_SC[060] - HDMI_LDSW_ENB */ + GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ + GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ + GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ + GPIO_FUNC1, /* GPIO_S0_SC[072] - SIO_UART1_RTSB */ + GPIO_FUNC1, /* GPIO_S0_SC[073] - SIO_UART1_CTSB */ + GPIO_FUNC1, /* GPIO_S0_SC[074] - SIO_UART2_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[075] - SIO_UART2_TXD */ + GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) */ + GPIO_FUNC1, /* GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) */ + GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[088] - LSS_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[089] - LSS_I2C_SCL */ + GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ + GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[092] - TP13 */ + GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[093] - TP16 */ + GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ + GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ + GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[00] - SOC_GPIO_S5_0 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[01] - SOC_GPIO_S5_1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */ + GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */ + GPIO_NC, /* GPIO_S5[04] - No Connect */ + GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 */ + GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ + GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ + GPIO_OUT_HIGH, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ + GPIO_OUT_HIGH, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ + GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ + GPIO_FUNC0, /* GPIO_S5[12] - PMC_SUSCLK0 */ + GPIO_FUNC1, /* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */ + GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ + GPIO_FUNC0, /* GPIO_S5[15] - PMC_PCIE_WAKE_R */ + GPIO_FUNC0, /* GPIO_S5[16] - PMC_PWRBTN */ + GPIO_NC1, /* GPIO_S5[17] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[18] - LPCPD_L (TP7) */ + GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ + GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ + GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ + GPIO_NC, /* GPIO_S5[22] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[23] - XDP_H_OBSDATA_A0 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[24] - XDP_H_OBSDATA_A1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[25] - XDP_H_OBSDATA_A2 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[26] - XDP_H_OBSDATA_A3 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[27] - EXP_GPIO1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[28] - EXP_GPIO2 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[29] - EXP_GPIO3 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[30] - EXP_GPIO4 */ + GPIO_NC, /* GPIO_S5[31] - No Connect */ + GPIO_NC, /* GPIO_S5[32] - No Connect */ + GPIO_NC, /* GPIO_S5[33] - No Connect */ + GPIO_NC, /* GPIO_S5[34] - No Connect */ + GPIO_NC, /* GPIO_S5[35] - No Connect */ + GPIO_NC, /* GPIO_S5[36] - No Connect */ + GPIO_NC, /* GPIO_S5[37] - No Connect */ + GPIO_NC, /* GPIO_S5[38] - No Connect */ + GPIO_NC, /* GPIO_S5[39] - No Connect */ + GPIO_NC, /* GPIO_S5[40] - No Connect */ + GPIO_NC, /* GPIO_S5[41] - No Connect */ + GPIO_NC, /* GPIO_S5[42] - No Connect */ + GPIO_NC, /* GPIO_S5[43] - No Connect */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c new file mode 100644 index 0000000..552be8f --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h new file mode 100644 index 0000000..99c3776 --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 4), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c new file mode 100644 index 0000000..21767e2 --- /dev/null +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ +// printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " enable.\n"); + + +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +// printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); + + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c new file mode 100644 index 0000000..575e646 --- /dev/null +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <stddef.h> +#include <arch/cpu.h> +#include <lib.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <romstage_handoff.h> +#include <timestamp.h> +#include <baytrail/gpio.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/romstage.h> +#include <baytrail/acpi.h> +#include <baytrail/baytrail.h> +#include <drivers/intel/fsp/fsp_util.h> + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry() +{ + +} + +/** + * Get function disables - most of these will be done automatically + * @param fd_mask + * @param fd2_mask + */ +void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +{ + +} + + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ + +void late_mainboard_romstage_entry() +{ + +} + + +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + + /* Disable 2nd DIMM */ + UpdData->PcdMrcInitSPDAddr2 = 0x00; + + return; +}

1 0

Patch merged into coreboot/master: aaaef06 fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1
by gerrit＠coreboot.org 01 Aug '14

01 Aug '14

the following patch was just integrated into master: commit aaaef061792f7904d75f401e1de376311d6cdd0b Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 28 14:20:58 2014 -0600 fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1 The GPIO_NC setting sets up the gpio as a no-connect - sets it as an input, and pulls it high. It makes an assumption that the GPIO function is muxing function 0. There are a few GPIOs that are on function 1 instead: * GPIO_S0_SC[092-93] * GPIO_S5[11-21] For these GPIOs, use the GPIO_NC1 setting instead of GPIO_NC. Change-Id: Iac6790b40e87ad4ac9a3b265a8e10662186c1201 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6428 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6428 for details. -gerrit

1 0

New patch to review for coreboot: a6db77a tegra124: Add a stub implementation of the tegra124 SOC.
by Isaac Christensen 31 Jul '14

31 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6431 -gerrit commit a6db77a21bc340ac4cb682f71fb2c25a904a1825 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Sep 26 16:22:09 2013 -0700 tegra124: Add a stub implementation of the tegra124 SOC. Most things still needs to be filled in, but this will allow us to build boards which use this SOC. Change-Id: Ic790685a78193ccb223f4d9355bd3db57812af39 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170836 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 462456fd00164c10c80eff72240226a04445fe60) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/Kconfig | 1 + src/soc/Makefile.inc | 1 + src/soc/nvidia/Kconfig | 1 + src/soc/nvidia/Makefile.inc | 1 + src/soc/nvidia/tegra124/Kconfig | 42 ++++++++++++++++++++++++ src/soc/nvidia/tegra124/Makefile.inc | 9 ++++++ src/soc/nvidia/tegra124/bootblock.c | 23 ++++++++++++++ src/soc/nvidia/tegra124/cbfs.c | 26 +++++++++++++++ src/soc/nvidia/tegra124/monotonic_timer.c | 24 ++++++++++++++ src/soc/nvidia/tegra124/timer.c | 53 +++++++++++++++++++++++++++++++ 10 files changed, 181 insertions(+) diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 823d76c..152e206 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1 +1,2 @@ source src/soc/intel/Kconfig +source src/soc/nvidia/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index fdf9db0..d419309 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -2,3 +2,4 @@ ## Subdirectories ################################################################################ subdirs-y += intel +subdirs-y += nvidia diff --git a/src/soc/nvidia/Kconfig b/src/soc/nvidia/Kconfig new file mode 100644 index 0000000..836edeb --- /dev/null +++ b/src/soc/nvidia/Kconfig @@ -0,0 +1 @@ +source src/soc/nvidia/tegra124/Kconfig diff --git a/src/soc/nvidia/Makefile.inc b/src/soc/nvidia/Makefile.inc new file mode 100644 index 0000000..34feb0a --- /dev/null +++ b/src/soc/nvidia/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124 diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig new file mode 100644 index 0000000..5d8fd4c --- /dev/null +++ b/src/soc/nvidia/tegra124/Kconfig @@ -0,0 +1,42 @@ +config SOC_NVIDIA_TEGRA124 + depends on ARCH_ARMV7 + bool + default n + +if SOC_NVIDIA_TEGRA124 + +config BOOTBLOCK_CPU_INIT + string + default "soc/nvidia/tegra124/bootblock.c" + help + CPU/SoC-specific bootblock code. This is useful if the + bootblock must load microcode or copy data from ROM before + searching for the bootblock. + +# ROM image layout. +# +# 0x00000 Combined bootblock and BCT blob +# 0x18000 Master CBFS header. +# 0x18080 Free for CBFS data. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +config SYS_SDRAM_BASE + hex + default 0x80000000 + +config BOOTBLOCK_BASE + hex + default 0x80000000 + +endif diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc new file mode 100644 index 0000000..49e2b1f --- /dev/null +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -0,0 +1,9 @@ +bootblock-y += cbfs.c + +romstage-y += cbfs.c +romstage-y += monotonic_timer.c +romstage-y += timer.c + +ramstage-y += cbfs.c +ramstage-y += monotonic_timer.c +ramstage-y += timer.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c new file mode 100644 index 0000000..a8d6990 --- /dev/null +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ +} diff --git a/src/soc/nvidia/tegra124/cbfs.c b/src/soc/nvidia/tegra124/cbfs.c new file mode 100644 index 0000000..ede9146 --- /dev/null +++ b/src/soc/nvidia/tegra124/cbfs.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbfs.h> /* This driver serves as a CBFS media source. */ + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return -1; +} diff --git a/src/soc/nvidia/tegra124/monotonic_timer.c b/src/soc/nvidia/tegra124/monotonic_timer.c new file mode 100644 index 0000000..3423dde --- /dev/null +++ b/src/soc/nvidia/tegra124/monotonic_timer.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <timer.h> + +void timer_monotonic_get(struct mono_time *mt) +{ +} diff --git a/src/soc/nvidia/tegra124/timer.c b/src/soc/nvidia/tegra124/timer.c new file mode 100644 index 0000000..83f499c --- /dev/null +++ b/src/soc/nvidia/tegra124/timer.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void init_timer(void) +{ +} + +/* delay x useconds */ +void udelay(unsigned usec) +{ + struct mono_time current, end; + + if (!thread_yield_microseconds(usec)) + return; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, usec); + + if (mono_time_after(&current, &end)) { + printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n", + usec); + /* There's not much we can do if usec is too big. Use a long, + * paranoid delay value and hope for the best... */ + end = current; + mono_time_add_usecs(&end, USECS_PER_SEC); + } + + while (mono_time_before(&current, &end)) + timer_monotonic_get(&current); +} +

1 0

New patch to review for coreboot: 4046b2e bayleybay: add initial Bayley Bay board support
by Isaac Christensen 31 Jul '14

31 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6430 -gerrit commit 4046b2e8853cf7dd27fab2949340a2a567b8a458 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 7 00:45:37 2013 -0500 bayleybay: add initial Bayley Bay board support The Bayley Bay reference board is a Bay Trail mobile and/or desktop reference board. Change-Id: Ia0a4f94244ce7ac3a960de796170c091e384f976 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168388 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit d177555133010d6a8b135e5dbfe5ed2ff98e362e) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/bayleybay/Kconfig | 27 +++ src/mainboard/intel/bayleybay/Makefile.inc | 23 ++ src/mainboard/intel/bayleybay/acpi/chromeos.asl | 24 ++ src/mainboard/intel/bayleybay/acpi/ec.asl | 37 +++ src/mainboard/intel/bayleybay/acpi/mainboard.asl | 28 +++ src/mainboard/intel/bayleybay/acpi/platform.asl | 73 ++++++ src/mainboard/intel/bayleybay/acpi/superio.asl | 20 ++ src/mainboard/intel/bayleybay/acpi/thermal.asl | 246 +++++++++++++++++++ src/mainboard/intel/bayleybay/acpi/video.asl | 43 ++++ src/mainboard/intel/bayleybay/acpi_tables.c | 287 +++++++++++++++++++++++ src/mainboard/intel/bayleybay/chromeos.c | 79 +++++++ src/mainboard/intel/bayleybay/cmos.layout | 139 +++++++++++ src/mainboard/intel/bayleybay/devicetree.cb | 8 + src/mainboard/intel/bayleybay/dsdt.asl | 55 +++++ src/mainboard/intel/bayleybay/fadt.c | 156 ++++++++++++ src/mainboard/intel/bayleybay/graphics.c | 89 +++++++ src/mainboard/intel/bayleybay/mainboard.c | 143 +++++++++++ src/mainboard/intel/bayleybay/mainboard_smi.c | 63 +++++ src/mainboard/intel/bayleybay/romstage.c | 39 +++ src/mainboard/intel/bayleybay/thermal.h | 57 +++++ 21 files changed, 1639 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4f1ff4c..9bff2e9 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -29,6 +29,8 @@ config BOARD_INTEL_BASKING_RIDGE bool "Basking Ridge CRB" config BOARD_INTEL_WTM2 bool "Whitetip Mountain 2 CRB" +config BOARD_INTEL_BAYLEYBAY + bool "Bayley Bay CRB" endchoice @@ -45,6 +47,7 @@ source "src/mainboard/intel/mtarvon/Kconfig" source "src/mainboard/intel/truxton/Kconfig" source "src/mainboard/intel/xe7501devkit/Kconfig" source "src/mainboard/intel/wtm2/Kconfig" +source "src/mainboard/intel/bayleybay/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/intel/bayleybay/Kconfig b/src/mainboard/intel/bayleybay/Kconfig new file mode 100644 index 0000000..cee2bd8 --- /dev/null +++ b/src/mainboard/intel/bayleybay/Kconfig @@ -0,0 +1,27 @@ +if BOARD_INTEL_BAYLEYBAY + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select SOC_INTEL_BAYTRAIL + select ENABLE_BUILTIN_COM1 + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select CHROMEOS + select MARK_GRAPHICS_MEM_WRCOMB + +config MAINBOARD_DIR + string + default intel/bayleybay + +config MAINBOARD_PART_NUMBER + string + default "BAYLEY BAY" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/intel/bayleybay/Makefile.inc b/src/mainboard/intel/bayleybay/Makefile.inc new file mode 100644 index 0000000..f393388 --- /dev/null +++ b/src/mainboard/intel/bayleybay/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/bayleybay/acpi/chromeos.asl b/src/mainboard/intel/bayleybay/acpi/chromeos.asl new file mode 100644 index 0000000..40ffcf0 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/chromeos.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery + Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer + Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect +}) diff --git a/src/mainboard/intel/bayleybay/acpi/ec.asl b/src/mainboard/intel/bayleybay/acpi/ec.asl new file mode 100644 index 0000000..9ae5951 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/ec.asl @@ -0,0 +1,37 @@ +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x03), + ACPR, 1, // AC Power (1=present) + , 2, + CFAN, 1, // CPU Fan (1=on) + , 2, + LIDS, 1, // Lid State (1=open) + , 1, + SPTR, 8, // SMBUS Protocol Register + SSTS, 8, // SMBUS Status Register + SADR, 8, // SMBUS Address Register + SCMD, 8, // SMBUS Command Register + SBFR, 256, // SMBUS Block Buffer + SCNT, 8, // SMBUS Block Count + + Offset (0x3a), + ECMD, 8, // EC Command Register + + Offset (0x82), + PECL, 8, // PECI fractional (1/64 Celsius) + PECH, 8, // PECI integer (Celsius) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) +} diff --git a/src/mainboard/intel/bayleybay/acpi/mainboard.asl b/src/mainboard/intel/bayleybay/acpi/mainboard.asl new file mode 100644 index 0000000..3e0eb33 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake from deep sleep via GPIO27 + Name(_PRW, Package(){27, 4}) +} diff --git a/src/mainboard/intel/bayleybay/acpi/platform.asl b/src/mainboard/intel/bayleybay/acpi/platform.asl new file mode 100644 index 0000000..e069392 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/intel/bayleybay/acpi/superio.asl b/src/mainboard/intel/bayleybay/acpi/superio.asl new file mode 100644 index 0000000..9092a6c --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/intel/bayleybay/acpi/thermal.asl b/src/mainboard/intel/bayleybay/acpi/thermal.asl new file mode 100644 index 0000000..00a8750 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/thermal.asl @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 0 seconds + Name (_TZP, 0) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + Return (CTOK (30)) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (\F2OF)) + } Else { + Return (CTOK (\F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (\F3OF)) + } Else { + Return (CTOK (\F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (\F4OF)) + } Else { + Return (CTOK (\F4ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/intel/bayleybay/acpi/video.asl b/src/mainboard/intel/bayleybay/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/intel/bayleybay/acpi_tables.c b/src/mainboard/intel/bayleybay/acpi_tables.c new file mode 100644 index 0000000..3723021 --- /dev/null +++ b/src/mainboard/intel/bayleybay/acpi_tables.c @@ -0,0 +1,287 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> + +extern const unsigned char AmlCode[]; + +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->f4of = FAN4_THRESHOLD_OFF; + gnvs->f4on = FAN4_THRESHOLD_ON; + gnvs->f4pw = FAN4_PWM; + + gnvs->f3of = FAN3_THRESHOLD_OFF; + gnvs->f3on = FAN3_THRESHOLD_ON; + gnvs->f3pw = FAN3_PWM; + + gnvs->f2of = FAN2_THRESHOLD_OFF; + gnvs->f2on = FAN2_THRESHOLD_ON; + gnvs->f2pw = FAN2_PWM; + + gnvs->f1of = FAN1_THRESHOLD_OFF; + gnvs->f1on = FAN1_THRESHOLD_ON; + gnvs->f1pw = FAN1_PWM; + + gnvs->f0of = FAN0_THRESHOLD_OFF; + gnvs->f0on = FAN0_THRESHOLD_ON; + gnvs->f0pw = FAN0_PWM; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + /* Emerald Lake has no EC (?) */ + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); + ssdt = (acpi_header_t *)current; + acpi_create_serialio_ssdt(ssdt); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/bayleybay/chromeos.c b/src/mainboard/intel/bayleybay/chromeos.c new file mode 100644 index 0000000..2681b3a --- /dev/null +++ b/src/mainboard/intel/bayleybay/chromeos.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +/* Compile-time settings for developer and recovery mode. */ +#define DEV_MODE_SETTING 1 +#define REC_MODE_SETTING 0 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static void fill_lb_gpio(struct lb_gpio *gpio, int polarity, + const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = -1; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "recovery", REC_MODE_SETTING); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "developer", DEV_MODE_SETTING); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "lid", 1); // force open + fill_lb_gpio(gpio++, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif + +int get_developer_mode_switch(void) +{ + return DEV_MODE_SETTING; +} + +int get_recovery_mode_switch(void) +{ + return REC_MODE_SETTING; +} + +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/intel/bayleybay/cmos.layout b/src/mainboard/intel/bayleybay/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/intel/bayleybay/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/bayleybay/devicetree.cb b/src/mainboard/intel/bayleybay/devicetree.cb new file mode 100644 index 0000000..376aab6 --- /dev/null +++ b/src/mainboard/intel/bayleybay/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/baytrail + device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 1f.0 on end # LPC Bridge + end +end diff --git a/src/mainboard/intel/bayleybay/dsdt.asl b/src/mainboard/intel/bayleybay/dsdt.asl new file mode 100644 index 0000000..172aaf4 --- /dev/null +++ b/src/mainboard/intel/bayleybay/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + //#include "acpi/thermal.asl" + + //#include <soc/intel/baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/baytrail/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/bayleybay/fadt.c b/src/mainboard/intel/bayleybay/fadt.c new file mode 100644 index 0000000..9c8bd60 --- /dev/null +++ b/src/mainboard/intel/bayleybay/fadt.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + /* FIXME: hard coded address. */ + u16 pmbase = 0x400; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/bayleybay/graphics.c b/src/mainboard/intel/bayleybay/graphics.c new file mode 100644 index 0000000..6d375e6 --- /dev/null +++ b/src/mainboard/intel/bayleybay/graphics.c @@ -0,0 +1,89 @@ +/* +* This file is part of the coreboot project. +* +* Copyright 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +/* this file was for the most part machine generated, and in future + * will be all machine generated. Avoid editing. + */ +#include <console/console.h> +#include <device/i915.h> + +void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose) +{ + + io_i915_write32(0x80000000,0x45400); + io_i915_write32(0x00000000,_CURACNTR); + io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR); + io_i915_write32(0x00000000,_DSPBCNTR); + io_i915_write32(0x80000000,CPU_VGACNTRL); + io_i915_write32(0x00000000,_DSPASIZE+0xc); + io_i915_write32(0x00000000,_DSPBSURF); + io_i915_write32(0x00000000,0x4f050); + io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | + DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | + DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | + DP_SYNC_VS_HIGH |0x00000091,DP_A); + io_i915_write32(0x00200090,_FDI_RXA_MISC); + io_i915_write32(0x0a000000,_FDI_RXA_MISC); + /* not yet documented anywhere that we can find. */ + io_i915_write32(0x00000070,0x46408); + io_i915_write32(0x04000000,0x42090); + io_i915_write32(0x40000000,0x4f050); + io_i915_write32(0x00000000,0x9840); + io_i915_write32(0xa4000000,0x42090); + io_i915_write32(0x00004000,0x42080); + io_i915_write32(0x00ffffff,0x64f80); + io_i915_write32(0x0007000e,0x64f84); + io_i915_write32(0x00d75fff,0x64f88); + io_i915_write32(0x000f000a,0x64f8c); + io_i915_write32(0x00c30fff,0x64f90); + io_i915_write32(0x00060006,0x64f94); + io_i915_write32(0x00aaafff,0x64f98); + io_i915_write32(0x001e0000,0x64f9c); + io_i915_write32(0x00ffffff,0x64fa0); + io_i915_write32(0x000f000a,0x64fa4); + io_i915_write32(0x00d75fff,0x64fa8); + io_i915_write32(0x00160004,0x64fac); + io_i915_write32(0x00c30fff,0x64fb0); + io_i915_write32(0x001e0000,0x64fb4); + io_i915_write32(0x00ffffff,0x64fb8); + io_i915_write32(0x00060006,0x64fbc); + io_i915_write32(0x00d75fff,0x64fc0); + io_i915_write32(0x001e0000,0x64fc4); + io_i915_write32(0x00ffffff,0x64e00); + io_i915_write32(0x0006000e,0x64e04); + io_i915_write32(0x00d75fff,0x64e08); + io_i915_write32(0x0005000a,0x64e0c); + io_i915_write32(0x00c30fff,0x64e10); + io_i915_write32(0x00040006,0x64e14); + io_i915_write32(0x80aaafff,0x64e18); + io_i915_write32(0x000b0000,0x64e1c); + io_i915_write32(0x00ffffff,0x64e20); + io_i915_write32(0x0005000a,0x64e24); + io_i915_write32(0x00d75fff,0x64e28); + io_i915_write32(0x000c0004,0x64e2c); + io_i915_write32(0x80c30fff,0x64e30); + io_i915_write32(0x000b0000,0x64e34); + io_i915_write32(0x00ffffff,0x64e38); + io_i915_write32(0x00040006,0x64e3c); + io_i915_write32(0x80d75fff,0x64e40); + io_i915_write32(0x000b0000,0x64e44); + /* end not yet documented. */ + io_i915_write32(0x10000000,SDEISR+0x30); +} + + diff --git a/src/mainboard/intel/bayleybay/mainboard.c b/src/mainboard/intel/bayleybay/mainboard.c new file mode 100644 index 0000000..0092034 --- /dev/null +++ b/src/mainboard/intel/bayleybay/mainboard.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/intel/bayleybay/mainboard_smi.c b/src/mainboard/intel/bayleybay/mainboard_smi.c new file mode 100644 index 0000000..0571baf --- /dev/null +++ b/src/mainboard/intel/bayleybay/mainboard_smi.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <baytrail/nvs.h> + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#define APMC_FINALIZE 0xcb + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + mainboard_finalized = 1; + break; + } + return 0; +} diff --git a/src/mainboard/intel/bayleybay/romstage.c b/src/mainboard/intel/bayleybay/romstage.c new file mode 100644 index 0000000..318fa1d --- /dev/null +++ b/src/mainboard/intel/bayleybay/romstage.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <baytrail/mrc_wrapper.h> +#include <baytrail/romstage.h> + +void mainboard_romstage_entry(unsigned long bist) +{ + struct mrc_params mp = { + .mainboard = { + .dram_type = DRAM_DDR3L, + .dram_info_location = DRAM_INFO_SPD_SMBUS, + .spd_addrs = { 0xa0, 0xa2 }, + }, + }; + struct romstage_params rp = { + .mrc_params = &mp, + }; + romstage_common(&rp); +} diff --git a/src/mainboard/intel/bayleybay/thermal.h b/src/mainboard/intel/bayleybay/thermal.h new file mode 100644 index 0000000..f771014 --- /dev/null +++ b/src/mainboard/intel/bayleybay/thermal.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYLEYBAY_THERMAL_H +#define BAYLEYBAY_THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 48 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x40 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 52 +#define FAN2_THRESHOLD_ON 64 +#define FAN2_PWM 0x80 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 60 +#define FAN1_THRESHOLD_ON 68 +#define FAN1_PWM 0xb0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 66 +#define FAN0_THRESHOLD_ON 78 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif

1 0

New patch to review for coreboot: 8028c8b mainboard/intel/minnowmax: Add MinnowMax mainboard
by Martin Roth 31 Jul '14

31 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6429 -gerrit commit 8028c8bd5d8b881864c9773c2bdd1b5584723d8a Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 28 14:22:32 2014 -0600 mainboard/intel/minnowmax: Add MinnowMax mainboard MinnowMax board using Intel's Bay Trail FSP Working: - Booting from SATA / USB / (USB3 with latest SeaBIOS) Not working: - Boot from SD - S3 Suspend / Resume ***** To configure the FSP ***** Download the Bay Trail FSP and the binary config tool: Modify the standard Bay Trail FSP: Enable Memory Down: Enabled DRAM Speed: 1066 MHz DIMM_DWidth: x16 DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max) tCL: 7 tRP_tRCD: 7 tWR: 8 tRRD: 6 tRTP: 4 tFAW: 27 Other FSP values can remain the same. ***** To configure the vbios ***** The vbios is in the Bay Trail FSP package. Download Intel's "Binary Modification Program" (BMP) Use it to disable all ports except HDMI on port B. Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/minnowmax/Kconfig | 127 ++++++++++ src/mainboard/intel/minnowmax/Makefile.inc | 21 ++ src/mainboard/intel/minnowmax/acpi/ec.asl | 0 src/mainboard/intel/minnowmax/acpi/mainboard.asl | 25 ++ src/mainboard/intel/minnowmax/acpi/superio.asl | 0 src/mainboard/intel/minnowmax/acpi/video.asl | 0 src/mainboard/intel/minnowmax/acpi_tables.c | 282 +++++++++++++++++++++++ src/mainboard/intel/minnowmax/cmos.layout | 139 +++++++++++ src/mainboard/intel/minnowmax/devicetree.cb | 80 +++++++ src/mainboard/intel/minnowmax/dsdt.asl | 57 +++++ src/mainboard/intel/minnowmax/fadt.c | 36 +++ src/mainboard/intel/minnowmax/gpio.c | 235 +++++++++++++++++++ src/mainboard/intel/minnowmax/irqroute.c | 22 ++ src/mainboard/intel/minnowmax/irqroute.h | 73 ++++++ src/mainboard/intel/minnowmax/mainboard.c | 57 +++++ src/mainboard/intel/minnowmax/romstage.c | 82 +++++++ 17 files changed, 1239 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4f1ff4c..9dd8a5e 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -17,6 +17,8 @@ config BOARD_INTEL_EMERALDLAKE2 bool "Emerald Lake 2 CRB" config BOARD_INTEL_JARRELL bool "Jarrell (SE7520JR2)" +config BOARD_INTEL_MINNOWMAX + bool "Minnow Max" config BOARD_INTEL_MOHONPEAK bool "Mohon Peak CRB" config BOARD_INTEL_MTARVON @@ -40,6 +42,7 @@ source "src/mainboard/intel/eagleheights/Kconfig" source "src/mainboard/intel/emeraldlake2/Kconfig" source "src/mainboard/intel/baskingridge/Kconfig" source "src/mainboard/intel/jarrell/Kconfig" +source "src/mainboard/intel/minnowmax/Kconfig" source "src/mainboard/intel/mohonpeak/Kconfig" source "src/mainboard/intel/mtarvon/Kconfig" source "src/mainboard/intel/truxton/Kconfig" diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig new file mode 100644 index 0000000..0e83d5a --- /dev/null +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -0,0 +1,127 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_INTEL_MINNOWMAX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select OVERRIDE_MRC_CACHE_LOC + select TSC_MONOTONIC_TIMER + +config MAINBOARD_DIR + string + default "intel/minnowmax" + +config INCLUDE_ME + bool + default n + +config LOCK_MANAGEMENT_ENGINE + bool + default n + +config MAINBOARD_PART_NUMBER + string + default "Minnow Max 2GB" if MINNOWMAX_2GB_SKU + default "Minnow Max 1GB" + +choice + prompt "Memory SKU to build" + default MINNOWMAX_1GB_SKU + +config MINNOWMAX_1GB_SKU + bool "1GB" + +config MINNOWMAX_2GB_SKU + bool "2GB" +endchoice + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_LOC + hex + default 0xfffc0000 + +config FSP_FILE + string + default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_2gb.bin" if MINNOWMAX_2GB_SKU + default "../intel/mainboard/intel/minnowmax/fsp/FvFsp_E3825_1gb.bin" + +config MRC_CACHE_LOC_OVERRIDE + hex + default 0xfff90000 + depends on ENABLE_FSP_FAST_BOOT + +config CBFS_SIZE + hex + default 0x00300000 + +config DRIVERS_PS2_KEYBOARD + bool + default n + +config CONSOLE_POST + bool + default y + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config POST_IO + bool + default n + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default n + +config VGA_BIOS_FILE + string + default "../intel/mainboard/intel/minnowmax/Vga.dat" if VGA_BIOS + +endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc new file mode 100644 index 0000000..2f7a8c5 --- /dev/null +++ b/src/mainboard/intel/minnowmax/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-y += gpio.c +ramstage-y += irqroute.c diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 0000000..c1884c5 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/minnowmax/acpi/video.asl b/src/mainboard/intel/minnowmax/acpi/video.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c new file mode 100644 index 0000000..881c143 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> // hexdump +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> +#include <baytrail/iomap.h> + + +extern const unsigned char AmlCode[]; + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* No TPM Present */ + gnvs->tpmp = 0; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, + facs->length); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + ALIGN_CURRENT; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, + dsdt->length); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, + fadt->header.length); + + /* + * We explicitly add these tables later on: + */ + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, + hpet->header.length); + + /* If we want to use HPET Timers Linux wants an MADT */ + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, + madt->header.length); + + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, + mcfg->header.length); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ +#if CONFIG_HAVE_SMI_HANDLER + smm_setup_structures(gnvs, NULL, NULL); +#endif + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + ssdt = (acpi_header_t *)current; + memset(ssdt, 0, sizeof(acpi_header_t)); + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length) { + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, + ssdt->length); + ALIGN_CURRENT; + } else { + ssdt = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); + } + + ssdt2 = (acpi_header_t *)current; + memset(ssdt2, 0, sizeof(acpi_header_t)); + acpi_create_serialio_ssdt(ssdt2); + if (ssdt2->length) { + current += ssdt2->length; + acpi_add_table(rsdp, ssdt2); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, + ssdt2->length); + ALIGN_CURRENT; + } else { + ssdt2 = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); + } + + printk(BIOS_DEBUG, "current = %lx\n", current); + +#if IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) + printk(BIOS_DEBUG, "rsdp\n"); + hexdump(BIOS_DEBUG, rsdp, sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + hexdump(BIOS_DEBUG, rsdt, sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "hpet\n"); + hexdump(BIOS_DEBUG, hpet, hpet->header.length); + + printk(BIOS_DEBUG, "madt\n"); + hexdump(BIOS_DEBUG, madt, madt->header.length); + + printk(BIOS_DEBUG, "mcfg\n"); + hexdump(BIOS_DEBUG, mcfg, mcfg->header.length); + + printk(BIOS_DEBUG, "dsdt\n"); + hexdump(BIOS_DEBUG, dsdt, dsdt->length); + + if (ssdt != NULL) { + printk(BIOS_DEBUG, "ssdt\n"); + hexdump(BIOS_DEBUG, ssdt, ssdt->length); + } + + if (ssdt2 != NULL) { + printk(BIOS_DEBUG, "ssdt2\n"); + hexdump(BIOS_DEBUG, ssdt2, ssdt2->length); + } + + printk(BIOS_DEBUG, "fadt\n"); + hexdump(BIOS_DEBUG, fadt, fadt->header.length); + + printk(BIOS_DEBUG, "facs\n"); + hexdump(BIOS_DEBUG, facs, facs->length); + +#endif /* IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) */ + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout new file mode 100644 index 0000000..a668188 --- /dev/null +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1719 64 h 0 timestamp_value1 +1783 64 h 0 timestamp_value2 +1847 64 h 0 timestamp_value3 +1911 64 h 0 timestamp_value4 +1975 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb new file mode 100644 index 0000000..4e3833e --- /dev/null +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -0,0 +1,80 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/intel/fsp_baytrail + + #### ACPI Register Settings #### + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + #### FSP register settings #### + register "SataMode" = "SATA_MODE_AHCI" + register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "ApertureSize" = "APERTURE_SIZE_DEFAULT" + register "GttSize" = "GTT_SIZE_DEFAULT" + register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router - + device pci 02.0 on end # 8086 0F31 - GFX micro HDMI + device pci 03.0 off end # 8086 0F38 - MIPI - + + device pci 10.0 off end # 8086 0F14 - EMMC Port - + device pci 11.0 off end # 8086 0F15 - SDIO Port - + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI Onboard & HSEC + device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC + device pci 17.0 off end # 8086 0F50 - MMC Port - + device pci 18.0 on end # 8086 0F40 - SIO - DMA - + device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) - + device pci 18.2 off end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) - + device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) - + device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) - + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC + device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC + device pci 1a.0 on end # 8086 0F18 - TXE - + device pci 1b.0 off end # 8086 0F04 - HD Audio - + device pci 1c.0 off end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC + device pci 1d.0 off end # 8086 0F34 - USB EHCI - + device pci 1e.0 on end # 8086 0F06 - SIO - DMA - + device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC + device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC + device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC + device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC + device pci 1e.5 on end # 8086 0F0E - SPI LSEC + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000..cb2a4da --- /dev/null +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/minnowmax/fadt.c b/src/mainboard/intel/minnowmax/fadt.c new file mode 100644 index 0000000..91995f0 --- /dev/null +++ b/src/mainboard/intel/minnowmax/fadt.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <baytrail/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt,facs,dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c new file mode 100644 index 0000000..9b735cf --- /dev/null +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ + GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ + GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ + GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ + GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ + GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ + GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ + GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ + GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ + GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ + GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ + GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ + GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ + GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ + GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ + GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ + GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ + GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ + GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ + GPIO_FUNC1, /* GPIO_S0_SC[040] - TP12 (SD3_1P8EN) */ + GPIO_FUNC1, /* GPIO_S0_SC[041] - TP11 (/SD3_PWREN) */ + GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ + GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) */ + GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ + GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) */ + GPIO_FUNC0, /* GPIO_S0_SC[059] - HDMI_DCDC_ENB */ + GPIO_FUNC0, /* GPIO_S0_SC[060] - HDMI_LDSW_ENB */ + GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ + GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ + GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ + GPIO_FUNC1, /* GPIO_S0_SC[072] - SIO_UART1_RTSB */ + GPIO_FUNC1, /* GPIO_S0_SC[073] - SIO_UART1_CTSB */ + GPIO_FUNC1, /* GPIO_S0_SC[074] - SIO_UART2_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[075] - SIO_UART2_TXD */ + GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) */ + GPIO_FUNC1, /* GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) */ + GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[088] - LSS_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[089] - LSS_I2C_SCL */ + GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ + GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[092] - TP13 */ + GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[093] - TP16 */ + GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ + GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ + GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[00] - SOC_GPIO_S5_0 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[01] - SOC_GPIO_S5_1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */ + GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */ + GPIO_NC, /* GPIO_S5[04] - No Connect */ + GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 */ + GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ + GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ + GPIO_OUT_HIGH, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ + GPIO_OUT_HIGH, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ + GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ + GPIO_FUNC0, /* GPIO_S5[12] - PMC_SUSCLK0 */ + GPIO_FUNC1, /* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */ + GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ + GPIO_FUNC0, /* GPIO_S5[15] - PMC_PCIE_WAKE_R */ + GPIO_FUNC0, /* GPIO_S5[16] - PMC_PWRBTN */ + GPIO_NC1, /* GPIO_S5[17] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[18] - LPCPD_L (TP7) */ + GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ + GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ + GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ + GPIO_NC, /* GPIO_S5[22] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[23] - XDP_H_OBSDATA_A0 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[24] - XDP_H_OBSDATA_A1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[25] - XDP_H_OBSDATA_A2 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[26] - XDP_H_OBSDATA_A3 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[27] - EXP_GPIO1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[28] - EXP_GPIO2 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[29] - EXP_GPIO3 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[30] - EXP_GPIO4 */ + GPIO_NC, /* GPIO_S5[31] - No Connect */ + GPIO_NC, /* GPIO_S5[32] - No Connect */ + GPIO_NC, /* GPIO_S5[33] - No Connect */ + GPIO_NC, /* GPIO_S5[34] - No Connect */ + GPIO_NC, /* GPIO_S5[35] - No Connect */ + GPIO_NC, /* GPIO_S5[36] - No Connect */ + GPIO_NC, /* GPIO_S5[37] - No Connect */ + GPIO_NC, /* GPIO_S5[38] - No Connect */ + GPIO_NC, /* GPIO_S5[39] - No Connect */ + GPIO_NC, /* GPIO_S5[40] - No Connect */ + GPIO_NC, /* GPIO_S5[41] - No Connect */ + GPIO_NC, /* GPIO_S5[42] - No Connect */ + GPIO_NC, /* GPIO_S5[43] - No Connect */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c new file mode 100644 index 0000000..552be8f --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h new file mode 100644 index 0000000..bbb5134 --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 4), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c new file mode 100644 index 0000000..21767e2 --- /dev/null +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ +// printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " enable.\n"); + + +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +// printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); + + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c new file mode 100644 index 0000000..575e646 --- /dev/null +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <stddef.h> +#include <arch/cpu.h> +#include <lib.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <romstage_handoff.h> +#include <timestamp.h> +#include <baytrail/gpio.h> +#include <baytrail/iomap.h> +#include <baytrail/lpc.h> +#include <baytrail/pci_devs.h> +#include <baytrail/romstage.h> +#include <baytrail/acpi.h> +#include <baytrail/baytrail.h> +#include <drivers/intel/fsp/fsp_util.h> + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry() +{ + +} + +/** + * Get function disables - most of these will be done automatically + * @param fd_mask + * @param fd2_mask + */ +void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +{ + +} + + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ + +void late_mainboard_romstage_entry() +{ + +} + + +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + + /* Disable 2nd DIMM */ + UpdData->PcdMrcInitSPDAddr2 = 0x00; + + return; +}

1 0

New patch to review for coreboot: 4d81861 fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1
by Martin Roth 31 Jul '14

31 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6428 -gerrit commit 4d81861fe19ebc85f7819c7e803413f8d1bb29c0 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Jul 28 14:20:58 2014 -0600 fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1 The GPIO_NC setting sets up the gpio as a no-connect - sets it as an input, and pulls it high. It makes an assumption that the GPIO function is muxing function 0. There are a few GPIOs that are on function 1 instead: * GPIO_S0_SC[092-93] * GPIO_S5[11-21] For these GPIOs, use the GPIO_NC1 setting instead of GPIO_NC. Change-Id: Iac6790b40e87ad4ac9a3b265a8e10662186c1201 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/baytrail/gpio.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index 4c9e8a8..957b0de 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -156,8 +156,8 @@ #define PAD_VAL_DEFAULT PAD_VAL_INPUT /* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ +#define GPIO_INPUT_PU_10K(_func) \ + { .pad_conf0 = PAD_FUNC##_func | PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_MMIO, \ @@ -265,9 +265,10 @@ /* Common default GPIO settings */ #define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_10K +#define GPIO_INPUT_PU GPIO_INPUT_PU_10K(0) #define GPIO_INPUT_PD GPIO_INPUT_PD_10K -#define GPIO_NC GPIO_INPUT_PU_10K +#define GPIO_NC GPIO_INPUT_PU_10K(0) +#define GPIO_NC1 GPIO_INPUT_PU_10K(1) #define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */

1 0

New patch to review for coreboot: 11e582e libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.
by Isaac Christensen 31 Jul '14

31 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6427 -gerrit commit 11e582eede5bf317235036f03fb30fd0ea3dd210 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Aug 9 04:27:35 2013 -0700 libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig. When libpayload header files are included in the payload itself, it's possible that the payloads config settings will conflict with the ones in libpayload. It's also possible for the libpayload config settings to conflict with the payloads. To avoid that, the libpayload config settings have _LP_ (for libpayload) added to them. The symbols themselves as defined in the Config.in files are still the same, but the prefix added to them is now CONFIG_LP_ instead of just CONFIG_. Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65303 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/Makefile | 24 +- payloads/libpayload/Makefile.inc | 22 +- payloads/libpayload/arch/armv7/Makefile.inc | 2 +- payloads/libpayload/arch/armv7/coreboot.c | 19 +- payloads/libpayload/arch/armv7/main.c | 2 +- payloads/libpayload/arch/x86/Makefile.inc | 4 +- payloads/libpayload/arch/x86/coreboot.c | 14 +- payloads/libpayload/arch/x86/main.c | 2 +- payloads/libpayload/arch/x86/multiboot.c | 4 +- payloads/libpayload/arch/x86/rom_media.c | 10 +- payloads/libpayload/arch/x86/sysinfo.c | 6 +- payloads/libpayload/bin/lpgcc | 8 +- payloads/libpayload/configs/config.panther | 92 ++++---- payloads/libpayload/configs/defconfig | 106 ++++----- payloads/libpayload/crypto/sha1.c | 2 +- payloads/libpayload/curses/Makefile.inc | 254 ++++++++++----------- payloads/libpayload/curses/keyboard.c | 14 +- payloads/libpayload/curses/local.h | 4 +- .../libpayload/curses/pdcurses-backend/pdcdisp.c | 16 +- .../libpayload/curses/pdcurses-backend/pdckbd.c | 14 +- .../libpayload/curses/pdcurses-backend/pdcscrn.c | 2 +- .../libpayload/curses/pdcurses-backend/pdcsetsc.c | 4 +- .../libpayload/curses/pdcurses-backend/pdcutil.c | 2 +- payloads/libpayload/curses/tinycurses.c | 30 +-- payloads/libpayload/drivers/Makefile.inc | 80 +++---- payloads/libpayload/drivers/keyboard.c | 4 +- payloads/libpayload/drivers/nvram.c | 2 +- payloads/libpayload/drivers/serial.c | 12 +- payloads/libpayload/drivers/storage/ahci.c | 8 +- payloads/libpayload/drivers/storage/ata.c | 2 +- payloads/libpayload/drivers/storage/storage.c | 4 +- payloads/libpayload/drivers/usb/ehci.c | 2 +- payloads/libpayload/drivers/usb/ohci.c | 2 +- payloads/libpayload/drivers/usb/usb.c | 6 +- payloads/libpayload/drivers/usb/usbhid.c | 2 +- payloads/libpayload/drivers/usb/usbinit.c | 28 +-- payloads/libpayload/drivers/usb/xhci.c | 6 +- payloads/libpayload/drivers/usb/xhci_private.h | 2 +- payloads/libpayload/drivers/video/video.c | 12 +- payloads/libpayload/include/cbfs_core.h | 2 +- payloads/libpayload/include/endian.h | 4 +- payloads/libpayload/include/kconfig.h | 4 +- payloads/libpayload/include/libpayload.h | 4 +- payloads/libpayload/include/stdlib.h | 2 +- payloads/libpayload/include/storage/storage.h | 2 +- payloads/libpayload/include/sysinfo.h | 8 +- payloads/libpayload/libc/Makefile.inc | 18 +- payloads/libpayload/libc/console.c | 12 +- payloads/libpayload/libc/exec.c | 4 +- payloads/libpayload/libc/malloc.c | 14 +- payloads/libpayload/libc/time.c | 4 +- payloads/libpayload/libcbfs/Makefile.inc | 4 +- payloads/libpayload/libcbfs/cbfs.c | 8 +- payloads/libpayload/libcbfs/cbfs_core.c | 4 +- payloads/libpayload/liblzma/Makefile.inc | 2 +- payloads/libpayload/tests/libpayload-config.h | 48 ++-- payloads/libpayload/util/kconfig/confdata.c | 52 ++--- payloads/libpayload/util/kconfig/mconf.c | 20 +- 58 files changed, 523 insertions(+), 522 deletions(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index a1e8dc7..6416519 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -57,7 +57,7 @@ export KCONFIG_AUTOCONFIG := $(obj)/auto.conf # directory containing the toplevel Makefile.inc TOPLEVEL := . -CONFIG_SHELL := sh +CONFIG_LP_SHELL := sh KBUILD_DEFCONFIG := configs/defconfig UNAME_RELEASE := $(shell uname -r) DOTCONFIG ?= .config @@ -91,15 +91,15 @@ include util/kconfig/Makefile include $(HAVE_DOTCONFIG) -ARCHDIR-$(CONFIG_ARCH_ARMV7) := armv7 -ARCHDIR-$(CONFIG_ARCH_X86) := x86 +ARCHDIR-$(CONFIG_LP_ARCH_ARMV7) := armv7 +ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 ARCH-y := $(ARCHDIR-y) # If architecture folder name is different from GCC binutils architecture name, # override here. -ARCH-$(CONFIG_ARCH_ARMV7) := armv7 -ARCH-$(CONFIG_ARCH_X86) := i386 +ARCH-$(CONFIG_LP_ARCH_ARMV7) := armv7 +ARCH-$(CONFIG_LP_ARCH_X86) := i386 CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) @@ -137,13 +137,13 @@ real-all: config else ifneq ($(INNER_SCANBUILD),y) -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) CC:=clang -m32 HOSTCC:=clang endif endif -ifeq ($(CONFIG_CCACHE),y) +ifeq ($(CONFIG_LP_CCACHE),y) CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH))))) ifeq ($(CCACHE),) $(error ccache selected, but not found in PATH) @@ -161,12 +161,12 @@ strip_quotes = $(subst ",,$(subst \",,$(1))) # other files ifeq ($(INNER_SCANBUILD),y) -CONFIG_SCANBUILD_ENABLE:= +CONFIG_LP_SCANBUILD_ENABLE:= endif -ifeq ($(CONFIG_SCANBUILD_ENABLE),y) -ifneq ($(CONFIG_SCANBUILD_REPORT_LOCATION),) -CONFIG_SCANBUILD_REPORT_LOCATION:=-o $(CONFIG_SCANBUILD_REPORT_LOCATION) +ifeq ($(CONFIG_LP_SCANBUILD_ENABLE),y) +ifneq ($(CONFIG_LP_SCANBUILD_REPORT_LOCATION),) +CONFIG_LP_SCANBUILD_REPORT_LOCATION:=-o $(CONFIG_LP_SCANBUILD_REPORT_LOCATION) endif real-all: echo '#!/bin/sh' > .ccwrap @@ -175,7 +175,7 @@ real-all: echo 'if [ "$$1" = "--hostcxx" ]; then shift; CC="$(HOSTCXX)"; fi' >> .ccwrap echo 'eval $$CC $$*' >> .ccwrap chmod +x .ccwrap - scan-build $(CONFIG_SCANBUILD_REPORT_LOCATION) -analyze-headers --use-cc=$(top)/.ccwrap --use-c++=$(top)/.ccwrap $(MAKE) INNER_SCANBUILD=y + scan-build $(CONFIG_LP_SCANBUILD_REPORT_LOCATION) -analyze-headers --use-cc=$(top)/.ccwrap --use-c++=$(top)/.ccwrap $(MAKE) INNER_SCANBUILD=y else real-all: real-target endif diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index ea1bcff..a5de4b3 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -31,26 +31,26 @@ export KERNELVERSION := 0.2.0 -ARCHDIR-$(CONFIG_ARCH_ARMV7) := armv7 -ARCHDIR-$(CONFIG_ARCH_X86) := x86 +ARCHDIR-$(CONFIG_LP_ARCH_ARMV7) := armv7 +ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 DESTDIR ?= install real-target: lib -classes-$(CONFIG_PCI) += libpci -classes-$(CONFIG_LIBC) += libc -classes-$(CONFIG_CURSES) += libcurses -classes-$(CONFIG_PDCURSES) += libmenu libform libpanel -classes-$(CONFIG_CBFS) += libcbfs -classes-$(CONFIG_LZMA) += liblzma +classes-$(CONFIG_LP_PCI) += libpci +classes-$(CONFIG_LP_LIBC) += libc +classes-$(CONFIG_LP_CURSES) += libcurses +classes-$(CONFIG_LP_PDCURSES) += libmenu libform libpanel +classes-$(CONFIG_LP_CBFS) += libcbfs +classes-$(CONFIG_LP_LZMA) += liblzma libraries := $(classes-y) classes-y += head.o subdirs-y := arch/$(ARCHDIR-y) subdirs-y += crypto libc drivers libpci -subdirs-$(CONFIG_CURSES) += curses -subdirs-$(CONFIG_CBFS) += libcbfs -subdirs-$(CONFIG_LZMA) += liblzma +subdirs-$(CONFIG_LP_CURSES) += curses +subdirs-$(CONFIG_LP_CBFS) += libcbfs +subdirs-$(CONFIG_LP_LZMA) += liblzma INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index a27fdd4..cd909bb 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -36,4 +36,4 @@ libc-y += virtual.c libc-y += memcpy.S memset.S libc-y += exception_asm.S exception.c libc-y += cache.c -libcbfs-$(CONFIG_CBFS) += dummy_media.c +libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/armv7/coreboot.c index bc9b47e..076010d 100644 --- a/payloads/libpayload/arch/armv7/coreboot.c +++ b/payloads/libpayload/arch/armv7/coreboot.c @@ -56,7 +56,7 @@ static void cb_parse_memory(void *ptr, struct sysinfo_t *info) for (i = 0; i < count; i++) { struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); -#ifdef CONFIG_MEMMAP_RAM_ONLY +#ifdef CONFIG_LP_MEMMAP_RAM_ONLY if (range->type != CB_MEM_RAM) continue; #endif @@ -78,7 +78,7 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) info->serial = ((struct cb_serial *)ptr); } -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) { struct cb_vbnv *vbnv = (struct cb_vbnv *)ptr; @@ -126,7 +126,7 @@ static void cb_parse_mrc_cache(unsigned char *ptr, struct sysinfo_t *info) info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); } -#ifdef CONFIG_NVRAM +#ifdef CONFIG_LP_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { /* ptr points to a coreboot table entry and is already virtual */ @@ -142,7 +142,7 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) } #endif -#ifdef CONFIG_COREBOOT_VIDEO_CONSOLE +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { /* ptr points to a coreboot table entry and is already virtual */ @@ -233,7 +233,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_ASSEMBLER: cb_parse_string(ptr, &info->assembler); break; -#ifdef CONFIG_NVRAM +#ifdef CONFIG_LP_NVRAM case CB_TAG_CMOS_OPTION_TABLE: cb_parse_optiontable(ptr, info); break; @@ -241,7 +241,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) cb_parse_checksum(ptr, info); break; #endif -#ifdef CONFIG_COREBOOT_VIDEO_CONSOLE +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE // FIXME we should warn on serial if coreboot set up a // framebuffer buf the payload does not know about it. case CB_TAG_FRAMEBUFFER: @@ -251,7 +251,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MAINBOARD: info->mainboard = (struct cb_mainboard *)ptr; break; -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS case CB_TAG_GPIO: cb_parse_gpios(ptr, info); break; @@ -284,8 +284,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(CONFIG_COREBOOT_INFO_RANGE_BASE), - CONFIG_COREBOOT_INFO_RANGE_SIZE, info); + int ret = cb_parse_header( + phys_to_virt(CONFIG_LP_COREBOOT_INFO_RANGE_BASE), + CONFIG_LP_COREBOOT_INFO_RANGE_SIZE, info); return (ret == 1) ? 0 : -1; } diff --git a/payloads/libpayload/arch/armv7/main.c b/payloads/libpayload/arch/armv7/main.c index 93cfce5..4e7c05d 100644 --- a/payloads/libpayload/arch/armv7/main.c +++ b/payloads/libpayload/arch/armv7/main.c @@ -48,7 +48,7 @@ void start_main(void) lib_get_sysinfo(); /* Optionally set up the consoles. */ -#ifndef CONFIG_SKIP_CONSOLE_INIT +#ifndef CONFIG_LP_SKIP_CONSOLE_INIT console_init(); #endif diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 0977eb1..8efbc12 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -33,7 +33,7 @@ libc-y += timer.c coreboot.c util.S libc-y += exec.S virtual.c libc-y += string.c -libcbfs-$(CONFIG_CBFS) += rom_media.c +libcbfs-$(CONFIG_LP_CBFS) += rom_media.c # Multiboot support is configurable -libc-$(CONFIG_MULTIBOOT) += multiboot.c +libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 43aa970..05ab336 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -57,7 +57,7 @@ static void cb_parse_memory(void *ptr, struct sysinfo_t *info) for (i = 0; i < count; i++) { struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); -#ifdef CONFIG_MEMMAP_RAM_ONLY +#ifdef CONFIG_LP_MEMMAP_RAM_ONLY if (range->type != CB_MEM_RAM) continue; #endif @@ -79,7 +79,7 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) info->serial = ((struct cb_serial *)ptr); } -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) { struct cb_vboot_handoff *vbho = (struct cb_vboot_handoff *)ptr; @@ -141,7 +141,7 @@ static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); } -#ifdef CONFIG_NVRAM +#ifdef CONFIG_LP_NVRAM static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { /* ptr points to a coreboot table entry and is already virtual */ @@ -157,7 +157,7 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) } #endif -#ifdef CONFIG_COREBOOT_VIDEO_CONSOLE +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { /* ptr points to a coreboot table entry and is already virtual */ @@ -254,7 +254,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_ASSEMBLER: cb_parse_string(ptr, &info->assembler); break; -#ifdef CONFIG_NVRAM +#ifdef CONFIG_LP_NVRAM case CB_TAG_CMOS_OPTION_TABLE: cb_parse_optiontable(ptr, info); break; @@ -262,7 +262,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) cb_parse_checksum(ptr, info); break; #endif -#ifdef CONFIG_COREBOOT_VIDEO_CONSOLE +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE // FIXME we should warn on serial if coreboot set up a // framebuffer buf the payload does not know about it. case CB_TAG_FRAMEBUFFER: @@ -271,7 +271,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) #endif case CB_TAG_MAINBOARD: info->mainboard = (struct cb_mainboard *)ptr; -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS case CB_TAG_GPIO: cb_parse_gpios(ptr, info); break; diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c index 1bac7a8..c788f0f 100644 --- a/payloads/libpayload/arch/x86/main.c +++ b/payloads/libpayload/arch/x86/main.c @@ -50,7 +50,7 @@ void start_main(void) lib_get_sysinfo(); /* Optionally set up the consoles. */ -#ifndef CONFIG_SKIP_CONSOLE_INIT +#ifndef CONFIG_LP_SKIP_CONSOLE_INIT console_init(); #endif diff --git a/payloads/libpayload/arch/x86/multiboot.c b/payloads/libpayload/arch/x86/multiboot.c index fa0c576..c2c3607 100644 --- a/payloads/libpayload/arch/x86/multiboot.c +++ b/payloads/libpayload/arch/x86/multiboot.c @@ -45,7 +45,7 @@ static void mb_parse_mmap(struct multiboot_header *table, while(ptr < (start + table->mmap_length)) { struct multiboot_mmap *mmap = (struct multiboot_mmap *) ptr; -#ifdef CONFIG_MEMMAP_RAM_ONLY +#ifdef CONFIG_LP_MEMMAP_RAM_ONLY /* 1 == normal RAM. Ignore everything else for now */ if (mmap->type == 1) { @@ -56,7 +56,7 @@ static void mb_parse_mmap(struct multiboot_header *table, if (++info->n_memranges == SYSINFO_MAX_MEM_RANGES) return; -#ifdef CONFIG_MEMMAP_RAM_ONLY +#ifdef CONFIG_LP_MEMMAP_RAM_ONLY } #endif diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c index e338d1c..5b8cbad 100644 --- a/payloads/libpayload/arch/x86/rom_media.c +++ b/payloads/libpayload/arch/x86/rom_media.c @@ -83,19 +83,19 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { struct cbfs_header *header = (struct cbfs_header*) *(uint32_t*)(0xfffffffc); if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { -#if defined(CONFIG_ROM_SIZE) +#if defined(CONFIG_LP_ROM_SIZE) printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); - media->context = (void*)CONFIG_ROM_SIZE; + media->context = (void*)CONFIG_LP_ROM_SIZE; #else return -1; #endif } else { uint32_t romsize = ntohl(header->romsize); media->context = (void*)romsize; -#if defined(CONFIG_ROM_SIZE) - if (CONFIG_ROM_SIZE != romsize) +#if defined(CONFIG_LP_ROM_SIZE) + if (CONFIG_LP_ROM_SIZE != romsize) printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", - CONFIG_ROM_SIZE, romsize); + CONFIG_LP_ROM_SIZE, romsize); #endif } media->open = x86_rom_open; diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c index 6c1ef3f..8e8b1c8 100644 --- a/payloads/libpayload/arch/x86/sysinfo.c +++ b/payloads/libpayload/arch/x86/sysinfo.c @@ -38,8 +38,8 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = 200, -#ifdef CONFIG_SERIAL_CONSOLE - .ser_ioport = CONFIG_SERIAL_IOBASE, +#ifdef CONFIG_LP_SERIAL_CONSOLE + .ser_ioport = CONFIG_LP_SERIAL_IOBASE, #else .ser_ioport = 0x3f8, #endif @@ -52,7 +52,7 @@ int lib_get_sysinfo(void) /* Get the CPU speed (for delays). */ lib_sysinfo.cpu_khz = get_cpu_speed(); -#ifdef CONFIG_MULTIBOOT +#ifdef CONFIG_LP_MULTIBOOT /* Get the information from the multiboot tables, * if they exist */ get_multiboot_info(&lib_sysinfo); diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 4eca091..32ec568 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -68,14 +68,14 @@ else exit 1 fi -if [ "$CONFIG_ARCH_ARMV7" = "y" ]; then +if [ "$CONFIG_LP_ARCH_ARMV7" = "y" ]; then _ARCHINCDIR=$_INCDIR/armv7 _ARCHLIBDIR=$_LIBDIR/armv7 _ARCHEXTRA="" _ARCH=armv7 fi -if [ "$CONFIG_ARCH_X86" = "y" ]; then +if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHINCDIR=$_INCDIR/x86 _ARCHLIBDIR=$_LIBDIR/x86 _ARCHEXTRA="-m32 " @@ -135,11 +135,11 @@ done _CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" -if [ "$CONFIG_PDCURSES" = y ]; then +if [ "$CONFIG_LP_PDCURSES" = y ]; then _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses-3.4" fi -if [ "$CONFIG_TINYCURSES" = y ]; then +if [ "$CONFIG_LP_TINYCURSES" = y ]; then _CFLAGS="$_CFLAGS -I$BASE/../curses" fi diff --git a/payloads/libpayload/configs/config.panther b/payloads/libpayload/configs/config.panther index 005c6eb..ec0f11d 100644 --- a/payloads/libpayload/configs/config.panther +++ b/payloads/libpayload/configs/config.panther @@ -7,65 +7,65 @@ # # Generic Options # -# CONFIG_EXPERIMENTAL is not set -# CONFIG_OBSOLETE is not set -# CONFIG_DEVELOPER is not set -CONFIG_CHROMEOS=y +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_OBSOLETE is not set +# CONFIG_LP_DEVELOPER is not set +CONFIG_LP_CHROMEOS=y # # Architecture Options # -# CONFIG_ARCH_ARMV7 is not set -# CONFIG_ARCH_POWERPC is not set -CONFIG_ARCH_X86=y -# CONFIG_MEMMAP_RAM_ONLY is not set -# CONFIG_MULTIBOOT is not set +# CONFIG_LP_ARCH_ARMV7 is not set +# CONFIG_LP_ARCH_POWERPC is not set +CONFIG_LP_ARCH_X86=y +# CONFIG_LP_MEMMAP_RAM_ONLY is not set +# CONFIG_LP_MULTIBOOT is not set # # Standard Libraries # -CONFIG_LIBC=y -# CONFIG_CURSES is not set -CONFIG_CBFS=y -CONFIG_LZMA=y +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y # # Console Options # -CONFIG_SKIP_CONSOLE_INIT=y -CONFIG_CBMEM_CONSOLE=y -CONFIG_SERIAL_CONSOLE=y -CONFIG_8250_SERIAL_CONSOLE=y -CONFIG_SERIAL_IOBASE=0x3f8 -# CONFIG_SERIAL_SET_SPEED is not set -# CONFIG_SERIAL_ACS_FALLBACK is not set -CONFIG_VIDEO_CONSOLE=y -# CONFIG_VGA_VIDEO_CONSOLE is not set -# CONFIG_GEODELX_VIDEO_CONSOLE is not set -CONFIG_COREBOOT_VIDEO_CONSOLE=y -CONFIG_PC_KEYBOARD=y -CONFIG_PC_KEYBOARD_LAYOUT_US=y -# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set +CONFIG_LP_SKIP_CONSOLE_INIT=y +CONFIG_LP_CBMEM_CONSOLE=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_8250_SERIAL_CONSOLE=y +CONFIG_LP_SERIAL_IOBASE=0x3f8 +# CONFIG_LP_SERIAL_SET_SPEED is not set +# CONFIG_LP_SERIAL_ACS_FALLBACK is not set +CONFIG_LP_VIDEO_CONSOLE=y +# CONFIG_LP_VGA_VIDEO_CONSOLE is not set +# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +CONFIG_LP_PC_KEYBOARD=y +CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set # # Drivers # -CONFIG_PCI=y -CONFIG_NVRAM=y -# CONFIG_RTC_PORT_EXTENDED_VIA is not set -# CONFIG_SPEAKER is not set -# CONFIG_STORAGE is not set -CONFIG_USB=y -# CONFIG_USB_UHCI is not set -# CONFIG_USB_OHCI is not set -# CONFIG_USB_EHCI is not set -CONFIG_USB_XHCI=y -CONFIG_USB_HID=y -CONFIG_USB_HUB=y -CONFIG_USB_MSC=y -CONFIG_USB_PCI=y -# CONFIG_USB_MEMORY is not set -# CONFIG_BIG_ENDIAN is not set -CONFIG_LITTLE_ENDIAN=y -CONFIG_IO_ADDRESS_SPACE=y -CONFIG_ARCH_SPECIFIC_OPTIONS=y +CONFIG_LP_PCI=y +CONFIG_LP_NVRAM=y +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +# CONFIG_LP_SPEAKER is not set +# CONFIG_LP_STORAGE is not set +CONFIG_LP_USB=y +# CONFIG_LP_USB_UHCI is not set +# CONFIG_LP_USB_OHCI is not set +# CONFIG_LP_USB_EHCI is not set +CONFIG_LP_USB_XHCI=y +CONFIG_LP_USB_HID=y +CONFIG_LP_USB_HUB=y +CONFIG_LP_USB_MSC=y +CONFIG_LP_USB_PCI=y +# CONFIG_LP_USB_MEMORY is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +CONFIG_LP_IO_ADDRESS_SPACE=y +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index b41727f..c4e0d15 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -7,72 +7,72 @@ # # Generic Options # -# CONFIG_EXPERIMENTAL is not set -# CONFIG_OBSOLETE is not set -# CONFIG_DEVELOPER is not set -# CONFIG_CHROMEOS is not set +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_OBSOLETE is not set +# CONFIG_LP_DEVELOPER is not set +# CONFIG_LP_CHROMEOS is not set # # Architecture Options # -# CONFIG_ARCH_ARMV7 is not set -CONFIG_ARCH_X86=y -# CONFIG_MEMMAP_RAM_ONLY is not set -# CONFIG_MULTIBOOT is not set +# CONFIG_LP_ARCH_ARMV7 is not set +CONFIG_LP_ARCH_X86=y +# CONFIG_LP_MEMMAP_RAM_ONLY is not set +# CONFIG_LP_MULTIBOOT is not set # # Standard Libraries # -CONFIG_LIBC=y -CONFIG_CURSES=y -# CONFIG_TINYCURSES is not set -CONFIG_PDCURSES=y -CONFIG_CBFS=y -CONFIG_LZMA=y +CONFIG_LP_LIBC=y +CONFIG_LP_CURSES=y +# CONFIG_LP_TINYCURSES is not set +CONFIG_LP_PDCURSES=y +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y # # Console Options # -# CONFIG_SKIP_CONSOLE_INIT is not set -CONFIG_CBMEM_CONSOLE=y -CONFIG_SERIAL_CONSOLE=y -CONFIG_X86_SERIAL_CONSOLE=y -CONFIG_SERIAL_IOBASE=0x3f8 -# CONFIG_SERIAL_SET_SPEED is not set -# CONFIG_SERIAL_ACS_FALLBACK is not set -CONFIG_VIDEO_CONSOLE=y -CONFIG_VGA_VIDEO_CONSOLE=y -# CONFIG_GEODELX_VIDEO_CONSOLE is not set -CONFIG_COREBOOT_VIDEO_CONSOLE=y -CONFIG_PC_KEYBOARD=y -CONFIG_PC_KEYBOARD_LAYOUT_US=y -# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set +# CONFIG_LP_SKIP_CONSOLE_INIT is not set +CONFIG_LP_CBMEM_CONSOLE=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_X86_SERIAL_CONSOLE=y +CONFIG_LP_SERIAL_IOBASE=0x3f8 +# CONFIG_LP_SERIAL_SET_SPEED is not set +# CONFIG_LP_SERIAL_ACS_FALLBACK is not set +CONFIG_LP_VIDEO_CONSOLE=y +CONFIG_LP_VGA_VIDEO_CONSOLE=y +# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +CONFIG_LP_PC_KEYBOARD=y +CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set # # Drivers # -CONFIG_PCI=y -CONFIG_NVRAM=y -# CONFIG_RTC_PORT_EXTENDED_VIA is not set -CONFIG_SPEAKER=y -CONFIG_STORAGE=y -# CONFIG_STORAGE_64BIT_LBA is not set -CONFIG_STORAGE_ATA=y -CONFIG_STORAGE_ATAPI=y -CONFIG_STORAGE_AHCI=y -CONFIG_STORAGE_AHCI_ONLY_TESTED=y -CONFIG_USB=y -CONFIG_USB_UHCI=y -CONFIG_USB_OHCI=y -CONFIG_USB_EHCI=y -CONFIG_USB_XHCI=y -CONFIG_USB_HID=y -CONFIG_USB_HUB=y -CONFIG_USB_MSC=y -CONFIG_USB_GEN_HUB=y -CONFIG_USB_PCI=y -# CONFIG_USB_MEMORY is not set -# CONFIG_BIG_ENDIAN is not set -CONFIG_LITTLE_ENDIAN=y -CONFIG_IO_ADDRESS_SPACE=y -CONFIG_ARCH_SPECIFIC_OPTIONS=y +CONFIG_LP_PCI=y +CONFIG_LP_NVRAM=y +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +CONFIG_LP_SPEAKER=y +CONFIG_LP_STORAGE=y +# CONFIG_LP_STORAGE_64BIT_LBA is not set +CONFIG_LP_STORAGE_ATA=y +CONFIG_LP_STORAGE_ATAPI=y +CONFIG_LP_STORAGE_AHCI=y +CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y +CONFIG_LP_USB=y +CONFIG_LP_USB_UHCI=y +CONFIG_LP_USB_OHCI=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y +CONFIG_LP_USB_HID=y +CONFIG_LP_USB_HUB=y +CONFIG_LP_USB_MSC=y +CONFIG_LP_USB_GEN_HUB=y +CONFIG_LP_USB_PCI=y +# CONFIG_LP_USB_MEMORY is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +CONFIG_LP_IO_ADDRESS_SPACE=y +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/crypto/sha1.c b/payloads/libpayload/crypto/sha1.c index c973e18..615ed72 100644 --- a/payloads/libpayload/crypto/sha1.c +++ b/payloads/libpayload/crypto/sha1.c @@ -30,7 +30,7 @@ typedef unsigned int u_int; /* Moved from libpayload.h */ -#ifdef CONFIG_LITTLE_ENDIAN +#ifdef CONFIG_LP_LITTLE_ENDIAN #define BYTE_ORDER LITTLE_ENDIAN #else #define BYTE_ORDER BIG_ENDIAN diff --git a/payloads/libpayload/curses/Makefile.inc b/payloads/libpayload/curses/Makefile.inc index 5d14431..025a051 100644 --- a/payloads/libpayload/curses/Makefile.inc +++ b/payloads/libpayload/curses/Makefile.inc @@ -27,142 +27,142 @@ ## SUCH DAMAGE. ## -ifeq ($(CONFIG_TINYCURSES),y) +ifeq ($(CONFIG_LP_TINYCURSES),y) INCLUDES += -Icurses endif -libcurses-$(CONFIG_TINYCURSES) += keyboard.c -libcurses-$(CONFIG_TINYCURSES) += tinycurses.c -libcurses-$(CONFIG_TINYCURSES) += colors.c +libcurses-$(CONFIG_LP_TINYCURSES) += keyboard.c +libcurses-$(CONFIG_LP_TINYCURSES) += tinycurses.c +libcurses-$(CONFIG_LP_TINYCURSES) += colors.c -includes-$(CONFIG_TINYCURSES) += curses.h +includes-$(CONFIG_LP_TINYCURSES) += curses.h -ifeq ($(CONFIG_PDCURSES),y) +ifeq ($(CONFIG_LP_PDCURSES),y) INCLUDES += -D_LP64=0 -Icurses/PDCurses-3.4 -Icurses/pdcurses-backend -Icurses/menu -Icurses/form endif -libcurses-$(CONFIG_PDCURSES) += pdcurses-backend/pdcdisp.c -libcurses-$(CONFIG_PDCURSES) += pdcurses-backend/pdcgetsc.c -libcurses-$(CONFIG_PDCURSES) += pdcurses-backend/pdckbd.c -libcurses-$(CONFIG_PDCURSES) += pdcurses-backend/pdcscrn.c -libcurses-$(CONFIG_PDCURSES) += pdcurses-backend/pdcsetsc.c -libcurses-$(CONFIG_PDCURSES) += pdcurses-backend/pdcutil.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/addch.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/move.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/overlay.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/refresh.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/terminfo.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/window.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/util.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/inopts.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/addstr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/keyname.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/instr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/clear.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/addchstr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/kernel.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/pad.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/insstr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/border.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/getyx.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/getstr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/getch.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/termattr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/outopts.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/color.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/deleteln.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/initscr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/slk.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/delch.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/touch.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/mouse.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/scanw.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/scroll.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/printw.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/bkgd.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/inch.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/attr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/insch.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/inchstr.c -libcurses-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/beep.c +libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdcdisp.c +libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdcgetsc.c +libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdckbd.c +libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdcscrn.c +libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdcsetsc.c +libcurses-$(CONFIG_LP_PDCURSES) += pdcurses-backend/pdcutil.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/addch.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/move.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/overlay.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/refresh.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/terminfo.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/window.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/util.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/inopts.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/addstr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/keyname.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/instr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/clear.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/addchstr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/kernel.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/pad.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/insstr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/border.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/getyx.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/getstr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/getch.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/termattr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/outopts.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/color.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/deleteln.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/initscr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/slk.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/delch.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/touch.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/mouse.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/scanw.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/scroll.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/printw.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/bkgd.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/inch.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/attr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/insch.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/inchstr.c +libcurses-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/beep.c -includes-$(CONFIG_PDCURSES) += pdcurses-backend/nc_alloc.h -includes-$(CONFIG_PDCURSES) += pdcurses-backend/ncurses_cfg.h -includes-$(CONFIG_PDCURSES) += PDCurses-3.4/curses.h -includes-$(CONFIG_PDCURSES) += PDCurses-3.4/term.h -includes-$(CONFIG_PDCURSES) += PDCurses-3.4/panel.h -includes-$(CONFIG_PDCURSES) += menu/eti.h -includes-$(CONFIG_PDCURSES) += menu/menu.h -includes-$(CONFIG_PDCURSES) += menu/mf_common.h -includes-$(CONFIG_PDCURSES) += form/form.h +includes-$(CONFIG_LP_PDCURSES) += pdcurses-backend/nc_alloc.h +includes-$(CONFIG_LP_PDCURSES) += pdcurses-backend/ncurses_cfg.h +includes-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/curses.h +includes-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/term.h +includes-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/panel.h +includes-$(CONFIG_LP_PDCURSES) += menu/eti.h +includes-$(CONFIG_LP_PDCURSES) += menu/menu.h +includes-$(CONFIG_LP_PDCURSES) += menu/mf_common.h +includes-$(CONFIG_LP_PDCURSES) += form/form.h -libpanel-$(CONFIG_PDCURSES) += PDCurses-3.4/pdcurses/panel.c +libpanel-$(CONFIG_LP_PDCURSES) += PDCurses-3.4/pdcurses/panel.c -libmenu-$(CONFIG_PDCURSES) += menu/m_req_name.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_nam.c -libmenu-$(CONFIG_PDCURSES) += menu/m_pad.c -libmenu-$(CONFIG_PDCURSES) += menu/m_cursor.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_new.c -libmenu-$(CONFIG_PDCURSES) += menu/m_attribs.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_opt.c -libmenu-$(CONFIG_PDCURSES) += menu/m_format.c -libmenu-$(CONFIG_PDCURSES) += menu/m_post.c -libmenu-$(CONFIG_PDCURSES) += menu/m_userptr.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_cur.c -libmenu-$(CONFIG_PDCURSES) += menu/m_driver.c -libmenu-$(CONFIG_PDCURSES) += menu/m_sub.c -libmenu-$(CONFIG_PDCURSES) += menu/m_win.c -libmenu-$(CONFIG_PDCURSES) += menu/m_global.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_vis.c -libmenu-$(CONFIG_PDCURSES) += menu/m_new.c -libmenu-$(CONFIG_PDCURSES) += menu/m_scale.c -libmenu-$(CONFIG_PDCURSES) += menu/m_spacing.c -libmenu-$(CONFIG_PDCURSES) += menu/m_opts.c -libmenu-$(CONFIG_PDCURSES) += menu/m_pattern.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_val.c -libmenu-$(CONFIG_PDCURSES) += menu/m_hook.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_use.c -libmenu-$(CONFIG_PDCURSES) += menu/m_items.c -libmenu-$(CONFIG_PDCURSES) += menu/m_item_top.c -libform-$(CONFIG_PDCURSES) += form/frm_page.c -libform-$(CONFIG_PDCURSES) += form/frm_opts.c -libform-$(CONFIG_PDCURSES) += form/frm_def.c -libform-$(CONFIG_PDCURSES) += form/frm_req_name.c -libform-$(CONFIG_PDCURSES) += form/fty_alpha.c -libform-$(CONFIG_PDCURSES) += form/frm_driver.c -libform-$(CONFIG_PDCURSES) += form/fld_user.c -libform-$(CONFIG_PDCURSES) += form/frm_win.c -libform-$(CONFIG_PDCURSES) += form/fld_newftyp.c -#libform-$(CONFIG_PDCURSES) += form/fty_regex.c -libform-$(CONFIG_PDCURSES) += form/fld_stat.c -libform-$(CONFIG_PDCURSES) += form/fld_pad.c -libform-$(CONFIG_PDCURSES) += form/fld_current.c -libform-$(CONFIG_PDCURSES) += form/frm_post.c -#libform-$(CONFIG_PDCURSES) += form/f_trace.c -libform-$(CONFIG_PDCURSES) += form/fty_generic.c -libform-$(CONFIG_PDCURSES) += form/fld_page.c -libform-$(CONFIG_PDCURSES) += form/frm_hook.c -libform-$(CONFIG_PDCURSES) += form/frm_scale.c -libform-$(CONFIG_PDCURSES) += form/fty_int.c -libform-$(CONFIG_PDCURSES) += form/fty_alnum.c -libform-$(CONFIG_PDCURSES) += form/frm_cursor.c -#libform-$(CONFIG_PDCURSES) += form/fty_ipv4.c -libform-$(CONFIG_PDCURSES) += form/fld_link.c -libform-$(CONFIG_PDCURSES) += form/fld_arg.c -libform-$(CONFIG_PDCURSES) += form/fld_move.c -libform-$(CONFIG_PDCURSES) += form/fld_def.c -libform-$(CONFIG_PDCURSES) += form/fld_type.c -libform-$(CONFIG_PDCURSES) += form/fld_max.c -libform-$(CONFIG_PDCURSES) += form/fld_ftlink.c -libform-$(CONFIG_PDCURSES) += form/fld_ftchoice.c -libform-$(CONFIG_PDCURSES) += form/fld_info.c -libform-$(CONFIG_PDCURSES) += form/frm_user.c -#libform-$(CONFIG_PDCURSES) += form/fty_num.c -libform-$(CONFIG_PDCURSES) += form/frm_sub.c -libform-$(CONFIG_PDCURSES) += form/fty_enum.c -libform-$(CONFIG_PDCURSES) += form/frm_data.c -libform-$(CONFIG_PDCURSES) += form/fld_opts.c -libform-$(CONFIG_PDCURSES) += form/fld_attr.c -libform-$(CONFIG_PDCURSES) += form/fld_dup.c -libform-$(CONFIG_PDCURSES) += form/fld_just.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_req_name.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_nam.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_pad.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_cursor.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_new.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_attribs.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_opt.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_format.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_post.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_userptr.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_cur.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_driver.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_sub.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_win.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_global.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_vis.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_new.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_scale.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_spacing.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_opts.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_pattern.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_val.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_hook.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_use.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_items.c +libmenu-$(CONFIG_LP_PDCURSES) += menu/m_item_top.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_page.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_opts.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_def.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_req_name.c +libform-$(CONFIG_LP_PDCURSES) += form/fty_alpha.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_driver.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_user.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_win.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_newftyp.c +#libform-$(CONFIG_LP_PDCURSES) += form/fty_regex.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_stat.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_pad.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_current.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_post.c +#libform-$(CONFIG_LP_PDCURSES) += form/f_trace.c +libform-$(CONFIG_LP_PDCURSES) += form/fty_generic.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_page.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_hook.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_scale.c +libform-$(CONFIG_LP_PDCURSES) += form/fty_int.c +libform-$(CONFIG_LP_PDCURSES) += form/fty_alnum.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_cursor.c +#libform-$(CONFIG_LP_PDCURSES) += form/fty_ipv4.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_link.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_arg.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_move.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_def.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_type.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_max.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_ftlink.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_ftchoice.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_info.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_user.c +#libform-$(CONFIG_LP_PDCURSES) += form/fty_num.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_sub.c +libform-$(CONFIG_LP_PDCURSES) += form/fty_enum.c +libform-$(CONFIG_LP_PDCURSES) += form/frm_data.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_opts.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_attr.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_dup.c +libform-$(CONFIG_LP_PDCURSES) += form/fld_just.c diff --git a/payloads/libpayload/curses/keyboard.c b/payloads/libpayload/curses/keyboard.c index 9648dde..927e06f 100644 --- a/payloads/libpayload/curses/keyboard.c +++ b/payloads/libpayload/curses/keyboard.c @@ -45,7 +45,7 @@ static int _halfdelay = 0; /* ============== Serial ==================== */ -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE /* We treat serial like a vt100 terminal. For now we do the cooking in here, but we should probably eventually pass it to dedicated vt100 code */ @@ -146,12 +146,12 @@ static int cook_serial(unsigned char ch) static int curses_getchar(int _delay) { -#if defined(CONFIG_USB_HID) || defined(CONFIG_PC_KEYBOARD) || defined(CONFIG_SERIAL_CONSOLE) +#if defined(CONFIG_LP_USB_HID) || defined(CONFIG_LP_PC_KEYBOARD) || defined(CONFIG_LP_SERIAL_CONSOLE) unsigned short c; #endif do { -#ifdef CONFIG_USB_HID +#ifdef CONFIG_LP_USB_HID usb_poll(); if ((curses_flags & F_ENABLE_CONSOLE) && usbhid_havechar()) { @@ -159,7 +159,7 @@ static int curses_getchar(int _delay) if (c != 0) return c; } #endif -#ifdef CONFIG_PC_KEYBOARD +#ifdef CONFIG_LP_PC_KEYBOARD if ((curses_flags & F_ENABLE_CONSOLE) && keyboard_havechar()) { c = keyboard_getchar(); @@ -167,7 +167,7 @@ static int curses_getchar(int _delay) } #endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if ((curses_flags & F_ENABLE_SERIAL) && serial_havechar()) { c = serial_getchar(); @@ -225,7 +225,7 @@ int nocbreak(void) return 0; } -#ifdef CONFIG_VGA_VIDEO_CONSOLE +#ifdef CONFIG_LP_VGA_VIDEO_CONSOLE void curses_enable_vga(int state) { if (state) @@ -243,7 +243,7 @@ void curses_enable_vga(int state) { } int curses_vga_enabled(void) { return 0; } #endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE void curses_enable_serial(int state) { if (state) diff --git a/payloads/libpayload/curses/local.h b/payloads/libpayload/curses/local.h index b7c459d..73fb005 100644 --- a/payloads/libpayload/curses/local.h +++ b/payloads/libpayload/curses/local.h @@ -70,13 +70,13 @@ /* Flags used to determine what output methods are available */ -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE #define F_ENABLE_CONSOLE 0x01 #else #define F_ENABLE_CONSOLE 0x00 #endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE #define F_ENABLE_SERIAL 0x02 #else #define F_ENABLE_SERIAL 0x00 diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c b/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c index ab73831..308370e 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c @@ -66,8 +66,8 @@ chtype fallback_acs_map[128] = '|', '<', '>', '*', '!', 'f', 'o', ' ', }; -#ifdef CONFIG_SERIAL_CONSOLE -#ifdef CONFIG_SERIAL_ACS_FALLBACK +#ifdef CONFIG_LP_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_ACS_FALLBACK chtype serial_acs_map[128]; #else /* See acsc of vt100. */ @@ -93,7 +93,7 @@ chtype serial_acs_map[128] = #endif #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE /* See acsc of linux. */ chtype console_acs_map[128] = { @@ -122,10 +122,10 @@ void PDC_gotoyx(int row, int col) { PDC_LOG(("PDC_gotoyx() - called: row %d col %d\n", row, col)); -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE serial_set_cursor(col, row); #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE video_console_set_cursor(col, row); #endif } @@ -139,7 +139,7 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp) PDC_LOG(("PDC_transform_line() - called: line %d, len %d, curses_flags %d\n", lineno, len, curses_flags)); -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE int serial_is_bold = 0; int serial_is_reverse = 0; int serial_is_altcharset = 0; @@ -157,7 +157,7 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp) { ch = srcp[j]; attr = ch; -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) { if (attr & A_BOLD) { if (!serial_is_bold) { @@ -222,7 +222,7 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp) } #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE unsigned char c = pdc_atrtab[srcp[j] >> PDC_ATTR_SHIFT]; if (curses_flags & F_ENABLE_CONSOLE) { diff --git a/payloads/libpayload/curses/pdcurses-backend/pdckbd.c b/payloads/libpayload/curses/pdcurses-backend/pdckbd.c index 49b80c7..d1061b2 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdckbd.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdckbd.c @@ -5,7 +5,7 @@ unsigned long pdc_key_modifiers = 0L; -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE /* We treat serial like a vt100 terminal. For now we do the cooking in here, but we should probably eventually pass it to dedicated vt100 code */ @@ -108,7 +108,7 @@ void PDC_set_keyboard_binary(bool on) bool PDC_check_key(void) { -#ifdef CONFIG_USB_HID +#ifdef CONFIG_LP_USB_HID usb_poll(); if ((curses_flags & F_ENABLE_CONSOLE) && usbhid_havechar()) { @@ -116,14 +116,14 @@ bool PDC_check_key(void) } #endif -#ifdef CONFIG_PC_KEYBOARD +#ifdef CONFIG_LP_PC_KEYBOARD if ((curses_flags & F_ENABLE_CONSOLE) && keyboard_havechar()) { return TRUE; } #endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if ((curses_flags & F_ENABLE_SERIAL) && serial_havechar()) { return TRUE; @@ -139,7 +139,7 @@ int PDC_get_key(void) { int c = 0; -#ifdef CONFIG_USB_HID +#ifdef CONFIG_LP_USB_HID usb_poll(); if ((curses_flags & F_ENABLE_CONSOLE) && usbhid_havechar()) { @@ -147,14 +147,14 @@ int PDC_get_key(void) } #endif -#ifdef CONFIG_PC_KEYBOARD +#ifdef CONFIG_LP_PC_KEYBOARD if ((curses_flags & F_ENABLE_CONSOLE) && keyboard_havechar() && (c==0)) { c = keyboard_getchar(); } #endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if ((curses_flags & F_ENABLE_SERIAL) && serial_havechar() && (c==0)) { c = cook_serial(serial_getchar()); diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c index e741b15..c4922ec 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c @@ -72,7 +72,7 @@ int PDC_scr_open(int argc, char **argv) SP->lines = PDC_get_rows(); SP->cols = PDC_get_columns(); -#ifdef CONFIG_SPEAKER +#ifdef CONFIG_LP_SPEAKER SP->audible = TRUE; #endif diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c index d016063..b2997a1 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c @@ -13,12 +13,12 @@ int PDC_curs_set(int visibility) ret_vis = SP->visibility; SP->visibility = visibility; -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) { serial_cursor_enable(visibility); } #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE if (curses_flags & F_ENABLE_CONSOLE) { video_console_cursor_enable(visibility); } diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcutil.c b/payloads/libpayload/curses/pdcurses-backend/pdcutil.c index 030f462..c40e2ed 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcutil.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcutil.c @@ -11,7 +11,7 @@ void PDC_beep(void) { PDC_LOG(("PDC_beep() - called\n")); -#ifdef CONFIG_SPEAKER +#ifdef CONFIG_LP_SPEAKER speaker_tone(1760, 500); /* 1760 == note A6 */ #endif } diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c index fe6e7de..d5bf23f 100644 --- a/payloads/libpayload/curses/tinycurses.c +++ b/payloads/libpayload/curses/tinycurses.c @@ -111,8 +111,8 @@ chtype fallback_acs_map[128] = '|', '<', '>', '*', '!', 'f', 'o', ' ', }; -#ifdef CONFIG_SERIAL_CONSOLE -#ifdef CONFIG_SERIAL_ACS_FALLBACK +#ifdef CONFIG_LP_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_ACS_FALLBACK chtype serial_acs_map[128]; #else /* See acsc of vt100. */ @@ -138,7 +138,7 @@ chtype serial_acs_map[128] = #endif #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE /* See acsc of linux. */ chtype console_acs_map[128] = { @@ -191,7 +191,7 @@ NCURSES_CH_T _nc_render(WINDOW *win, NCURSES_CH_T ch) int beep(void) { /* TODO: Flash the screen if beeping fails? */ -#ifdef CONFIG_SPEAKER +#ifdef CONFIG_LP_SPEAKER speaker_tone(1760, 500); /* 1760 == note A6 */ #endif return OK; @@ -202,12 +202,12 @@ int cbreak(void) { /* TODO */ return 0; } // int color_content(short color, short *r, short *g, short *b) {} int curs_set(int on) { -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) { serial_cursor_enable(on); } #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE if (curses_flags & F_ENABLE_CONSOLE) { video_console_cursor_enable(on); } @@ -315,12 +315,12 @@ WINDOW *initscr(void) for (i = 0; i < 128; i++) acs_map[i] = (chtype) i | A_ALTCHARSET; -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) { serial_clear(); } #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE if (curses_flags & F_ENABLE_CONSOLE) { /* Clear the screen and kill the cursor */ @@ -719,7 +719,7 @@ int whline(WINDOW *win, chtype ch, int n) (((c) & 0x4400) >> 2) | ((c) & 0xAA00) | (((c) & 0x1100) << 2) int wnoutrefresh(WINDOW *win) { -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE // FIXME. int serial_is_bold = 0; int serial_is_reverse = 0; @@ -732,7 +732,7 @@ int wnoutrefresh(WINDOW *win) int x, y; chtype ch; -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE serial_end_bold(); serial_end_altcharset(); #endif @@ -744,7 +744,7 @@ int wnoutrefresh(WINDOW *win) /* Position the serial cursor */ -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) serial_set_cursor(win->_begy + y, win->_begx + win->_line[y].firstchar); @@ -753,7 +753,7 @@ int wnoutrefresh(WINDOW *win) for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) { attr_t attr = win->_line[y].text[x].attr; -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) { ch = win->_line[y].text[x].chars[0]; @@ -819,7 +819,7 @@ int wnoutrefresh(WINDOW *win) } #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE unsigned int c = ((int)color_pairs[PAIR_NUMBER(attr)]) << 8; @@ -860,12 +860,12 @@ int wnoutrefresh(WINDOW *win) win->_line[y].lastchar = _NOCHANGE; } -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE if (curses_flags & F_ENABLE_SERIAL) serial_set_cursor(win->_begy + win->_cury, win->_begx + win->_curx); #endif -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE if (curses_flags & F_ENABLE_CONSOLE) video_console_set_cursor(win->_begx + win->_curx, win->_begy + win->_cury); #endif diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 901c77e..b31e341 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -29,65 +29,65 @@ ## SUCH DAMAGE. ## -libc-$(CONFIG_PCI) += pci.c +libc-$(CONFIG_LP_PCI) += pci.c -libc-$(CONFIG_SPEAKER) += speaker.c +libc-$(CONFIG_LP_SPEAKER) += speaker.c -libc-$(CONFIG_X86_SERIAL_CONSOLE) += serial.c +libc-$(CONFIG_LP_X86_SERIAL_CONSOLE) += serial.c -libc-$(CONFIG_PC_KEYBOARD) += keyboard.c +libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c -libc-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.c +libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c -libc-$(CONFIG_NVRAM) += nvram.c -libc-$(CONFIG_NVRAM) += options.c +libc-$(CONFIG_LP_NVRAM) += nvram.c +libc-$(CONFIG_LP_NVRAM) += options.c # Video console drivers -libc-$(CONFIG_VIDEO_CONSOLE) += video/video.c -libc-$(CONFIG_VGA_VIDEO_CONSOLE) += video/vga.c +libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c +libc-$(CONFIG_LP_VGA_VIDEO_CONSOLE) += video/vga.c # Geode LX console drivers -libc-$(CONFIG_GEODELX_VIDEO_CONSOLE) += video/geodelx.c -libc-$(CONFIG_GEODELX_VIDEO_CONSOLE) += video/font8x16.c +libc-$(CONFIG_LP_GEODELX_VIDEO_CONSOLE) += video/geodelx.c +libc-$(CONFIG_LP_GEODELX_VIDEO_CONSOLE) += video/font8x16.c # coreboot generic framebuffer driver libc-$(CONFIG_COREBOOT_VIDEO_CONSOLE) += video/corebootfb.c libc-$(CONFIG_COREBOOT_VIDEO_CONSOLE) += video/font8x16.c # AHCI/ATAPI driver -libc-$(CONFIG_STORAGE) += storage/storage.c -libc-$(CONFIG_STORAGE_AHCI) += storage/ahci.c -libc-$(CONFIG_STORAGE_AHCI) += storage/ahci_common.c -ifeq ($(CONFIG_STORAGE_ATA),y) -libc-$(CONFIG_STORAGE_ATA) += storage/ata.c -libc-$(CONFIG_STORAGE_ATA) += storage/ahci_ata.c +libc-$(CONFIG_LP_STORAGE) += storage/storage.c +libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c +libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci_common.c +ifeq ($(CONFIG_LP_STORAGE_ATA),y) +libc-$(CONFIG_LP_STORAGE_ATA) += storage/ata.c +libc-$(CONFIG_LP_STORAGE_ATA) += storage/ahci_ata.c endif -ifeq ($(CONFIG_STORAGE_ATAPI),y) -libc-$(CONFIG_STORAGE_ATAPI) += storage/atapi.c -libc-$(CONFIG_STORAGE_ATAPI) += storage/ahci_atapi.c +ifeq ($(CONFIG_LP_STORAGE_ATAPI),y) +libc-$(CONFIG_LP_STORAGE_ATAPI) += storage/atapi.c +libc-$(CONFIG_LP_STORAGE_ATAPI) += storage/ahci_atapi.c endif # USB stack -libc-$(CONFIG_USB) += usb/usbinit.c -libc-$(CONFIG_USB) += usb/usb.c -libc-$(CONFIG_USB) += usb/usb_dev.c -libc-$(CONFIG_USB) += usb/quirks.c -libc-$(CONFIG_USB_GEN_HUB) += usb/generic_hub.c -libc-$(CONFIG_USB_HUB) += usb/usbhub.c -libc-$(CONFIG_USB_UHCI) += usb/uhci.c -libc-$(CONFIG_USB_UHCI) += usb/uhci_rh.c -libc-$(CONFIG_USB_OHCI) += usb/ohci.c -libc-$(CONFIG_USB_OHCI) += usb/ohci_rh.c -libc-$(CONFIG_USB_EHCI) += usb/ehci.c -libc-$(CONFIG_USB_EHCI) += usb/ehci_rh.c -libc-$(CONFIG_USB_XHCI) += usb/xhci.c -libc-$(CONFIG_USB_XHCI) += usb/xhci_debug.c -libc-$(CONFIG_USB_XHCI) += usb/xhci_devconf.c -libc-$(CONFIG_USB_XHCI) += usb/xhci_events.c -libc-$(CONFIG_USB_XHCI) += usb/xhci_commands.c -libc-$(CONFIG_USB_XHCI) += usb/xhci_rh.c -libc-$(CONFIG_USB_HID) += usb/usbhid.c -libc-$(CONFIG_USB_MSC) += usb/usbmsc.c +libc-$(CONFIG_LP_USB) += usb/usbinit.c +libc-$(CONFIG_LP_USB) += usb/usb.c +libc-$(CONFIG_LP_USB) += usb/usb_dev.c +libc-$(CONFIG_LP_USB) += usb/quirks.c +libc-$(CONFIG_LP_USB_GEN_HUB) += usb/generic_hub.c +libc-$(CONFIG_LP_USB_HUB) += usb/usbhub.c +libc-$(CONFIG_LP_USB_UHCI) += usb/uhci.c +libc-$(CONFIG_LP_USB_UHCI) += usb/uhci_rh.c +libc-$(CONFIG_LP_USB_OHCI) += usb/ohci.c +libc-$(CONFIG_LP_USB_OHCI) += usb/ohci_rh.c +libc-$(CONFIG_LP_USB_EHCI) += usb/ehci.c +libc-$(CONFIG_LP_USB_EHCI) += usb/ehci_rh.c +libc-$(CONFIG_LP_USB_XHCI) += usb/xhci.c +libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_debug.c +libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_devconf.c +libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_events.c +libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_commands.c +libc-$(CONFIG_LP_USB_XHCI) += usb/xhci_rh.c +libc-$(CONFIG_LP_USB_HID) += usb/usbhid.c +libc-$(CONFIG_LP_USB_MSC) += usb/usbmsc.c # used by both USB HID and keyboard libc-y += hid.c diff --git a/payloads/libpayload/drivers/keyboard.c b/payloads/libpayload/drivers/keyboard.c index ddedbd3..8525a3e 100644 --- a/payloads/libpayload/drivers/keyboard.c +++ b/payloads/libpayload/drivers/keyboard.c @@ -41,7 +41,7 @@ struct layout_maps { static struct layout_maps *map; static struct layout_maps keyboard_layouts[] = { -#ifdef CONFIG_PC_KEYBOARD_LAYOUT_US +#ifdef CONFIG_LP_PC_KEYBOARD_LAYOUT_US { .country = "us", .map = { { /* No modifier */ 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, @@ -97,7 +97,7 @@ static struct layout_maps keyboard_layouts[] = { } }}, #endif -#ifdef CONFIG_PC_KEYBOARD_LAYOUT_DE +#ifdef CONFIG_LP_PC_KEYBOARD_LAYOUT_DE { .country = "de", .map = { { /* No modifier */ 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index 86ff670..a046c8e 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -60,7 +60,7 @@ * doesn't try to do this on its own. */ #define RTC_PORT_STANDARD 0x70 -#ifdef CONFIG_RTC_PORT_EXTENDED_VIA +#ifdef CONFIG_LP_RTC_PORT_EXTENDED_VIA #define RTC_PORT_EXTENDED 0x74 #else #define RTC_PORT_EXTENDED 0x72 diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c index 0d2964b..92782a0 100644 --- a/payloads/libpayload/drivers/serial.c +++ b/payloads/libpayload/drivers/serial.c @@ -39,7 +39,7 @@ static int serial_is_mem_mapped = 0; static uint8_t serial_read_reg(int offset) { -#ifdef CONFIG_IO_ADDRESS_SPACE +#ifdef CONFIG_LP_IO_ADDRESS_SPACE if (!serial_is_mem_mapped) return inb(IOBASE + offset); else @@ -49,7 +49,7 @@ static uint8_t serial_read_reg(int offset) static void serial_write_reg(uint8_t val, int offset) { -#ifdef CONFIG_IO_ADDRESS_SPACE +#ifdef CONFIG_LP_IO_ADDRESS_SPACE if (!serial_is_mem_mapped) outb(val, IOBASE + offset); else @@ -57,7 +57,7 @@ static void serial_write_reg(uint8_t val, int offset) writeb(val, MEMBASE + offset); } -#ifdef CONFIG_SERIAL_SET_SPEED +#ifdef CONFIG_LP_SERIAL_SET_SPEED static void serial_hardware_init(int speed, int word_bits, int parity, int stop_bits) { @@ -102,7 +102,7 @@ void serial_init(void) (lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED); if (!serial_is_mem_mapped) { -#ifdef CONFIG_IO_ADDRESS_SPACE +#ifdef CONFIG_LP_IO_ADDRESS_SPACE if ((inb(IOBASE + 0x05) == 0xFF) && (inb(IOBASE + 0x06) == 0xFF)) { printf("IO space mapped serial not present."); @@ -114,8 +114,8 @@ void serial_init(void) #endif } -#ifdef CONFIG_SERIAL_SET_SPEED - serial_hardware_init(CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); +#ifdef CONFIG_LP_SERIAL_SET_SPEED + serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); #endif console_add_input_driver(&consin); console_add_output_driver(&consout); diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 5711fa2..4eef843 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -152,7 +152,7 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, switch (port->signature) { case HBA_PxSIG_ATA: printf("ahci: ATA drive on port #%d.\n", portnum); -#ifdef CONFIG_STORAGE_ATA +#ifdef CONFIG_LP_STORAGE_ATA dev->ata_dev.identify = ahci_identify_device; dev->ata_dev.read_sectors = ahci_ata_read_sectors; return ata_attach_device(&dev->ata_dev, PORT_TYPE_SATA); @@ -160,7 +160,7 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl, break; case HBA_PxSIG_ATAPI: printf("ahci: ATAPI drive on port #%d.\n", portnum); -#ifdef CONFIG_STORAGE_ATAPI +#ifdef CONFIG_LP_STORAGE_ATAPI dev->atapi_dev.identify = ahci_identify_device; dev->atapi_dev.packet_read_cmd = ahci_packet_read_cmd; return atapi_attach_device(&dev->atapi_dev, PORT_TYPE_SATA); @@ -217,7 +217,7 @@ static void ahci_port_probe(hba_ctrl_t *const ctrl, ahci_dev_init(ctrl, port, portnum); } -#ifdef CONFIG_STORAGE_AHCI_ONLY_TESTED +#ifdef CONFIG_LP_STORAGE_AHCI_ONLY_TESTED static u32 working_controllers[] = { 0x8086 | 0x2929 << 16, /* Mobile ICH9 */ 0x8086 | 0x1e03 << 16, /* Mobile Panther Point PCH */ @@ -233,7 +233,7 @@ static void ahci_init_pci(pcidev_t dev) const u16 vendor = pci_read_config16(dev, 0x00); const u16 device = pci_read_config16(dev, 0x02); -#ifdef CONFIG_STORAGE_AHCI_ONLY_TESTED +#ifdef CONFIG_LP_STORAGE_AHCI_ONLY_TESTED const u32 vendor_device = pci_read_config32(dev, 0x0); for (i = 0; i < ARRAY_SIZE(working_controllers); ++i) if (vendor_device == working_controllers[i]) diff --git a/payloads/libpayload/drivers/storage/ata.c b/payloads/libpayload/drivers/storage/ata.c index e7d45fd..f1cf28f 100644 --- a/payloads/libpayload/drivers/storage/ata.c +++ b/payloads/libpayload/drivers/storage/ata.c @@ -212,7 +212,7 @@ int ata_attach_device(ata_dev_t *const dev, const storage_port_t port_type) ata_strncpy(model, id + 27, sizeof(model)); printf("ata: Identified %s [%s]\n", model, fw); -#ifdef CONFIG_STORAGE_64BIT_LBA +#ifdef CONFIG_LP_STORAGE_64BIT_LBA if (id[ATA_CMDS_AND_FEATURE_SETS + 1] & (1 << 10)) { printf("ata: Support for LBA-48 enabled.\n"); dev->read_cmd = ATA_READ_DMA_EXT; diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index ae60309..ccfd02c 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -28,7 +28,7 @@ */ #include <libpayload.h> -#ifdef CONFIG_STORAGE_AHCI +#ifdef CONFIG_LP_STORAGE_AHCI # include <storage/ahci.h> #endif #include <storage/storage.h> @@ -110,7 +110,7 @@ ssize_t storage_read_blocks512(const size_t dev_num, */ void storage_initialize(void) { -#ifdef CONFIG_STORAGE_AHCI +#ifdef CONFIG_LP_STORAGE_AHCI ahci_initialize(); #endif } diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 82802a7..b983701 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -805,7 +805,7 @@ ehci_init (unsigned long physical_bar) return controller; } -#ifdef CONFIG_USB_PCI +#ifdef CONFIG_LP_USB_PCI hci_t * ehci_pci_init (pcidev_t addr) { diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 9f15dd0..0683de3 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -251,7 +251,7 @@ ohci_init (unsigned long physical_bar) return controller; } -#ifdef CONFIG_USB_PCI +#ifdef CONFIG_LP_USB_PCI hci_t * ohci_pci_init (pcidev_t addr) { diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 47f8eb6..6b54dbb 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -464,7 +464,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) break; case hid_device: usb_debug ("HID\n"); -#ifdef CONFIG_USB_HID +#ifdef CONFIG_LP_USB_HID controller->devices[adr]->init = usb_hid_init; return adr; #else @@ -482,7 +482,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) break; case msc_device: usb_debug ("MSC\n"); -#ifdef CONFIG_USB_MSC +#ifdef CONFIG_LP_USB_MSC controller->devices[adr]->init = usb_msc_init; return adr; #else @@ -491,7 +491,7 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) break; case hub_device: usb_debug ("hub\n"); -#ifdef CONFIG_USB_HUB +#ifdef CONFIG_LP_USB_HUB controller->devices[adr]->init = usb_hub_init; return adr; #else diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index b8c04f1..51c3d46 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -138,7 +138,7 @@ struct layout_maps { static const struct layout_maps *map; static const struct layout_maps keyboard_layouts[] = { -// #ifdef CONFIG_PC_KEYBOARD_LAYOUT_US +// #ifdef CONFIG_LP_PC_KEYBOARD_LAYOUT_US { .country = "us", .map = { { /* No modifier */ -1, -1, -1, -1, 'a', 'b', 'c', 'd', diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index ca0bf76..90c31d7 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -36,7 +36,7 @@ #include "xhci.h" #include <usb/usbdisk.h> -#ifdef CONFIG_USB_PCI +#ifdef CONFIG_LP_USB_PCI /** * Initializes USB controller attached to PCI * @@ -71,7 +71,7 @@ static int usb_controller_initialize(int bus, int dev, int func) pciid >> 16, pciid & 0xFFFF, func); switch (prog_if) { case 0x00: -#ifdef CONFIG_USB_UHCI +#ifdef CONFIG_LP_USB_UHCI usb_debug("UHCI controller\n"); uhci_pci_init (pci_device); #else @@ -80,7 +80,7 @@ static int usb_controller_initialize(int bus, int dev, int func) break; case 0x10: -#ifdef CONFIG_USB_OHCI +#ifdef CONFIG_LP_USB_OHCI usb_debug("OHCI controller\n"); ohci_pci_init(pci_device); #else @@ -89,7 +89,7 @@ static int usb_controller_initialize(int bus, int dev, int func) break; case 0x20: -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_LP_USB_EHCI usb_debug("EHCI controller\n"); ehci_pci_init(pci_device); #else @@ -98,7 +98,7 @@ static int usb_controller_initialize(int bus, int dev, int func) break; case 0x30: -#ifdef CONFIG_USB_XHCI +#ifdef CONFIG_LP_USB_XHCI usb_debug("xHCI controller\n"); xhci_pci_init(pci_device); #else @@ -156,17 +156,17 @@ static void usb_scan_pci_bus(int bus) } #endif -#ifdef CONFIG_USB_MEMORY +#ifdef CONFIG_LP_USB_MEMORY static void usb_scan_memory(void) { -#ifdef CONFIG_USB_XHCI - xhci_init(CONFIG_USB_XHCI_BASE_ADDRESS); +#ifdef CONFIG_LP_USB_XHCI + xhci_init(CONFIG_LP_USB_XHCI_BASE_ADDRESS); #endif -#ifdef CONFIG_USB_EHCI - ehci_init(CONFIG_USB_EHCI_BASE_ADDRESS); +#ifdef CONFIG_LP_USB_EHCI + ehci_init(CONFIG_LP_USB_EHCI_BASE_ADDRESS); #endif -#ifdef CONFIG_USB_OHCI - ohci_init(CONFIG_USB_OHCI_BASE_ADDRESS); +#ifdef CONFIG_LP_USB_OHCI + ohci_init(CONFIG_LP_USB_OHCI_BASE_ADDRESS); #endif } #endif @@ -176,10 +176,10 @@ static void usb_scan_memory(void) */ int usb_initialize(void) { -#ifdef CONFIG_USB_PCI +#ifdef CONFIG_LP_USB_PCI usb_scan_pci_bus(0); #endif -#ifdef CONFIG_USB_MEMORY +#ifdef CONFIG_LP_USB_MEMORY usb_scan_memory(); #endif return 0; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 0bd54c7..2e9dd3b 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -297,7 +297,7 @@ _free_controller: return NULL; } -#ifdef CONFIG_USB_PCI +#ifdef CONFIG_LP_USB_PCI hci_t * xhci_pci_init (pcidev_t addr) { @@ -344,8 +344,8 @@ xhci_reinit (hci_t *controller) return; /* Enable all available slots */ - xhci->opreg->config = xhci->capreg->MaxSlots & CONFIG_MASK_MaxSlotsEn; - xhci->max_slots_en = xhci->capreg->MaxSlots & CONFIG_MASK_MaxSlotsEn; + xhci->opreg->config = xhci->capreg->MaxSlots & CONFIG_LP_MASK_MaxSlotsEn; + xhci->max_slots_en = xhci->capreg->MaxSlots & CONFIG_LP_MASK_MaxSlotsEn; /* Set DCBAA */ xhci->opreg->dcbaap_lo = virt_to_phys(xhci->dcbaa); diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 6f7893e..945c7f1 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -389,7 +389,7 @@ typedef struct xhci { u32 dcbaap_lo; u32 dcbaap_hi; u32 config; -#define CONFIG_MASK_MaxSlotsEn 0xff +#define CONFIG_LP_MASK_MaxSlotsEn 0xff u8 res3[0x3ff-0x3c+1]; struct { u32 portsc; diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c index b8fe5d9..ed47234 100644 --- a/payloads/libpayload/drivers/video/video.c +++ b/payloads/libpayload/drivers/video/video.c @@ -31,27 +31,27 @@ #include <libpayload.h> #include <video_console.h> -#ifdef CONFIG_GEODELX_VIDEO_CONSOLE +#ifdef CONFIG_LP_GEODELX_VIDEO_CONSOLE extern struct video_console geodelx_video_console; #endif -#ifdef CONFIG_COREBOOT_VIDEO_CONSOLE +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE extern struct video_console coreboot_video_console; #endif -#ifdef CONFIG_VGA_VIDEO_CONSOLE +#ifdef CONFIG_LP_VGA_VIDEO_CONSOLE extern struct video_console vga_video_console; #endif static struct video_console *console_list[] = { -#ifdef CONFIG_GEODELX_VIDEO_CONSOLE +#ifdef CONFIG_LP_GEODELX_VIDEO_CONSOLE &geodelx_video_console, #endif -#ifdef CONFIG_COREBOOT_VIDEO_CONSOLE +#ifdef CONFIG_LP_COREBOOT_VIDEO_CONSOLE &coreboot_video_console, #endif -#ifdef CONFIG_VGA_VIDEO_CONSOLE +#ifdef CONFIG_LP_VGA_VIDEO_CONSOLE &vga_video_console, #endif }; diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index f9d1fc3..d908d83 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -88,7 +88,7 @@ /** this is the master cbfs header - it needs to be located somewhere available to bootblock (to load romstage). Where it actually lives is up to coreboot. On x86, a pointer to this header will live at 0xFFFFFFFC. - For other platforms, you need to define CONFIG_CBFS_HEADER_ROM_OFFSET */ + For other platforms, you need to define CONFIG_LP_CBFS_HEADER_ROM_OFFSET */ struct cbfs_header { uint32_t magic; diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index d4ddb5d..ada6bc6 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -45,7 +45,7 @@ static inline uint64_t swap_bytes64(uint64_t in) /* Endian functions from glibc 2.9 / BSD "endian.h" */ -#if defined CONFIG_BIG_ENDIAN +#if defined CONFIG_LP_BIG_ENDIAN #define htobe16(in) (in) #define htobe32(in) (in) @@ -55,7 +55,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #define htole32(in) swap_bytes32(in) #define htole64(in) swap_bytes64(in) -#elif defined CONFIG_LITTLE_ENDIAN +#elif defined CONFIG_LP_LITTLE_ENDIAN #define htobe16(in) swap_bytes16(in) #define htobe32(in) swap_bytes32(in) diff --git a/payloads/libpayload/include/kconfig.h b/payloads/libpayload/include/kconfig.h index 3d7d768..adb3403 100644 --- a/payloads/libpayload/include/kconfig.h +++ b/payloads/libpayload/include/kconfig.h @@ -5,10 +5,10 @@ /* * Getting something that works in C and CPP for an arg that may or may - * not be defined is tricky. Here, if we have "#define CONFIG_BOOGER 1" + * not be defined is tricky. Here, if we have "#define CONFIG_LP_BOOGER 1" * we match on the placeholder define, insert the "0," for arg1 and generate * the triplet (0, 1, 0). Then the last step cherry picks the 2nd arg (a one). - * When CONFIG_BOOGER is not defined, we generate a (... 1, 0) pair, and when + * When CONFIG_LP_BOOGER is not defined, we generate a (... 1, 0) pair, and when * the last step cherry picks the 2nd arg, we get a zero. */ #define __ARG_PLACEHOLDER_1 0, diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 14f8a38..29b5629 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -56,7 +56,7 @@ #include <arch/virtual.h> #include <sysinfo.h> #include <pci.h> -#ifdef CONFIG_LAR +#ifdef CONFIG_LP_LAR #include <lar.h> #endif @@ -339,7 +339,7 @@ struct timeval { int gettimeofday(struct timeval *tv, void *tz); /** @} */ -#ifdef CONFIG_LAR +#ifdef CONFIG_LP_LAR /** * @defgroup lar LAR functions * @{ diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index cf37c80..92a13e3 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -36,7 +36,7 @@ * @defgroup malloc Memory allocation functions * @{ */ -#if defined(CONFIG_DEBUG_MALLOC) && !defined(IN_MALLOC_C) +#if defined(CONFIG_LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) #define free(p) \ ({ \ extern void print_malloc_map(void); \ diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h index ef61cd2..a3cebd9 100644 --- a/payloads/libpayload/include/storage/storage.h +++ b/payloads/libpayload/include/storage/storage.h @@ -34,7 +34,7 @@ #include <unistd.h> -#ifndef CONFIG_STORAGE_64BIT_LBA +#ifndef CONFIG_LP_STORAGE_64BIT_LBA typedef u32 lba_t; #else typedef u64 lba_t; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index e2ceffc..92b8dca 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -63,7 +63,7 @@ struct sysinfo_t { u32 cmos_range_start; u32 cmos_range_end; u32 cmos_checksum_location; -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS u32 vbnv_start; u32 vbnv_size; #endif @@ -83,7 +83,7 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS int num_gpios; struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; #endif @@ -93,14 +93,14 @@ struct sysinfo_t { struct cb_header *header; struct cb_mainboard *mainboard; -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_LP_CHROMEOS void *vboot_handoff; u32 vboot_handoff_size; void *vdat_addr; u32 vdat_size; #endif -#ifdef CONFIG_ARCH_X86 +#ifdef CONFIG_LP_ARCH_X86 int x86_rom_var_mtrr_index; #endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index edeb0d9..53f3c9b 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -28,14 +28,14 @@ ## SUCH DAMAGE. ## -libc-$(CONFIG_LIBC) += malloc.c printf.c console.c string.c -libc-$(CONFIG_LIBC) += memory.c ctype.c ipchecksum.c lib.c -libc-$(CONFIG_LIBC) += rand.c time.c exec.c -libc-$(CONFIG_LIBC) += readline.c getopt_long.c sysinfo.c -libc-$(CONFIG_LIBC) += args.c strings.c -libc-$(CONFIG_LIBC) += strlcpy.c -libc-$(CONFIG_LIBC) += qsort.c -libc-$(CONFIG_LIBC) += hexdump.c +libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c +libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c +libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c +libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c +libc-$(CONFIG_LP_LIBC) += args.c strings.c +libc-$(CONFIG_LP_LIBC) += strlcpy.c +libc-$(CONFIG_LP_LIBC) += qsort.c +libc-$(CONFIG_LP_LIBC) += hexdump.c # should be moved to coreboot directory -libc-$(CONFIG_LAR) += lar.c +libc-$(CONFIG_LP_LAR) += lar.c diff --git a/payloads/libpayload/libc/console.c b/payloads/libpayload/libc/console.c index 54844db..a362481 100644 --- a/payloads/libpayload/libc/console.c +++ b/payloads/libpayload/libc/console.c @@ -49,16 +49,16 @@ void console_add_input_driver(struct console_input_driver *in) void console_init(void) { -#ifdef CONFIG_VIDEO_CONSOLE +#ifdef CONFIG_LP_VIDEO_CONSOLE video_console_init(); #endif -#ifdef CONFIG_SERIAL_CONSOLE +#ifdef CONFIG_LP_SERIAL_CONSOLE serial_init(); #endif -#ifdef CONFIG_PC_KEYBOARD +#ifdef CONFIG_LP_PC_KEYBOARD keyboard_init(); #endif -#ifdef CONFIG_CBMEM_CONSOLE +#ifdef CONFIG_LP_CBMEM_CONSOLE cbmem_console_init(); #endif } @@ -94,7 +94,7 @@ int puts(const char *s) int havekey(void) { -#ifdef CONFIG_USB +#ifdef CONFIG_LP_USB usb_poll(); #endif struct console_input_driver *in; @@ -111,7 +111,7 @@ int havekey(void) int getchar(void) { while (1) { -#ifdef CONFIG_USB +#ifdef CONFIG_LP_USB usb_poll(); #endif struct console_input_driver *in; diff --git a/payloads/libpayload/libc/exec.c b/payloads/libpayload/libc/exec.c index 13a1e5a..4360bd5 100644 --- a/payloads/libpayload/libc/exec.c +++ b/payloads/libpayload/libc/exec.c @@ -30,7 +30,7 @@ #include <libpayload-config.h> #include <libpayload.h> -#ifdef CONFIG_ARCH_X86 +#ifdef CONFIG_LP_ARCH_X86 extern void i386_do_exec(long addr, int argc, char **argv, int *ret); #endif @@ -46,7 +46,7 @@ int exec(long addr, int argc, char **argv) { int val = -1; -#ifdef CONFIG_ARCH_X86 +#ifdef CONFIG_LP_ARCH_X86 i386_do_exec(addr, argc, argv, &val); #endif return val; diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 851ef57..f022f73 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -68,7 +68,7 @@ typedef u64 hdrtype_t; static int free_aligned(void* addr); void print_malloc_map(void); -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC static int heap_initialized = 0; static int minimal_free = 0; #endif @@ -77,7 +77,7 @@ static void setup(hdrtype_t volatile *start, int size) { *start = FREE_BLOCK(size); -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC heap_initialized = 1; minimal_free = size; #endif @@ -282,7 +282,7 @@ static struct align_region_t* align_regions = 0; static struct align_region_t *allocate_region(int alignment, int num_elements) { struct align_region_t *new_region; -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC printf("%s(old align_regions=%p, alignment=%u, num_elements=%u)\n", __func__, align_regions, alignment, num_elements); #endif @@ -344,7 +344,7 @@ look_further: { if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align)) { -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC printf(" found memalign region. %x free, %x required\n", reg->free, (size + align - 1)/align); #endif break; @@ -353,12 +353,12 @@ look_further: } if (reg == 0) { -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC printf(" need to allocate a new memalign region\n"); #endif /* get align regions */ reg = allocate_region(align, (size<1024)?(1024/align):(((size-1)/align)+1)); -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC printf(" ... returned %p\n", align_regions); #endif } @@ -394,7 +394,7 @@ look_further: } /* This is for debugging purposes. */ -#ifdef CONFIG_DEBUG_MALLOC +#ifdef CONFIG_LP_DEBUG_MALLOC void print_malloc_map(void) { void *ptr = hstart; diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 7b6bf47..ec1c85c 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -34,7 +34,7 @@ #include <libpayload-config.h> #include <libpayload.h> -#ifdef CONFIG_ARCH_X86 +#ifdef CONFIG_LP_ARCH_X86 #include <arch/rdtsc.h> #endif @@ -70,7 +70,7 @@ static void update_clock(void) } } -#ifdef CONFIG_NVRAM +#ifdef CONFIG_LP_NVRAM static unsigned int day_of_year(int mon, int day, int year) { diff --git a/payloads/libpayload/libcbfs/Makefile.inc b/payloads/libpayload/libcbfs/Makefile.inc index 0d3e1ec..72f6b79 100644 --- a/payloads/libpayload/libcbfs/Makefile.inc +++ b/payloads/libpayload/libcbfs/Makefile.inc @@ -27,6 +27,6 @@ ## SUCH DAMAGE. ## -libcbfs-$(CONFIG_CBFS) += cbfs.c -libcbfs-$(CONFIG_CBFS) += ram_media.c +libcbfs-$(CONFIG_LP_CBFS) += cbfs.c +libcbfs-$(CONFIG_LP_CBFS) += ram_media.c diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index c143abb..5610555 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -31,7 +31,7 @@ #ifdef LIBPAYLOAD # include <libpayload-config.h> -# ifdef CONFIG_LZMA +# ifdef CONFIG_LP_LZMA # include <lzma.h> # define CBFS_CORE_WITH_LZMA # endif @@ -55,15 +55,15 @@ # include <console/console.h> # define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) # define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -# if CONFIG_DEBUG_CBFS +# if CONFIG_LP_DEBUG_CBFS # define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) # else # define DEBUG(x...) # endif #endif -#if defined(CONFIG_CBFS_HEADER_ROM_OFFSET) && (CONFIG_CBFS_HEADER_ROM_OFFSET) -# define CBFS_HEADER_ROM_ADDRESS (CONFIG_CBFS_HEADER_ROM_OFFSET) +#if defined(CONFIG_LP_CBFS_HEADER_ROM_OFFSET) && (CONFIG_LP_CBFS_HEADER_ROM_OFFSET) +# define CBFS_HEADER_ROM_ADDRESS (CONFIG_LP_CBFS_HEADER_ROM_OFFSET) #else /* ugly hack: this assumes that "media" exists in the scope where the macro is used. */ diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index d14cf61..a3d3e02 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -69,7 +69,7 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) media->open(media); DEBUG("CBFS_HEADER_ROM_ADDRESS: 0x%x/0x%x\n", CBFS_HEADER_ROM_ADDRESS, - CONFIG_ROM_SIZE); + CONFIG_LP_ROM_SIZE); header = media->map(media, CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); media->close(media); @@ -118,7 +118,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) // TODO Add a "size" in CBFS header for a platform independent way to // determine the end of CBFS data. -#if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 +#if defined(CONFIG_LP_ARCH_X86) && CONFIG_LP_ARCH_X86 romsize -= htonl(header->bootblocksize); #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); diff --git a/payloads/libpayload/liblzma/Makefile.inc b/payloads/libpayload/liblzma/Makefile.inc index 2dd4a2d..7df45f2 100644 --- a/payloads/libpayload/liblzma/Makefile.inc +++ b/payloads/libpayload/liblzma/Makefile.inc @@ -27,5 +27,5 @@ ## SUCH DAMAGE. ## -liblzma-$(CONFIG_LZMA) += lzma.c +liblzma-$(CONFIG_LP_LZMA) += lzma.c diff --git a/payloads/libpayload/tests/libpayload-config.h b/payloads/libpayload/tests/libpayload-config.h index 6fe99a9..68995b8 100644 --- a/payloads/libpayload/tests/libpayload-config.h +++ b/payloads/libpayload/tests/libpayload-config.h @@ -4,27 +4,27 @@ * Sat Mar 9 10:22:45 2013 */ #define AUTOCONF_INCLUDED -#define CONFIG_SPEAKER 1 -#define CONFIG_STORAGE 1 -#define CONFIG_LIBC 1 -#define CONFIG_CBFS 1 -#define CONFIG_VGA_VIDEO_CONSOLE 1 -#define CONFIG_SERIAL_CONSOLE 1 -#define CONFIG_PC_KEYBOARD 1 -#define CONFIG_ARCH_X86 1 -#define CONFIG_STORAGE_ATA 1 -#define CONFIG_ARCH_SPECIFIC_OPTIONS 1 -#define CONFIG_STORAGE_AHCI_ONLY_TESTED 1 -#define CONFIG_X86_SERIAL_CONSOLE 1 -#define CONFIG_PDCURSES 1 -#define CONFIG_NVRAM 1 -#define CONFIG_PC_KEYBOARD_LAYOUT_US 1 -#define CONFIG_STORAGE_AHCI 1 -#define CONFIG_MULTIBOOT 1 -#define CONFIG_SERIAL_IOBASE 0x3f8 -#define CONFIG_CURSES 1 -#define CONFIG_CBMEM_CONSOLE 1 -#define CONFIG_LITTLE_ENDIAN 1 -#define CONFIG_PCI 1 -#define CONFIG_STORAGE_ATAPI 1 -#define CONFIG_VIDEO_CONSOLE 1 +#define CONFIG_LP_SPEAKER 1 +#define CONFIG_LP_STORAGE 1 +#define CONFIG_LP_LIBC 1 +#define CONFIG_LP_CBFS 1 +#define CONFIG_LP_VGA_VIDEO_CONSOLE 1 +#define CONFIG_LP_SERIAL_CONSOLE 1 +#define CONFIG_LP_PC_KEYBOARD 1 +#define CONFIG_LP_ARCH_X86 1 +#define CONFIG_LP_STORAGE_ATA 1 +#define CONFIG_LP_ARCH_SPECIFIC_OPTIONS 1 +#define CONFIG_LP_STORAGE_AHCI_ONLY_TESTED 1 +#define CONFIG_LP_X86_SERIAL_CONSOLE 1 +#define CONFIG_LP_PDCURSES 1 +#define CONFIG_LP_NVRAM 1 +#define CONFIG_LP_PC_KEYBOARD_LAYOUT_US 1 +#define CONFIG_LP_STORAGE_AHCI 1 +#define CONFIG_LP_MULTIBOOT 1 +#define CONFIG_LP_SERIAL_IOBASE 0x3f8 +#define CONFIG_LP_CURSES 1 +#define CONFIG_LP_CBMEM_CONSOLE 1 +#define CONFIG_LP_LITTLE_ENDIAN 1 +#define CONFIG_LP_PCI 1 +#define CONFIG_LP_STORAGE_ATAPI 1 +#define CONFIG_LP_VIDEO_CONSOLE 1 diff --git a/payloads/libpayload/util/kconfig/confdata.c b/payloads/libpayload/util/kconfig/confdata.c index b1f31d8..a28b930 100644 --- a/payloads/libpayload/util/kconfig/confdata.c +++ b/payloads/libpayload/util/kconfig/confdata.c @@ -219,22 +219,22 @@ load: sym = NULL; switch (line[0]) { case '#': - if (memcmp(line + 2, "CONFIG_", 7)) + if (memcmp(line + 2, "CONFIG_LP_", 10)) continue; - p = strchr(line + 9, ' '); + p = strchr(line + 12, ' '); if (!p) continue; *p++ = 0; if (strncmp(p, "is not set", 10)) continue; if (def == S_DEF_USER) { - sym = sym_find(line + 9); + sym = sym_find(line + 12); if (!sym) { - conf_warning("trying to assign nonexistent symbol %s", line + 9); + conf_warning("trying to assign nonexistent symbol %s", line + 12); break; } } else { - sym = sym_lookup(line + 9, 0); + sym = sym_lookup(line + 12, 0); if (sym->type == S_UNKNOWN) sym->type = S_BOOLEAN; } @@ -252,11 +252,11 @@ load: } break; case 'C': - if (memcmp(line, "CONFIG_", 7)) { + if (memcmp(line, "CONFIG_LP_", 10)) { conf_warning("unexpected data"); continue; } - p = strchr(line + 7, '='); + p = strchr(line + 10, '='); if (!p) continue; *p++ = 0; @@ -267,13 +267,13 @@ load: *p2 = 0; } if (def == S_DEF_USER) { - sym = sym_find(line + 7); + sym = sym_find(line + 10); if (!sym) { - conf_warning("trying to assign nonexistent symbol %s", line + 7); + conf_warning("trying to assign nonexistent symbol %s", line + 10); break; } } else { - sym = sym_lookup(line + 7, 0); + sym = sym_lookup(line + 10, 0); if (sym->type == S_UNKNOWN) sym->type = S_OTHER; } @@ -489,19 +489,19 @@ int conf_write(const char *name) case S_TRISTATE: switch (sym_get_tristate_value(sym)) { case no: - fprintf(out, "# CONFIG_%s is not set\n", sym->name); + fprintf(out, "# CONFIG_LP_%s is not set\n", sym->name); break; case mod: - fprintf(out, "CONFIG_%s=m\n", sym->name); + fprintf(out, "CONFIG_LP_%s=m\n", sym->name); break; case yes: - fprintf(out, "CONFIG_%s=y\n", sym->name); + fprintf(out, "CONFIG_LP_%s=y\n", sym->name); break; } break; case S_STRING: str = sym_get_string_value(sym); - fprintf(out, "CONFIG_%s=\"", sym->name); + fprintf(out, "CONFIG_LP_%s=\"", sym->name); while (1) { l = strcspn(str, "\"\\"); if (l) { @@ -517,12 +517,12 @@ int conf_write(const char *name) case S_HEX: str = sym_get_string_value(sym); if (str[0] != '0' || (str[1] != 'x' && str[1] != 'X')) { - fprintf(out, "CONFIG_%s=%s\n", sym->name, str); + fprintf(out, "CONFIG_LP_%s=%s\n", sym->name, str); break; } case S_INT: str = sym_get_string_value(sym); - fprintf(out, "CONFIG_%s=%s\n", sym->name, str); + fprintf(out, "CONFIG_LP_%s=%s\n", sym->name, str); break; } } @@ -730,19 +730,19 @@ int conf_write_autoconf(void) case no: break; case mod: - fprintf(out, "CONFIG_%s=m\n", sym->name); - fprintf(out_h, "#define CONFIG_%s_MODULE 1\n", sym->name); + fprintf(out, "CONFIG_LP_%s=m\n", sym->name); + fprintf(out_h, "#define CONFIG_LP_%s_MODULE 1\n", sym->name); break; case yes: - fprintf(out, "CONFIG_%s=y\n", sym->name); - fprintf(out_h, "#define CONFIG_%s 1\n", sym->name); + fprintf(out, "CONFIG_LP_%s=y\n", sym->name); + fprintf(out_h, "#define CONFIG_LP_%s 1\n", sym->name); break; } break; case S_STRING: str = sym_get_string_value(sym); - fprintf(out, "CONFIG_%s=\"", sym->name); - fprintf(out_h, "#define CONFIG_%s \"", sym->name); + fprintf(out, "CONFIG_LP_%s=\"", sym->name); + fprintf(out_h, "#define CONFIG_LP_%s \"", sym->name); while (1) { l = strcspn(str, "\"\\"); if (l) { @@ -762,14 +762,14 @@ int conf_write_autoconf(void) case S_HEX: str = sym_get_string_value(sym); if (str[0] != '0' || (str[1] != 'x' && str[1] != 'X')) { - fprintf(out, "CONFIG_%s=%s\n", sym->name, str); - fprintf(out_h, "#define CONFIG_%s 0x%s\n", sym->name, str); + fprintf(out, "CONFIG_LP_%s=%s\n", sym->name, str); + fprintf(out_h, "#define CONFIG_LP_%s 0x%s\n", sym->name, str); break; } case S_INT: str = sym_get_string_value(sym); - fprintf(out, "CONFIG_%s=%s\n", sym->name, str); - fprintf(out_h, "#define CONFIG_%s %s\n", sym->name, str); + fprintf(out, "CONFIG_LP_%s=%s\n", sym->name, str); + fprintf(out_h, "#define CONFIG_LP_%s %s\n", sym->name, str); break; default: break; diff --git a/payloads/libpayload/util/kconfig/mconf.c b/payloads/libpayload/util/kconfig/mconf.c index 5e93a30..fcebc50 100644 --- a/payloads/libpayload/util/kconfig/mconf.c +++ b/payloads/libpayload/util/kconfig/mconf.c @@ -232,7 +232,7 @@ save_config_help[] = N_( "leave this blank.\n"), search_help[] = N_( "\n" - "Search for CONFIG_ symbols and display their relations.\n" + "Search for CONFIG_LP_ symbols and display their relations.\n" "Regular expressions are allowed.\n" "Example: search for \"^FOO\"\n" "Result:\n" @@ -249,7 +249,7 @@ search_help[] = N_( "Selected by: BAR\n" "-----------------------------------------------------------------\n" "o The line 'Prompt:' shows the text used in the menu structure for\n" - " this CONFIG_ symbol\n" + " this CONFIG_LP_ symbol\n" "o The 'Defined at' line tell at what file / line number the symbol\n" " is defined\n" "o The 'Depends on:' line tell what symbols needs to be defined for\n" @@ -265,9 +265,9 @@ search_help[] = N_( "Only relevant lines are shown.\n" "\n\n" "Search examples:\n" - "Examples: USB => find all CONFIG_ symbols containing USB\n" - " ^USB => find all CONFIG_ symbols starting with USB\n" - " USB$ => find all CONFIG_ symbols ending with USB\n" + "Examples: USB => find all CONFIG_LP_ symbols containing USB\n" + " ^USB => find all CONFIG_LP_ symbols starting with USB\n" + " USB$ => find all CONFIG_LP_ symbols ending with USB\n" "\n"); static int indent; @@ -388,8 +388,8 @@ static void search_conf(void) again: dialog_clear(); dres = dialog_inputbox(_("Search Configuration Parameter"), - _("Enter CONFIG_ (sub)string to search for " - "(with or without \"CONFIG\")"), + _("Enter CONFIG_LP_ (sub)string to search for " + "(with or without \"CONFIG_LP\")"), 10, 75, ""); switch (dres) { case 0: @@ -401,9 +401,9 @@ again: return; } - /* strip CONFIG_ if necessary */ + /* strip CONFIG_LP_ if necessary */ dialog_input = dialog_input_result; - if (strncasecmp(dialog_input_result, "CONFIG_", 7) == 0) + if (strncasecmp(dialog_input_result, "CONFIG_LP_", 10) == 0) dialog_input += 7; sym_arr = sym_re_search(dialog_input); @@ -704,7 +704,7 @@ static void show_help(struct menu *menu) if (menu_has_help(menu)) { if (sym->name) { - str_printf(&help, "CONFIG_%s:\n\n", sym->name); + str_printf(&help, "CONFIG_LP_%s:\n\n", sym->name); str_append(&help, _(menu_get_help(menu))); str_append(&help, "\n"); }

1 0

New patch to review for coreboot: 15c0e90 coreboot classes: Add dynamic classes to coreboot
by Furquan Shaikh 31 Jul '14

31 Jul '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6426 -gerrit commit 15c0e90856fcde83725e2ce063269b2e5d42338c Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 31 09:28:55 2014 -0700 coreboot classes: Add dynamic classes to coreboot Provide functionality to create dynamic classes based on program name and architecture for which the program needs to be compiled/linked. define_class takes program_name and arch as its arguments and adds the program_name to classes-y to create dynamic class. Also, compiler toolset is created for the specified arch. All the files for this program can then be added to program_name-y += .. Ensure that define_class is called before any files are added to the class. Check subdirs-y for order of directory inclusion. One such example of dynamic class is rmodules. Multiple rmodules can be used which need to be compiled for different architectures. With dynamic classes, this is possible. Change-Id: Ie143ed6f79ced5f58c200394cff89b006bc9b342 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 6 +++++- src/arch/x86/Makefile.inc | 3 +-- src/arch/x86/lib/Makefile.inc | 6 +++--- src/cpu/x86/Makefile.inc | 10 +++++----- src/cpu/x86/smm/Makefile.inc | 4 ++-- src/lib/Makefile.inc | 9 ++++++--- src/vendorcode/google/chromeos/Makefile.inc | 14 +++++++------- toolchain.inc | 12 ++++++++++++ 8 files changed, 41 insertions(+), 23 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 42ed707..559ca04 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -75,7 +75,11 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode rmodules +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode + +# Add dynamic classes for rmodules +$(foreach supported_arch,$(ARCH_SUPPORTED), \ + $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) ####################################################################### # Helper functions for ramstage postprocess diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2e92d89..45ad7ce 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -308,10 +308,9 @@ endif ramstage-libs ?= -$(eval $(call create_class_compiler,rmodules,x86_32)) ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE))) +$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 0a3a575..22306f1 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -30,8 +30,8 @@ smm-y += memcpy.c smm-y += memmove.c smm-y += rom_media.c -rmodules-y += memset.c -rmodules-y += memcpy.c -rmodules-y += memmove.c +rmodules_x86_32-y += memset.c +rmodules_x86_32-y += memcpy.c +rmodules_x86_32-y += memmove.c endif # CONFIG_ARCH_RAMSTAGE_X86_32 \ No newline at end of file diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index b27fac0..a05c723 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -13,16 +13,16 @@ SIPI_DOTO=$(SIPI_ELF:.elf=.o) ifeq ($(CONFIG_PARALLEL_MP),y) ramstage-srcs += $(SIPI_BIN) endif -rmodules-$(CONFIG_PARALLEL_MP) += sipi_vector.S +rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S -$(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules.o - $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ $^ +$(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o + $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32)) $(SIPI_BIN): $(SIPI_RMOD) $(OBJCOPY_ramstage) -O binary $< $@ $(SIPI_BIN).ramstage.o: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY_ramstage) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) + cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index ff4023b..b179d7e 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -39,7 +39,7 @@ $(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs) $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ # Link the SMM stub module with a 0-byte heap. -$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0)) +$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_32)) $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ @@ -54,7 +54,7 @@ $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME_smm) $(CC_smm) $(CFLAGS_smm) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME_smm) -Wl,--end-group -$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE))) +$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod $(OBJCOPY_smm) -O binary $< $@ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5298bbe..76ab3dd 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -24,7 +24,9 @@ bootblock-y += memcmp.c romstage-y += memchr.c romstage-y += memcmp.c -rmodules-y += memcmp.c +$(foreach arch,$(ARCH_SUPPORTED),\ + $(eval rmodules_$(arch)-y += memcmp.c)) + romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c #romstage-y += lzmadecode.c @@ -106,12 +108,13 @@ RMODULE_LDFLAGS := -nostartfiles -Wl,--emit-relocs -Wl,-z,defs -Wl,-Bsymbolic - # (1) the object name to link # (2) the dependencies # (3) heap size of the relocatable module +# (4) arch for which the rmodules are to be linked # It will create the necessary Make rules to create a rmodule. The resulting # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(obj)/ldoptions $$(RMODTOOL) - $$(CC_rmodules) $$(CFLAGS_rmodules) $$(RMODULE_LDFLAGS) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--start-group $(strip $(2)) $$(LIBGCC_FILE_NAME_rmodules) -Wl,--end-group - $$(NM_rmodules) -n $$@ > $$(basename $$(a)).map + $$(CC_rmodules_$(4)) $$(CFLAGS_rmodules_$(4)) $$(RMODULE_LDFLAGS) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--start-group $(strip $(2)) $$(LIBGCC_FILE_NAME_rmodules_$(4)) -Wl,--end-group + $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map $(strip $(1)).rmod: $(strip $(1)) $$(RMODTOOL) -i $$^ -o $$@ diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 9bd5091..ccde71a 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) romstage-y += vboot_handoff.c ramstage-y += vboot_handoff.c romstage-y += vboot_loader.c -rmodules-y += vboot_wrapper.c +rmodules_$(ARCH-romstage-y)-y += vboot_wrapper.c VB_LIB = $(obj)/external/vboot_reference/vboot_fw.a # Currently, vboot comes into picture only during the romstage, thus @@ -55,10 +55,10 @@ VBOOT_STUB = $(VBOOT_STUB_ELF).rmod VBOOT_STUB_DOTO = $(VBOOT_STUB_ELF:.elf=.o) # Dependency for the vboot rmodules. Ordering matters. -VBOOT_STUB_DEPS += $(obj)/vendorcode/google/chromeos/vboot_wrapper.rmodules.o -VBOOT_STUB_DEPS += $(obj)/lib/memcmp.rmodules.o -VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memset.rmodules.o -VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memcpy.rmodules.o +VBOOT_STUB_DEPS += $(obj)/vendorcode/google/chromeos/vboot_wrapper.rmodules_$(ARCH-romstage-y).o +VBOOT_STUB_DEPS += $(obj)/lib/memcmp.rmodules_$(ARCH-romstage-y).o +VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memset.rmodules_$(ARCH-romstage-y).o +VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memcpy.rmodules_$(ARCH-romstage-y).o VBOOT_STUB_DEPS += $(VB_LIB) # Remove the '-include' option since that will break vboot's build and ensure # vboot_reference can get to coreboot's include files. @@ -66,10 +66,10 @@ VBOOT_CFLAGS += $(patsubst -I%,-I../%,$(filter-out -include $(src)/include/kconf VBOOT_CFLAGS += -DVBOOT_DEBUG $(VBOOT_STUB_DOTO): $(VBOOT_STUB_DEPS) - $(CC_romstage) $(CFLAGS_romstage) -nostdlib -r -o $@ $^ + $(CC_rmodules_$(ARCH-romstage-y)) $(CFLAGS_rmodules_$(ARCH-romstage-y)) -nostdlib -r -o $@ $^ # Link the vbootstub module with a 64KiB-byte heap. -$(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000)) +$(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000,$(ARCH-romstage-y))) # Build vboot library without the default includes from coreboot proper. $(VB_LIB): diff --git a/toolchain.inc b/toolchain.inc index 842473b..3b9c5d2 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -98,6 +98,18 @@ CPPFLAGS_$(1) += $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) LIBGCC_FILE_NAME_$(1) = $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name)) endef +# define_class: Allows defining any program as dynamic class and compiler tool +# set for the same based on the architecture for which the program is to be +# compiled +# @1: program (class name) +# @2: architecture for which the program needs to be compiled +# IMP: Ensure that define_class is called before any .c or .S files are added to +# the class of the program. Check subdirs-y for order of subdirectory inclusions +define define_class +classes-y += $(1) +$(eval $(call create_class_compiler,$(1),$(2))) +endef + # initialize standard toolchain (CC,AS and others) for give stage # @1 : stage for which the toolchain is to be initialized init_standard_toolchain = \

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Patch merged into coreboot/master: 0d7f133 payloads/external/SeaBIOS: Use coreboot’s serial console settings
by gerrit＠coreboot.org 31 Jul '14

31 Jul '14

the following patch was just integrated into master: commit 0d7f133c38673af2dae06988d418606d7f5628ac Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:33:49 2014 -0600 payloads/external/SeaBIOS: Use coreboot’s serial console settings Set up the serial console on SeaBIOS to match coreboot's settings. Previously, we were just forcing it on, and setting it to 0x3f8. Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6363 for details. -gerrit

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coreboot-gerrit July 2014