coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

1 participants
861 discussions

New patch to review for coreboot: df37d98 lenovo/t520/mainboard.c: add #include h8.h
by HAOUAS Elyes 31 Jul '14

31 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6424 -gerrit commit df37d989f87b824ffe217677183d7a044a762808 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 31 10:39:57 2014 +0200 lenovo/t520/mainboard.c: add #include h8.h Change-Id: I5ac6608ebf78f2d48bc7f68bce9eae7a2be82332 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t520/mainboard.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index c213791..d374e7e 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -39,6 +39,7 @@ #include <device/pci.h> #include <cbfs.h> #include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> void mainboard_suspend_resume(void) { @@ -182,8 +183,6 @@ static void mainboard_enable(device_t dev) verb_setup(); } -void h8_mainboard_init_dock (void); - void h8_mainboard_init_dock (void) { return;

1 0

Patch set updated for coreboot: 98fdd6e northbridge/intel: Various fsp_rangeley northbridge cleanups
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6420 -gerrit commit 98fdd6e6c2ec6115200c048d273bd811b6be3715 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 09:07:38 2014 +1000 northbridge/intel: Various fsp_rangeley northbridge cleanups Alphabetize headers and some minor style clean ups, nothing significant to see here. Introduced in: 2963ae7 northbridge/intel: Add fsp_rangeley northbridge support Change-Id: I13f2c46aa2bcedb9d1c66c485bf48ed7bc95d9c7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_rangeley/acpi.c | 13 +++++++------ src/northbridge/intel/fsp_rangeley/chip.h | 2 +- .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 16 +++++++--------- .../intel/fsp_rangeley/fsp/chipset_fsp_util.h | 10 +++++----- src/northbridge/intel/fsp_rangeley/northbridge.c | 17 +++++++++-------- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_rangeley/port_access.c | 5 +++-- src/northbridge/intel/fsp_rangeley/raminit.c | 7 ++++--- src/northbridge/intel/fsp_rangeley/udelay.c | 4 ++-- 9 files changed, 39 insertions(+), 37 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 895f5b4..7be183e 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -21,15 +21,16 @@ * MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <arch/io.h> #include <arch/acpi.h> +#include <arch/io.h> +#include <build.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <build.h> +#include <string.h> +#include <types.h> + #include "northbridge.h" unsigned long acpi_fill_mcfg(unsigned long current) @@ -56,7 +57,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; /* 256MB ECAM range */ - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); max_buses = 256; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 24609a1..0d19aa7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -60,4 +60,4 @@ struct northbridge_intel_fsp_rangeley_config { uint8_t Bifurcation; }; -#endif +#endif /* _FSP_RANGELEY_CHIP_H_ */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index bd196a5..ac45abf 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -17,25 +17,23 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <cpu/x86/stack.h> -#include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/stack.h> #include <device/device.h> -#include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp/fsp_util.h> -#include <fspvpd.h> #include <fspbootmode.h> +#include <fspvpd.h> +#include <string.h> +#include <southbridge/intel/fsp_rangeley/pci_devs.h> +#include <types.h> #include <reset.h> + #include "../chip.h" #ifdef __PRE_RAM__ #include <southbridge/intel/fsp_rangeley/romstage.h> -#endif - -#ifdef __PRE_RAM__ /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..09c4c38 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -20,13 +20,13 @@ #ifndef CHIPSET_FSP_UTIL_H #define CHIPSET_FSP_UTIL_H -#include <fsptypes.h> -#include <fspfv.h> -#include <fspffs.h> #include <fspapi.h> +#include <fspffs.h> +#include <fspfv.h> +#include <fsphob.h> #include <fspplatform.h> +#include <fsptypes.h> #include <fspinfoheader.h> -#include <fsphob.h> #include <fspvpd.h> #define FSP_RESERVE_MEMORY_SIZE 0x200000 @@ -42,7 +42,7 @@ } /* - *The FSP Image ID is different for each platform's FSP and + * The FSP Image ID is different for each platform's FSP and * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 98c0b9c..397c53f 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -19,24 +19,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> -#include <stdint.h> -#include <delay.h> -#include <cpu/intel/fsp_model_406dx/model_406dx.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> +#include <cpu/intel/fsp_model_406dx/model_406dx.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/fsp/fsp_util.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> -#include <cpu/cpu.h> -#include <cbmem.h> + #include "chip.h" #include "northbridge.h" -#include <drivers/intel/fsp/fsp_util.h> -#include <cpu/x86/lapic.h> static int bridge_revision_id = -1; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 855a056..6d40380 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index 508630e..83667f0 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -22,11 +22,12 @@ #define __PRE_RAM__ // Use simple device model for this file even in ramstage #endif -#include <stdint.h> #include <arch/io.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> +#include <stdint.h> + #include "northbridge.h" /* diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..3dbdfb9 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -18,13 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <device/pci_def.h> -#include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> +#include <string.h> + +#include "northbridge.h" unsigned long get_top_of_ram(void) { diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index bdd9f78..a921609 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <delay.h> -#include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <delay.h> +#include <stdint.h> /** * Intel Rangeley CPUs always run the TSC at BCLK=100MHz

1 0

New patch to review for coreboot: e71a527 vendorcode/intel/fsp/rangeley/include: Missing 'fsptypes.h'
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6423 -gerrit commit e71a527de48f3ce7d606111023148d40e4e20207 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 17:56:51 2014 +1000 vendorcode/intel/fsp/rangeley/include: Missing 'fsptypes.h' Without the inclusion of 'fsptypes.h' the order of inclusion becomes tentative. Change-Id: I6360e4ebac6c414c380a19ef69d39d658ea203bd Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/intel/fsp/rangeley/include/fspapi.h | 4 +++- src/vendorcode/intel/fsp/rangeley/include/fspffs.h | 3 ++- src/vendorcode/intel/fsp/rangeley/include/fspfv.h | 2 ++ src/vendorcode/intel/fsp/rangeley/include/fsphob.h | 2 ++ 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspapi.h b/src/vendorcode/intel/fsp/rangeley/include/fspapi.h index 5378b2a..5009246 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fspapi.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspapi.h @@ -31,6 +31,8 @@ are permitted provided that the following conditions are met: #ifndef _FSP_API_H_ #define _FSP_API_H_ +#include <fsptypes.h> + #pragma pack(1) typedef VOID (* CONTINUATION_PROC)(EFI_STATUS Status, VOID *HobListPtr); @@ -62,4 +64,4 @@ typedef struct { typedef FSP_STATUS (FSPAPI *FSP_FSP_INIT) (FSP_INIT_PARAMS *FspInitParamPtr); typedef FSP_STATUS (FSPAPI *FSP_NOTFY_PHASE) (NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr); -#endif \ No newline at end of file +#endif /* _FSP_API_H_ */ diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspffs.h b/src/vendorcode/intel/fsp/rangeley/include/fspffs.h index 7a7c367..9e8244d 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fspffs.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspffs.h @@ -28,10 +28,11 @@ are permitted provided that the following conditions are met: **/ - #ifndef __PI_FIRMWARE_FILE_H__ #define __PI_FIRMWARE_FILE_H__ +#include <fsptypes.h> + #pragma pack(1) /// /// Used to verify the integrity of the file. diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspfv.h b/src/vendorcode/intel/fsp/rangeley/include/fspfv.h index 75d17fa..9688cf4 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fspfv.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspfv.h @@ -31,6 +31,8 @@ are permitted provided that the following conditions are met: #ifndef __PI_FIRMWAREVOLUME_H__ #define __PI_FIRMWAREVOLUME_H__ +#include <fsptypes.h> + /// /// EFI_FV_FILE_ATTRIBUTES /// diff --git a/src/vendorcode/intel/fsp/rangeley/include/fsphob.h b/src/vendorcode/intel/fsp/rangeley/include/fsphob.h index a9c0bce..0f743b5 100644 --- a/src/vendorcode/intel/fsp/rangeley/include/fsphob.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fsphob.h @@ -31,6 +31,8 @@ are permitted provided that the following conditions are met: #ifndef __PI_HOB_H__ #define __PI_HOB_H__ +#include <fsptypes.h> + // // HobType of EFI_HOB_GENERIC_HEADER. //

1 0

Patch set updated for coreboot: d3b61e2 northbridge/intel: Trivial fsp_rangeley northbridge cleanups
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6420 -gerrit commit d3b61e2fdf4ad6d79a086295296063894de6afb9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 09:07:38 2014 +1000 northbridge/intel: Trivial fsp_rangeley northbridge cleanups Alphabetize headers and some minor style clean ups, nothing significant to see here. Introduced in: 2963ae7 northbridge/intel: Add fsp_rangeley northbridge support Change-Id: I13f2c46aa2bcedb9d1c66c485bf48ed7bc95d9c7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_rangeley/acpi.c | 13 +++++++------ src/northbridge/intel/fsp_rangeley/chip.h | 2 +- .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 18 ++++++++---------- .../intel/fsp_rangeley/fsp/chipset_fsp_util.h | 10 +++++----- src/northbridge/intel/fsp_rangeley/northbridge.c | 17 +++++++++-------- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_rangeley/port_access.c | 5 +++-- src/northbridge/intel/fsp_rangeley/raminit.c | 7 ++++--- src/northbridge/intel/fsp_rangeley/udelay.c | 4 ++-- 9 files changed, 40 insertions(+), 38 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 895f5b4..7be183e 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -21,15 +21,16 @@ * MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <arch/io.h> #include <arch/acpi.h> +#include <arch/io.h> +#include <build.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <build.h> +#include <string.h> +#include <types.h> + #include "northbridge.h" unsigned long acpi_fill_mcfg(unsigned long current) @@ -56,7 +57,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; /* 256MB ECAM range */ - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); max_buses = 256; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 24609a1..0d19aa7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -60,4 +60,4 @@ struct northbridge_intel_fsp_rangeley_config { uint8_t Bifurcation; }; -#endif +#endif /* _FSP_RANGELEY_CHIP_H_ */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index bd196a5..b95446f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -17,23 +17,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <cpu/x86/stack.h> -#include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/stack.h> #include <device/device.h> -#include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp/fsp_util.h> -#include <fspvpd.h> #include <fspbootmode.h> +#include <fspvpd.h> +#include <string.h> +#include <southbridge/intel/fsp_rangeley/romstage.h> +#include <southbridge/intel/fsp_rangeley/pci_devs.h> +#include <types.h> #include <reset.h> -#include "../chip.h" -#ifdef __PRE_RAM__ -#include <southbridge/intel/fsp_rangeley/romstage.h> -#endif +#include "../chip.h" #ifdef __PRE_RAM__ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..09c4c38 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -20,13 +20,13 @@ #ifndef CHIPSET_FSP_UTIL_H #define CHIPSET_FSP_UTIL_H -#include <fsptypes.h> -#include <fspfv.h> -#include <fspffs.h> #include <fspapi.h> +#include <fspffs.h> +#include <fspfv.h> +#include <fsphob.h> #include <fspplatform.h> +#include <fsptypes.h> #include <fspinfoheader.h> -#include <fsphob.h> #include <fspvpd.h> #define FSP_RESERVE_MEMORY_SIZE 0x200000 @@ -42,7 +42,7 @@ } /* - *The FSP Image ID is different for each platform's FSP and + * The FSP Image ID is different for each platform's FSP and * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 98c0b9c..397c53f 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -19,24 +19,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> -#include <stdint.h> -#include <delay.h> -#include <cpu/intel/fsp_model_406dx/model_406dx.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> +#include <cpu/intel/fsp_model_406dx/model_406dx.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/fsp/fsp_util.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> -#include <cpu/cpu.h> -#include <cbmem.h> + #include "chip.h" #include "northbridge.h" -#include <drivers/intel/fsp/fsp_util.h> -#include <cpu/x86/lapic.h> static int bridge_revision_id = -1; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 855a056..6d40380 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index 508630e..83667f0 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -22,11 +22,12 @@ #define __PRE_RAM__ // Use simple device model for this file even in ramstage #endif -#include <stdint.h> #include <arch/io.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> +#include <stdint.h> + #include "northbridge.h" /* diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..3dbdfb9 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -18,13 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <device/pci_def.h> -#include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> +#include <string.h> + +#include "northbridge.h" unsigned long get_top_of_ram(void) { diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index bdd9f78..a921609 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <delay.h> -#include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <delay.h> +#include <stdint.h> /** * Intel Rangeley CPUs always run the TSC at BCLK=100MHz

1 0

Patch set updated for coreboot: 067c6bf drivers: Add missing header guards
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6421 -gerrit commit 067c6bf6081b78116ae86e486341cdd5efc741ab Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 16:58:49 2014 +1000 drivers: Add missing header guards Change-Id: I1fe93ac080aea75229fa55eb828149b6c0d3a52d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/ati/ragexl/atyfb.h | 5 +++++ src/drivers/i2c/at24rf08c/lenovo.h | 5 +++++ src/drivers/i2c/rtd2132/chip.h | 5 +++++ src/drivers/i2c/w83793/chip.h | 5 +++++ src/drivers/ics/954309/chip.h | 5 +++++ src/drivers/intel/gma/edid.h | 5 +++++ src/drivers/intel/gma/i915.h | 5 +++++ src/drivers/lenovo/lenovo.h | 5 +++++ src/drivers/lenovo/wacom.c | 3 ++- src/drivers/net/ns8390.h | 5 +++++ src/drivers/xpowers/axp209/axp209.h | 5 +++++ 11 files changed, 52 insertions(+), 1 deletion(-) diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h index 94f31fe..c0e57be 100644 --- a/src/drivers/ati/ragexl/atyfb.h +++ b/src/drivers/ati/ragexl/atyfb.h @@ -2,6 +2,9 @@ * ATI Frame Buffer Device Driver Core Definitions */ +#ifndef AFYFB_H +#define AFYFB_H + #define PLL_CRTC_DECODE 0 #define EINVAL -1 @@ -405,3 +408,5 @@ extern const struct display_switch fbcon_aty16; extern const struct display_switch fbcon_aty24; extern const struct display_switch fbcon_aty32; #endif + +#endif /* AFYFB_H */ diff --git a/src/drivers/i2c/at24rf08c/lenovo.h b/src/drivers/i2c/at24rf08c/lenovo.h index 6824eb6..aaf9387 100644 --- a/src/drivers/i2c/at24rf08c/lenovo.h +++ b/src/drivers/i2c/at24rf08c/lenovo.h @@ -1 +1,6 @@ +#ifndef AT24RF08C_LENOVO_H +#define AT24RF08C_LENOVO_H + const char *lenovo_mainboard_partnumber(void); + +#endif /* AT24RF08C_LENOVO_H */ diff --git a/src/drivers/i2c/rtd2132/chip.h b/src/drivers/i2c/rtd2132/chip.h index 2cf0827..f6f2b70 100644 --- a/src/drivers/i2c/rtd2132/chip.h +++ b/src/drivers/i2c/rtd2132/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + struct drivers_i2c_rtd2132_config { /* Panel Power Sequencing. All units in ms. */ u16 t1; /* Delay from panel Vcc enable to LVDS output enable. */ @@ -49,3 +52,5 @@ struct drivers_i2c_rtd2132_config { */ u8 sscg_percent; }; + +#endif /* CHIP_H */ diff --git a/src/drivers/i2c/w83793/chip.h b/src/drivers/i2c/w83793/chip.h index 65a50bb..c1d1bd9 100644 --- a/src/drivers/i2c/w83793/chip.h +++ b/src/drivers/i2c/w83793/chip.h @@ -1,3 +1,6 @@ +#ifndef CHIP_H +#define CHIP_H + struct drivers_i2c_w83793_config { u8 mfc; u8 fanin; @@ -17,3 +20,5 @@ struct drivers_i2c_w83793_config { u8 tr1_fan_select; u8 tr2_fan_select; }; + +#endif /* CHIP_H */ diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h index 66cc2c6..807185a 100644 --- a/src/drivers/ics/954309/chip.h +++ b/src/drivers/ics/954309/chip.h @@ -19,6 +19,9 @@ * MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + struct drivers_ics_954309_config { u8 reg0; u8 reg1; @@ -33,3 +36,5 @@ struct drivers_ics_954309_config { u8 reg10; u8 reg11; }; + +#endif /* CHIP_H */ diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h index cb54b46..8f090b1 100644 --- a/src/drivers/intel/gma/edid.h +++ b/src/drivers/intel/gma/edid.h @@ -1 +1,6 @@ +#ifndef INTEL_GMA_EDID_H +#define INTEL_GMA_EDID_H + void intel_gmbus_read_edid(u32 gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size); + +#endif /* INTEL_GMA_EDID_H */ diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 9ef3abd..9e441ee 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I915_H +#define I915_H + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -262,3 +265,5 @@ int intel_dp_get_lane_count(struct intel_dp *intel_dp, int intel_dp_get_lane_align_status(struct intel_dp *intel_dp, u8 *recv); + +#endif /* I915_H */ diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..2e1fe77 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,8 @@ +#ifndef LENOVO_H +#define LENOVO_H + int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, int have_dock_serial); + +#endif /* LENOVO_H */ diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 33a2879..2fab858 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -26,8 +26,9 @@ #include <device/device.h> #include <device/pnp.h> #include <string.h> +#include <drivers/i2c/at24rf08c/lenovo.h> + #include "lenovo.h" -#include "drivers/i2c/at24rf08c/lenovo.h" static const char tablet_numbers[][5] = { /* X60t. */ diff --git a/src/drivers/net/ns8390.h b/src/drivers/net/ns8390.h index 23a68a0..d30b54d 100644 --- a/src/drivers/net/ns8390.h +++ b/src/drivers/net/ns8390.h @@ -1,3 +1,6 @@ +#ifndef NS8390_H +#define NS8390_H + /************************************************************************** ETHERBOOT - BOOTP/TFTP Bootstrap Program @@ -107,3 +110,5 @@ struct ringbuffer { * c-basic-offset: 8 * End: */ + +#endif /* NS8390_H */ diff --git a/src/drivers/xpowers/axp209/axp209.h b/src/drivers/xpowers/axp209/axp209.h index c9cdd7e..960e3d2 100644 --- a/src/drivers/xpowers/axp209/axp209.h +++ b/src/drivers/xpowers/axp209/axp209.h @@ -5,6 +5,9 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ +#ifndef AXP209_H +#define AXP209_H + #include <types.h> #include "chip.h" @@ -18,3 +21,5 @@ enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_voltages(u8 bus, const struct drivers_xpowers_axp209_config *cfg); + +#endif /* AXP209_H */

1 0

Patch set updated for coreboot: ca5c91f soc: Add missing header guards
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6422 -gerrit commit ca5c91f947b8d4b6b60f5d0afbb9977e039f2f4e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 17:05:19 2014 +1000 soc: Add missing header guards Change-Id: I0729b754226346df1e3be5f20c3a4b34cc76ed72 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/acpi/irq_helper.h | 5 +++++ src/soc/intel/baytrail/baytrail/nvs.h | 5 +++++ src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/src/soc/intel/baytrail/acpi/irq_helper.h b/src/soc/intel/baytrail/acpi/irq_helper.h index b19895b..01718ba 100644 --- a/src/soc/intel/baytrail/acpi/irq_helper.h +++ b/src/soc/intel/baytrail/acpi/irq_helper.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef IRQ_HELPER_H +#define IRQ_HELPER_H + #undef PCI_DEV_PIRQ_ROUTES #undef ACPI_DEV_APIC_IRQ #undef PCI_DEV_PIRQ_ROUTE @@ -46,3 +49,5 @@ /* Include the mainboard irq route definition. */ #include "irqroute.h" + +#endif /* IRQ_HELPER_H */ diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index dbf72e2..6549409 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + #include <vendorcode/google/chromeos/gnvs.h> #include <baytrail/device_nvs.h> @@ -70,3 +73,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h index e3a23d8..350d5dc 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h +++ b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef IRQ_HELPER_H +#define IRQ_HELPER_H + /* * This file will use arch/x86/acpi/irqroute.asl and mainboard/irqroute.h * to generate the ACPI IRQ routing for the mainboard being compiled. @@ -53,3 +56,5 @@ /* Include the mainboard irq route definition */ #include "irqroute.h" + +#endif /* IRQ_HELPER_H */

1 0

New patch to review for coreboot: d44d436 soc: Add missing header guards
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6422 -gerrit commit d44d43666c3f0828c9dc3df81da0568dbca59d94 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 17:05:19 2014 +1000 soc: Add missing header guards Change-Id: I0729b754226346df1e3be5f20c3a4b34cc76ed72 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/acpi/irq_helper.h | 5 +++++ src/soc/intel/baytrail/baytrail/nvs.h | 5 +++++ src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/src/soc/intel/baytrail/acpi/irq_helper.h b/src/soc/intel/baytrail/acpi/irq_helper.h index b19895b..01718ba 100644 --- a/src/soc/intel/baytrail/acpi/irq_helper.h +++ b/src/soc/intel/baytrail/acpi/irq_helper.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef IRQ_HELPER_H +#define IRQ_HELPER_H + #undef PCI_DEV_PIRQ_ROUTES #undef ACPI_DEV_APIC_IRQ #undef PCI_DEV_PIRQ_ROUTE @@ -46,3 +49,5 @@ /* Include the mainboard irq route definition. */ #include "irqroute.h" + +#endif /* IRQ_HELPER_H */ diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index dbf72e2..6549409 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NVS_H +#define NVS_H + #include <vendorcode/google/chromeos/gnvs.h> #include <baytrail/device_nvs.h> @@ -70,3 +73,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* NVS_H */ diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h index e3a23d8..350d5dc 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h +++ b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef IRQ_HELPER_H +#define IRQ_HELPER_H + /* * This file will use arch/x86/acpi/irqroute.asl and mainboard/irqroute.h * to generate the ACPI IRQ routing for the mainboard being compiled. @@ -53,3 +56,5 @@ /* Include the mainboard irq route definition */ #include "irqroute.h" + +#endif /* IRQ_HELPER_H */

1 0

New patch to review for coreboot: 8a7d20a drivers: Add missing header guards
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6421 -gerrit commit 8a7d20a981e6ea8899d687bc339f9febffe786fc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 16:58:49 2014 +1000 drivers: Add missing header guards Change-Id: I1fe93ac080aea75229fa55eb828149b6c0d3a52d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/ati/ragexl/atyfb.h | 5 +++++ src/drivers/i2c/at24rf08c/lenovo.h | 5 +++++ src/drivers/i2c/rtd2132/chip.h | 5 +++++ src/drivers/i2c/w83793/chip.h | 5 +++++ src/drivers/ics/954309/chip.h | 5 +++++ src/drivers/intel/gma/edid.h | 5 +++++ src/drivers/intel/gma/i915.h | 5 +++++ src/drivers/lenovo/lenovo.h | 5 +++++ src/drivers/net/ns8390.h | 5 +++++ src/drivers/xpowers/axp209/axp209.h | 5 +++++ 10 files changed, 50 insertions(+) diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h index 94f31fe..c0e57be 100644 --- a/src/drivers/ati/ragexl/atyfb.h +++ b/src/drivers/ati/ragexl/atyfb.h @@ -2,6 +2,9 @@ * ATI Frame Buffer Device Driver Core Definitions */ +#ifndef AFYFB_H +#define AFYFB_H + #define PLL_CRTC_DECODE 0 #define EINVAL -1 @@ -405,3 +408,5 @@ extern const struct display_switch fbcon_aty16; extern const struct display_switch fbcon_aty24; extern const struct display_switch fbcon_aty32; #endif + +#endif /* AFYFB_H */ diff --git a/src/drivers/i2c/at24rf08c/lenovo.h b/src/drivers/i2c/at24rf08c/lenovo.h index 6824eb6..8d1a813 100644 --- a/src/drivers/i2c/at24rf08c/lenovo.h +++ b/src/drivers/i2c/at24rf08c/lenovo.h @@ -1 +1,6 @@ +#ifndef LENOVO_H +#define LENOVO_H + const char *lenovo_mainboard_partnumber(void); + +#endif /* LENOVO_H */ diff --git a/src/drivers/i2c/rtd2132/chip.h b/src/drivers/i2c/rtd2132/chip.h index 2cf0827..f6f2b70 100644 --- a/src/drivers/i2c/rtd2132/chip.h +++ b/src/drivers/i2c/rtd2132/chip.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + struct drivers_i2c_rtd2132_config { /* Panel Power Sequencing. All units in ms. */ u16 t1; /* Delay from panel Vcc enable to LVDS output enable. */ @@ -49,3 +52,5 @@ struct drivers_i2c_rtd2132_config { */ u8 sscg_percent; }; + +#endif /* CHIP_H */ diff --git a/src/drivers/i2c/w83793/chip.h b/src/drivers/i2c/w83793/chip.h index 65a50bb..c1d1bd9 100644 --- a/src/drivers/i2c/w83793/chip.h +++ b/src/drivers/i2c/w83793/chip.h @@ -1,3 +1,6 @@ +#ifndef CHIP_H +#define CHIP_H + struct drivers_i2c_w83793_config { u8 mfc; u8 fanin; @@ -17,3 +20,5 @@ struct drivers_i2c_w83793_config { u8 tr1_fan_select; u8 tr2_fan_select; }; + +#endif /* CHIP_H */ diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h index 66cc2c6..807185a 100644 --- a/src/drivers/ics/954309/chip.h +++ b/src/drivers/ics/954309/chip.h @@ -19,6 +19,9 @@ * MA 02110-1301 USA */ +#ifndef CHIP_H +#define CHIP_H + struct drivers_ics_954309_config { u8 reg0; u8 reg1; @@ -33,3 +36,5 @@ struct drivers_ics_954309_config { u8 reg10; u8 reg11; }; + +#endif /* CHIP_H */ diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h index cb54b46..52bf96c 100644 --- a/src/drivers/intel/gma/edid.h +++ b/src/drivers/intel/gma/edid.h @@ -1 +1,6 @@ +#ifndef EDID_H +#define EDID_H + void intel_gmbus_read_edid(u32 gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size); + +#endif /* EDID_H */ diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 9ef3abd..9e441ee 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef I915_H +#define I915_H + #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/drm_dp_helper.h> #include <edid.h> @@ -262,3 +265,5 @@ int intel_dp_get_lane_count(struct intel_dp *intel_dp, int intel_dp_get_lane_align_status(struct intel_dp *intel_dp, u8 *recv); + +#endif /* I915_H */ diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..2e1fe77 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,8 @@ +#ifndef LENOVO_H +#define LENOVO_H + int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, int have_dock_serial); + +#endif /* LENOVO_H */ diff --git a/src/drivers/net/ns8390.h b/src/drivers/net/ns8390.h index 23a68a0..d30b54d 100644 --- a/src/drivers/net/ns8390.h +++ b/src/drivers/net/ns8390.h @@ -1,3 +1,6 @@ +#ifndef NS8390_H +#define NS8390_H + /************************************************************************** ETHERBOOT - BOOTP/TFTP Bootstrap Program @@ -107,3 +110,5 @@ struct ringbuffer { * c-basic-offset: 8 * End: */ + +#endif /* NS8390_H */ diff --git a/src/drivers/xpowers/axp209/axp209.h b/src/drivers/xpowers/axp209/axp209.h index c9cdd7e..960e3d2 100644 --- a/src/drivers/xpowers/axp209/axp209.h +++ b/src/drivers/xpowers/axp209/axp209.h @@ -5,6 +5,9 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ +#ifndef AXP209_H +#define AXP209_H + #include <types.h> #include "chip.h" @@ -18,3 +21,5 @@ enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_voltages(u8 bus, const struct drivers_xpowers_axp209_config *cfg); + +#endif /* AXP209_H */

1 0

Patch set updated for coreboot: 710abf9 northbridge/intel: Trivial fsp_rangeley northbridge cleanups
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6420 -gerrit commit 710abf9c107aadc9b3b4a6ecaaa4f3306624e521 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jul 31 09:07:38 2014 +1000 northbridge/intel: Trivial fsp_rangeley northbridge cleanups Alphabetize headers and some minor style clean ups, nothing significant to see here. Introduced in: 2963ae7 northbridge/intel: Add fsp_rangeley northbridge support Change-Id: I13f2c46aa2bcedb9d1c66c485bf48ed7bc95d9c7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_rangeley/acpi.c | 13 +++++++------ src/northbridge/intel/fsp_rangeley/chip.h | 2 +- .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 18 ++++++++---------- .../intel/fsp_rangeley/fsp/chipset_fsp_util.h | 10 +++++----- src/northbridge/intel/fsp_rangeley/northbridge.c | 17 +++++++++-------- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_rangeley/port_access.c | 5 +++-- src/northbridge/intel/fsp_rangeley/raminit.c | 7 ++++--- src/northbridge/intel/fsp_rangeley/udelay.c | 4 ++-- 9 files changed, 40 insertions(+), 38 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 895f5b4..7be183e 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -21,15 +21,16 @@ * MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <arch/io.h> #include <arch/acpi.h> +#include <arch/io.h> +#include <build.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <build.h> +#include <string.h> +#include <types.h> + #include "northbridge.h" unsigned long acpi_fill_mcfg(unsigned long current) @@ -56,7 +57,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; /* 256MB ECAM range */ - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); max_buses = 256; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 24609a1..0d19aa7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -60,4 +60,4 @@ struct northbridge_intel_fsp_rangeley_config { uint8_t Bifurcation; }; -#endif +#endif /* _FSP_RANGELEY_CHIP_H_ */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index bd196a5..b95446f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -17,23 +17,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <cpu/x86/stack.h> -#include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/stack.h> #include <device/device.h> -#include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp/fsp_util.h> -#include <fspvpd.h> #include <fspbootmode.h> +#include <fspvpd.h> +#include <string.h> +#include <southbridge/intel/fsp_rangeley/romstage.h> +#include <southbridge/intel/fsp_rangeley/pci_devs.h> +#include <types.h> #include <reset.h> -#include "../chip.h" -#ifdef __PRE_RAM__ -#include <southbridge/intel/fsp_rangeley/romstage.h> -#endif +#include "../chip.h" #ifdef __PRE_RAM__ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..09c4c38 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -20,13 +20,13 @@ #ifndef CHIPSET_FSP_UTIL_H #define CHIPSET_FSP_UTIL_H -#include <fsptypes.h> -#include <fspfv.h> -#include <fspffs.h> #include <fspapi.h> +#include <fspffs.h> +#include <fspfv.h> +#include <fsphob.h> #include <fspplatform.h> +#include <fsptypes.h> #include <fspinfoheader.h> -#include <fsphob.h> #include <fspvpd.h> #define FSP_RESERVE_MEMORY_SIZE 0x200000 @@ -42,7 +42,7 @@ } /* - *The FSP Image ID is different for each platform's FSP and + * The FSP Image ID is different for each platform's FSP and * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 98c0b9c..397c53f 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -19,24 +19,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> -#include <stdint.h> -#include <delay.h> -#include <cpu/intel/fsp_model_406dx/model_406dx.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> +#include <cpu/intel/fsp_model_406dx/model_406dx.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/fsp/fsp_util.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> -#include <cpu/cpu.h> -#include <cbmem.h> + #include "chip.h" #include "northbridge.h" -#include <drivers/intel/fsp/fsp_util.h> -#include <cpu/x86/lapic.h> static int bridge_revision_id = -1; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 855a056..6d40380 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index 508630e..83667f0 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -22,11 +22,12 @@ #define __PRE_RAM__ // Use simple device model for this file even in ramstage #endif -#include <stdint.h> #include <arch/io.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> +#include <stdint.h> + #include "northbridge.h" /* diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..3dbdfb9 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -18,13 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <device/pci_def.h> -#include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> +#include <string.h> + +#include "northbridge.h" unsigned long get_top_of_ram(void) { diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index bdd9f78..a921609 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <delay.h> -#include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <delay.h> +#include <stdint.h> /** * Intel Rangeley CPUs always run the TSC at BCLK=100MHz

1 0

Patch set updated for coreboot: 13c020f superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
by Edward O'Callaghan 31 Jul '14

31 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6231 -gerrit commit 13c020fdcb809c321a5d09fa95da84f44c638fe2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 20:26:25 2014 +1000 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/common/early_serial.c | 6 +++--- src/superio/fintek/common/fintek.h | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++---- src/superio/ite/common/early_serial.c | 16 ++++++++-------- src/superio/ite/common/ite.h | 10 +++++----- src/superio/ite/it8661f/early_serial.c | 10 +++++----- src/superio/ite/it8661f/it8661f.h | 2 +- src/superio/ite/it8671f/early_serial.c | 2 +- src/superio/ite/it8671f/it8671f.h | 2 +- src/superio/ite/it8718f/early_serial.c | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/nsc/pc8374/early_init.c | 2 +- src/superio/nsc/pc87309/early_serial.c | 2 +- src/superio/nsc/pc87309/pc87309.h | 2 +- src/superio/nsc/pc87351/early_serial.c | 2 +- src/superio/nsc/pc87360/early_serial.c | 2 +- src/superio/nsc/pc87366/early_serial.c | 2 +- src/superio/nsc/pc87392/early_serial.c | 2 +- src/superio/nsc/pc87417/early_init.c | 6 +++--- src/superio/nsc/pc87417/early_serial.c | 4 ++-- src/superio/nsc/pc87417/pc87417.h | 4 ++-- src/superio/nsc/pc87427/early_init.c | 6 +++--- src/superio/nsc/pc97317/early_serial.c | 2 +- src/superio/nuvoton/common/early_serial.c | 6 +++--- src/superio/nuvoton/common/nuvoton.h | 2 +- src/superio/nuvoton/nct5104d/early_init.c | 6 +++--- src/superio/nuvoton/nct5104d/nct5104d.h | 2 +- src/superio/serverengines/pilot/early_init.c | 2 +- src/superio/serverengines/pilot/early_serial.c | 8 ++++---- src/superio/serverengines/pilot/pilot.h | 10 +++++----- src/superio/smsc/fdc37m60x/early_serial.c | 2 +- src/superio/smsc/kbc1100/early_init.c | 8 ++++---- src/superio/smsc/kbc1100/kbc1100.h | 2 +- src/superio/smsc/lpc47b272/early_serial.c | 6 +++--- src/superio/smsc/lpc47b397/early_serial.c | 6 +++--- src/superio/smsc/lpc47m10x/early_serial.c | 6 +++--- src/superio/smsc/lpc47m15x/early_serial.c | 6 +++--- src/superio/smsc/lpc47n217/early_serial.c | 10 +++++----- src/superio/smsc/lpc47n227/early_serial.c | 10 +++++----- src/superio/smsc/sch4037/sch4037_early_init.c | 6 +++--- src/superio/smsc/sio1036/sio1036_early_init.c | 8 ++++---- src/superio/smsc/smscsuperio/early_serial.c | 6 +++--- src/superio/smsc/smscsuperio/smscsuperio.h | 2 +- src/superio/winbond/common/early_serial.c | 6 +++--- src/superio/winbond/common/winbond.h | 2 +- src/superio/winbond/w83627dhg/early_serial.c | 8 ++++---- src/superio/winbond/w83627dhg/w83627dhg.h | 8 ++++---- src/superio/winbond/w83627ehg/early_serial.c | 4 ++-- src/superio/winbond/w83627ehg/w83627ehg.h | 4 ++-- src/superio/winbond/w83627hf/early_init.c | 6 +++--- src/superio/winbond/w83627hf/early_serial.c | 8 ++++---- src/superio/winbond/w83627hf/w83627hf.h | 4 ++-- src/superio/winbond/w83627thg/w83627thg.h | 6 +++--- src/superio/winbond/w83697hf/early_serial.c | 8 ++++---- src/superio/winbond/w83697hf/w83697hf.h | 4 ++-- src/superio/winbond/w83977f/early_serial.c | 6 +++--- src/superio/winbond/w83977tf/early_serial.c | 6 +++--- 57 files changed, 146 insertions(+), 146 deletions(-) diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index d74b786..4433d11 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -46,7 +46,7 @@ #define FINTEK_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void fintek_enable_serial(device_t dev, u16 iobase) +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index a08cf92..1bc308b 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void fintek_enable_serial(device_t dev, u16 iobase); +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..96bb550 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "i3100.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -29,7 +29,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(0x86, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -38,14 +38,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +static void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +static void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 73354d4..a57c047 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -33,14 +33,14 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ /* Helper procedure */ -static void ite_sio_write(device_t dev, u8 reg, u8 value) +static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_set_logical_device(dev); pnp_write_config(dev, reg, value); } /* Enable configuration */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -51,12 +51,12 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); } -void ite_reg_write(device_t dev, u8 reg, u8 value) +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_enter_conf_state(dev); ite_sio_write(dev, reg, value); @@ -71,13 +71,13 @@ void ite_reg_write(device_t dev, u8 reg, u8 value) * ITE_UART_CLK_PREDIVIDE_24 * ITE_UART_CLK_PREDIVIDE_48 (default) */ -void ite_conf_clkin(device_t dev, u8 predivide) +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide) { ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); } /* Bring up early serial debugging output before the RAM is initialized. */ -void ite_enable_serial(device_t dev, u16 iobase) +void ite_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -101,7 +101,7 @@ void ite_enable_serial(device_t dev, u16 iobase) * and pass: GPIO_DEV */ -void ite_enable_3vsbsw(device_t dev) +void ite_enable_3vsbsw(pnp_devfn_t dev) { u8 tmp; pnp_enter_conf_state(dev); @@ -118,7 +118,7 @@ void ite_enable_3vsbsw(device_t dev) * and pass: GPIO_DEV */ -void ite_kill_watchdog(device_t dev) +void ite_kill_watchdog(pnp_devfn_t dev) { pnp_enter_conf_state(dev); ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00); diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 5389f14..c732664 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -27,12 +27,12 @@ #define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ #define ITE_UART_CLK_PREDIVIDE_24 0x01 -void ite_conf_clkin(device_t dev, u8 predivide); -void ite_enable_serial(device_t dev, u16 iobase); +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide); +void ite_enable_serial(pnp_devfn_t dev, u16 iobase); /* Some boards need to init wdt+gpio's very early */ -void ite_reg_write(device_t dev, u8 reg, u8 value); -void ite_enable_3vsbsw(device_t dev); -void ite_kill_watchdog(device_t dev); +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); +void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_kill_watchdog(pnp_devfn_t dev); #endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index 7373f71..19d60b1 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -26,7 +26,7 @@ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { int i; u16 port = dev >> 8; @@ -42,7 +42,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(init_values[i], port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); } @@ -55,21 +55,21 @@ static void pnp_exit_ext_func_mode(device_t dev) * * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. */ -static void it8661f_enable_logical_devices(device_t dev) +static void it8661f_enable_logical_devices(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); pnp_exit_ext_func_mode(dev); } -static void it8661f_set_clkin(device_t dev, u8 clkin) +static void it8661f_set_clkin(pnp_devfn_t dev, u8 clkin) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); pnp_exit_ext_func_mode(dev); } -void it8661f_enable_serial(device_t dev, u16 iobase) +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 045a54c..297dea3 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -52,6 +52,6 @@ static const u8 init_values[] = { 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -void it8661f_enable_serial(device_t dev, u16 iobase); +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8661F_H */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index 9f35b8a..89feb5f 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -89,7 +89,7 @@ void it8671f_48mhz_clkin(void) } /* Enable the serial port(s). */ -void it8671f_enable_serial(device_t dev, u16 iobase) +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase) { it8671f_enter_conf(); diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index c3865ff..90f1481 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -34,6 +34,6 @@ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ void it8671f_48mhz_clkin(void); -void it8671f_enable_serial(device_t dev, u16 iobase); +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8671F__H */ diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 166c856..563132a 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -27,7 +27,7 @@ * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(device_t dev) +void it8718f_disable_reboot(pnp_devfn_t dev) { ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 61c75cf..c0a79c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -35,6 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -void it8718f_disable_reboot(device_t dev); +void it8718f_disable_reboot(pnp_devfn_t dev); #endif /* SUPERIO_ITE_IT8718F_H */ diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c index d3f601d..a5e9b95 100644 --- a/src/superio/nsc/pc8374/early_init.c +++ b/src/superio/nsc/pc8374/early_init.c @@ -46,7 +46,7 @@ static void pc8374_enable(u16 iobase, u8 *init) } } -static void pc8374_enable_dev(device_t dev, u16 iobase) +static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c index 6e48e0c..da0d5d7 100644 --- a/src/superio/nsc/pc87309/early_serial.c +++ b/src/superio/nsc/pc87309/early_serial.c @@ -22,7 +22,7 @@ #include <device/pnp_def.h> #include "pc87309.h" -void pc87309_enable_serial(device_t dev, u16 iobase) +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h index 5f39b6e..513576e 100644 --- a/src/superio/nsc/pc87309/pc87309.h +++ b/src/superio/nsc/pc87309/pc87309.h @@ -34,6 +34,6 @@ #include <arch/io.h> #include <stdint.h> -void pc87309_enable_serial(device_t dev, u16 iobase); +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c index c34538f..a31f79c 100644 --- a/src/superio/nsc/pc87351/early_serial.c +++ b/src/superio/nsc/pc87351/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87351.h" -static void pc87351_enable_serial(device_t dev, u16 iobase) +static void pc87351_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index da4abdb..3deac3b 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87360.h" -static void pc87360_enable_serial(device_t dev, u16 iobase) +static void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e173afd..e663df6 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87366.h" -static void pc87366_enable_serial(device_t dev, u16 iobase) +static void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c index 6e85fb9..f1e5716 100644 --- a/src/superio/nsc/pc87392/early_serial.c +++ b/src/superio/nsc/pc87392/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "pc87392.h" -static void pc87392_enable_serial(device_t dev, u16 iobase) +static void pc87392_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index d1870f9..42f8cd1 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "pc87417.h" -static void pc87417_disable_dev(device_t dev) +static void pc87417_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(device_t dev, u16 iobase) +static void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -37,7 +37,7 @@ static void pc87417_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 33bae7e..42ba941 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include "pc87417.h" -void pc87417_enable_serial(device_t dev, u16 iobase) +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -31,7 +31,7 @@ void pc87417_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -void pc87417_enable_dev(device_t dev) +void pc87417_enable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 1); diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 73c1fbc..e7d5413 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -115,8 +115,8 @@ #define PC87417_XWBCNF 0x16 #if defined(__PRE_RAM__) -void pc87417_enable_serial(device_t dev, u16 iobase); -void pc87417_enable_dev(device_t dev); +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); +void pc87417_enable_dev(pnp_devfn_t dev); #endif #endif diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c index 6df1b9f..adaa868 100644 --- a/src/superio/nsc/pc87427/early_init.c +++ b/src/superio/nsc/pc87427/early_init.c @@ -22,13 +22,13 @@ #include <arch/io.h> #include "pc87427.h" -static void pc87427_disable_dev(device_t dev) +static void pc87427_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87427_enable_dev(device_t dev, u16 iobase) +static void pc87427_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -36,7 +36,7 @@ static void pc87427_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index 0c21561..ad43010 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -25,7 +25,7 @@ #define PM_BASE 0xe8 /* The PC97317 needs clocks to be set up before the serial port will operate. */ -static void pc97317_enable_serial(device_t dev, u16 iobase) +static void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) { /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 1cbcee8..dbb0d13 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -49,7 +49,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -57,14 +57,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void nuvoton_enable_serial(device_t dev, u16 iobase) +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index e9e8d4b..43d80a9 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -25,6 +25,6 @@ #include <arch/io.h> #include <stdint.h> -void nuvoton_enable_serial(device_t dev, u16 iobase); +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index c9a408e..96fac19 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -28,7 +28,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -36,14 +36,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Route UARTD to pins 41-48 */ -void nct5104d_enable_uartd(device_t dev) +void nct5104d_enable_uartd(pnp_devfn_t dev) { u8 tmp; u16 port = dev >> 8; diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index e4dcf38..5b12cc5 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -48,6 +48,6 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -void nct5104d_enable_uartd(device_t dev); +void nct5104d_enable_uartd(pnp_devfn_t dev); #endif /* SUPERIO_NUVOTON_NCT5104D_H */ diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 002210f..6635645 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -32,7 +32,7 @@ * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -void pilot_early_init(device_t dev) +void pilot_early_init(pnp_devfn_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 82e124c..3e99ef4 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -26,20 +26,20 @@ #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x5A, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xA5, port); } /* Serial config is a fairly standard procedure. */ -void pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -48,7 +48,7 @@ void pilot_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void pilot_disable_serial(device_t dev) +void pilot_disable_serial(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index e19cf37..cffa258 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -31,12 +31,12 @@ #define PILOT_LD7 0x07 /* Logical device 7 */ /* should not expose these however early_init needs love */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void pilot_early_init(device_t dev); +void pilot_early_init(pnp_devfn_t dev); -void pilot_enable_serial(device_t dev, u16 iobase); -void pilot_disable_serial(device_t dev); +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase); +void pilot_disable_serial(pnp_devfn_t dev); #endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index 38cb0f8..80258a9 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -46,7 +46,7 @@ static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) } /* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, u16 iobase) +static void fdc37m60x_enable_serial(pnp_devfn_t dev, u16 iobase) { /* (1) Enter the configuration state. */ outb(0x55, FDC37M60X_CONFIGURATION_PORT); diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c index d075f9c..bd42288 100644 --- a/src/superio/smsc/kbc1100/early_init.c +++ b/src/superio/smsc/kbc1100/early_init.c @@ -26,19 +26,19 @@ #include "kbc1100.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void kbc1100_early_serial(device_t dev, u16 iobase) +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -50,7 +50,7 @@ void kbc1100_early_serial(device_t dev, u16 iobase) void kbc1100_early_init(u16 port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, KBC1100_KBC); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 2b588f9..ec24dd3 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -36,7 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ -void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase); void kbc1100_early_init(u16 port); #endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index b2f0d1b..3624df2 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47b272.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47b272_enable_serial(device_t dev, u16 iobase) +static void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 31d515b..953cd4b 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -23,19 +23,19 @@ #include <arch/io.h> #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void lpc47b397_enable_serial(device_t dev, u16 iobase) +static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index fc6efb9..1174120 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "lpc47m10x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -40,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(device_t dev, u16 iobase) +static void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index 5686f52..0a42ad3 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -25,19 +25,19 @@ #include "lpc47m15x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void lpc47m15x_enable_serial(device_t dev, u16 iobase) +void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 451628a..7405f32 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -24,13 +24,13 @@ #include <assert.h> #include "lpc47n217.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); @@ -74,7 +74,7 @@ static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -109,7 +109,7 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(device_t dev, u16 iobase) +static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 4aea7c5..64a6d84 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47n227.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -41,7 +41,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n227_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N227 requires base ports to be a multiple of 4. */ /* it's not very useful to do an ASSERT here: if it trips, @@ -76,7 +76,7 @@ static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n227_pnp_set_enable(device_t dev, int enable) +static void lpc47n227_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -111,7 +111,7 @@ static void lpc47n227_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n227_enable_serial(device_t dev, u16 iobase) +static void lpc47n227_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index 29517ed..5be8fa8 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "sch4037.h" -static inline void pnp_enter_conf_state(device_t dev) +static inline void pnp_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0xaa, port); @@ -35,7 +35,7 @@ static void pnp_exit_conf_state(device_t dev) static inline void sch4037_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..9b1be52 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -25,13 +25,13 @@ #ifndef CONFIG_TTYS0_BASE #define CONFIG_TTYS0_BASE 0x3F8 #endif -static inline void sio1036_enter_conf_state(device_t dev) +static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0x55, port); } -static inline void sio1036_exit_conf_state(device_t dev) +static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0xaa, port); @@ -39,7 +39,7 @@ static inline void sio1036_exit_conf_state(device_t dev) static u8 detect_sio1036_chip(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, SIO1036_SP1); unsigned data; sio1036_enter_conf_state (dev); @@ -57,7 +57,7 @@ static u8 detect_sio1036_chip(unsigned port) static inline void sio1036_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, SIO1036_SP1); if (detect_sio1036_chip(port) != 0) { diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index e2eea6d..c058ef5 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -29,14 +29,14 @@ #define SMSC_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_ENTRY_KEY, port); } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_EXIT_KEY, port); @@ -49,7 +49,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev The device to use. * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ -void smscsuperio_enable_serial(device_t dev, u16 iobase) +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/smscsuperio/smscsuperio.h b/src/superio/smsc/smscsuperio/smscsuperio.h index 60a58e6..8a761ba 100644 --- a/src/superio/smsc/smscsuperio/smscsuperio.h +++ b/src/superio/smsc/smscsuperio/smscsuperio.h @@ -30,6 +30,6 @@ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ -void smscsuperio_enable_serial(device_t dev, u16 iobase); +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_SMSC_SMSCSUPERIO_H */ diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 747cc45..fd51cd5 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -46,7 +46,7 @@ #define WINBOND_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void winbond_enable_serial(device_t dev, u16 iobase) +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 20eefc8..0f937c1 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(device_t dev, u16 iobase); +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_COMMON_ROMSTAGE_H */ diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 67aaa93..83f8e34 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -24,14 +24,14 @@ #include <stdint.h> #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ void pnp_exit_ext_func_mode(device_t dev) * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} */ -void w83627dhg_enable_i2c(device_t dev) +void w83627dhg_enable_i2c(pnp_devfn_t dev) { u8 val; @@ -56,7 +56,7 @@ void w83627dhg_enable_i2c(device_t dev) pnp_exit_ext_func_mode(dev); } -void w83627dhg_set_clksel_48(device_t dev) +void w83627dhg_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 08ea04f..c4ead34 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -52,9 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); -void w83627dhg_enable_i2c(device_t dev); -void w83627dhg_set_clksel_48(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); +void w83627dhg_enable_i2c(pnp_devfn_t dev); +void w83627dhg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627DHG_H */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..e052863 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -23,14 +23,14 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..3d6f56f 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627EHG_H */ diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index db616ae..2e275e6 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -25,14 +25,14 @@ #include <device/pnp.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -43,7 +43,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * work around a limitation of ROMCC where we can no make early_serial.c into * link-time symbols and #include early_serial.c. */ -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index bc251a6..694a3fe 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -24,14 +24,14 @@ #include <arch/io.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -49,7 +49,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * XXX: ROMCC - everything is inlined, no forwarding function prototypes * declarations are accepted. */ -void w83627hf_enable_serial(device_t dev, u16 iobase) +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -59,7 +59,7 @@ void w83627hf_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index bf7186e..6eeb62b 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -115,7 +115,7 @@ #include <arch/io.h> -void w83627hf_set_clksel_48(device_t dev); -void w83627hf_enable_serial(device_t dev, u16 iobase); +void w83627hf_set_clksel_48(pnp_devfn_t dev); +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83627HF_H */ diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index ec857d3..8d85379 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,9 +34,9 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void w83627thg_set_clksel_48(device_t dev); +void w83627thg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627THG_W83627THG_H */ diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 6c00b27..515fee9 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -22,20 +22,20 @@ #include <device/pnp_def.h> #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; @@ -47,7 +47,7 @@ void w83697hf_set_clksel_48(device_t dev) } /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase) +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index f711786..3bd1f44 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -34,9 +34,9 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -void w83697hf_set_clksel_48(device_t); +void w83697hf_set_clksel_48(pnp_devfn_t); /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase); +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83697HF_H */ diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index c572dcb..9b5785d 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -21,20 +21,20 @@ #include <arch/io.h> #include "w83977f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977f_enable_serial(device_t dev, u16 iobase) +static void w83977f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c index c016515..866d9f2 100644 --- a/src/superio/winbond/w83977tf/early_serial.c +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -23,20 +23,20 @@ #include <arch/io.h> #include "w83977tf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977tf_enable_serial(device_t dev, u16 iobase) +static void w83977tf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2014