Patch set updated for coreboot: 4ac9e05 superio/winbond/w83627ehg: Remove pnp_enter symbol from global
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5871 -gerrit commit 4ac9e05732da1b716291fa9779a346b3a15ecd00 Author: Edward O'Callaghan <eocallaghan@alterapraxis.com> Date: Mon May 26 04:35:48 2014 +1000 superio/winbond/w83627ehg: Remove pnp_enter symbol from global Part 2/2: Break this poor relationship between boards and Super I/O support to be more well-defined. The Super I/O pnp_entry/exit functions should not be exposed into the global name-space, rather should be static-local. Provide Winbond w83627eh(f/g) input clock rate selection. This is selected by bit 6 of CR 24h by mask & 0xbf map (1 = 48MHz default) -> (0 = 24MHz), see data-sheet page 98. Change-Id: Ie39235f2926a2165092319a6b1375e505b7dac14 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 17 ++++++++++++++--- src/mainboard/asus/a8v-e_se/romstage.c | 17 ++++++++++++++--- src/mainboard/ibase/mb899/romstage.c | 13 +++++++++++++ src/mainboard/msi/ms7260/romstage.c | 5 +---- src/mainboard/msi/ms9652_fam10/romstage.c | 7 +------ src/mainboard/nvidia/l1_2pvv/romstage.c | 4 +--- src/superio/winbond/w83627ehg/early_serial.c | 17 +++++++++++++---- src/superio/winbond/w83627ehg/w83627ehg.h | 6 ++++-- 8 files changed, 61 insertions(+), 25 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..25169c0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -97,14 +97,24 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* We have GPIO for KB/MS pin. */ reg = pnp_read_config(SERIAL_DEV, 0x2a); pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); @@ -154,6 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..a11403a 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -97,14 +97,24 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* We have GPIO for KB/MS pin. */ reg = pnp_read_config(SERIAL_DEV, 0x2a); pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); @@ -154,6 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0e74418..24238b3 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -70,6 +70,19 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..072bae9 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -119,12 +119,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ - pnp_write_config(SERIAL_DEV, 0x24, 0); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..eff291b 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -103,7 +103,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; - u8 reg; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -121,11 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c..75bdb6f 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -118,9 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..dce18cf 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,15 +23,24 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } + +void w83627ehg_serial_clk(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + /* We have 24MHz input. */ + u8 reg = pnp_read_config(dev, 0x24); + pnp_write_config(dev, 0x24, (reg & 0xbf)); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..b514488 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,9 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +#include <arch/io.h> +#include <device/pnp.h> + +void w83627ehg_serial_clk(device_t); #endif /* SUPERIO_WINBOND_W83627EHG_H */
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Edward O'Callaghan