coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 06a8e6f i82801ix: Allow configuration of SATA mode in CMOS.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6409 -gerrit commit 06a8e6f2dd7f13070375a7e7a3cc1533a53a7b09 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:35:45 2014 +0200 i82801ix: Allow configuration of SATA mode in CMOS. Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/roda/rk9/cmos.layout | 5 ++++- src/mainboard/roda/rk9/devicetree.cb | 1 - src/southbridge/intel/i82801ix/chip.h | 2 -- src/southbridge/intel/i82801ix/sata.c | 23 ++++++++++++++++------- 4 files changed, 20 insertions(+), 11 deletions(-) diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index 8f12ef4..ca439c9 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -85,7 +85,8 @@ entries #400 8 r 0 unused # coreboot config options: southbridge -#408 8 r 0 unused +408 1 e 9 sata_mode +#409 7 r 0 unused # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -133,6 +134,8 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 5989278..deece86 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/gm45 register "alt_gp_smi_en" = "0x0002" # Set AHCI mode, enable ports 1 and 2. - register "sata_ahci" = "1" register "sata_port_map" = "0x03" register "sata_clock_request" = "0" register "sata_traffic_monitor" = "0" diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 222cfb5..5e1221d 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -70,8 +70,6 @@ struct southbridge_intel_i82801ix_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; /* If enabled, keep bit 2 of sata_enabled unset. */ uint8_t sata_port_map : 6; int sata_clock_request : 1; int sata_traffic_monitor : 1; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 02f6d53..10c8a2b 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "i82801ix.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_i82801ix_config config_t; @@ -149,6 +150,7 @@ static void sata_init(struct device *const dev) const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); const int is_mobile = (devid == 0x2928) || (devid == 0x2929); + u8 sata_mode; printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); @@ -158,6 +160,10 @@ static void sata_init(struct device *const dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * TODO: In contrast to ICH7 and PCH code we don't set * timings, dma and IDE-I/O settings here. Looks like they @@ -171,13 +177,11 @@ static void sata_init(struct device *const dev) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); - if (!config->sata_ahci) + if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); - } else if (config->sata_ahci) { + if (sata_mode == 0) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); } else { printk(BIOS_DEBUG, "SATA controller in native mode.\n"); @@ -193,7 +197,7 @@ static void sata_init(struct device *const dev) /* Port enable. For AHCI, it's managed in memory mapped space. */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; - reg16 |= (1 << 15) | (config->sata_ahci ? 0x3f : config->sata_port_map); + reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map); pci_write_config16(dev, 0x92, reg16); /* SATA clock settings */ @@ -218,7 +222,7 @@ static void sata_init(struct device *const dev) } } - if (config->sata_ahci) + if (sata_mode == 0) sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); sata_program_indexed(dev, is_mobile); @@ -230,15 +234,20 @@ static void sata_enable(device_t dev) const config_t *const config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */ map |= (config->sata_port_map ^ 0x3f) << 8;

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Patch set updated for coreboot: 331a02a gm45: Move spd address map to board-specific config.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5931 -gerrit commit 331a02ae0cdb77e07321c2e6552ba3e893d492b3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jun 5 09:14:48 2014 +0200 gm45: Move spd address map to board-specific config. Change-Id: I8f45a821ecd414dbd0129ae6d583d4e7dc06bc5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/roda/rk9/romstage.c | 4 ++ src/northbridge/intel/gm45/gm45.h | 1 + src/northbridge/intel/gm45/raminit.c | 81 +++++++++++++++++++----------------- 3 files changed, 48 insertions(+), 38 deletions(-) diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 0ebd5da..d4bb56a 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -171,6 +171,10 @@ void main(unsigned long bist) /* RAM initialization */ enter_raminit_or_reset(); get_gmch_info(&sysinfo); + sysinfo.spd_map[0] = 0x50; + sysinfo.spd_map[1] = 0; + sysinfo.spd_map[2] = 0x52; + sysinfo.spd_map[3] = 0; raminit(&sysinfo, s3resume); raminit_thermal(&sysinfo); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 227baef..edcb56b 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -143,6 +143,7 @@ typedef struct { int spd_type; timings_t selected_timings; dimminfo_t dimms[2]; + u8 spd_map[4]; } sysinfo_t; #define TOTAL_CHANNELS 2 #define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 1f66760..149127f 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -235,61 +235,62 @@ void enter_raminit_or_reset(void) /* For a detected DIMM, test the value of an SPD byte to match the expected value after masking some bits. */ -static int test_dimm(int dimm, int addr, int bitmask, int expected) +static int test_dimm(sysinfo_t *const sysinfo, + int dimm, int addr, int bitmask, int expected) { - return (smbus_read_byte(DIMM0 + dimm, addr) & bitmask) == expected; + return (smbus_read_byte(sysinfo->spd_map[dimm], addr) & bitmask) == expected; } /* This function dies if dimm is unsuitable for the chipset. */ -static void verify_ddr3_dimm(int dimm) +static void verify_ddr3_dimm(sysinfo_t *const sysinfo, int dimm) { - if (!test_dimm(dimm, 3, 15, 3)) + if (!test_dimm(sysinfo, dimm, 3, 15, 3)) die("Chipset only supports SO-DIMM\n"); - if (!test_dimm(dimm, 8, 0x18, 0)) + if (!test_dimm(sysinfo, dimm, 8, 0x18, 0)) die("Chipset doesn't support ECC RAM\n"); - if (!test_dimm(dimm, 7, 0x38, 0) && - !test_dimm(dimm, 7, 0x38, 8)) + if (!test_dimm(sysinfo, dimm, 7, 0x38, 0) && + !test_dimm(sysinfo, dimm, 7, 0x38, 8)) die("Chipset wants single or double sided DIMMs\n"); - if (!test_dimm(dimm, 7, 7, 1) && - !test_dimm(dimm, 7, 7, 2)) + if (!test_dimm(sysinfo, dimm, 7, 7, 1) && + !test_dimm(sysinfo, dimm, 7, 7, 2)) die("Chipset requires x8 or x16 width\n"); - if (!test_dimm(dimm, 4, 0x0f, 0) && - !test_dimm(dimm, 4, 0x0f, 1) && - !test_dimm(dimm, 4, 0x0f, 2) && - !test_dimm(dimm, 4, 0x0f, 3)) + if (!test_dimm(sysinfo, dimm, 4, 0x0f, 0) && + !test_dimm(sysinfo, dimm, 4, 0x0f, 1) && + !test_dimm(sysinfo, dimm, 4, 0x0f, 2) && + !test_dimm(sysinfo, dimm, 4, 0x0f, 3)) die("Chipset requires 256Mb, 512Mb, 1Gb or 2Gb chips."); - if (!test_dimm(dimm, 4, 0x70, 0)) + if (!test_dimm(sysinfo, dimm, 4, 0x70, 0)) die("Chipset requires 8 banks on DDR3\n"); /* How to check if burst length is 8? Other values are not supported, are they even possible? */ - if (!test_dimm(dimm, 10, 0xff, 1)) + if (!test_dimm(sysinfo, dimm, 10, 0xff, 1)) die("Code assumes 1/8ns MTB\n"); - if (!test_dimm(dimm, 11, 0xff, 8)) + if (!test_dimm(sysinfo, dimm, 11, 0xff, 8)) die("Code assumes 1/8ns MTB\n"); - if (!test_dimm(dimm, 62, 0x9f, 0) && - !test_dimm(dimm, 62, 0x9f, 1) && - !test_dimm(dimm, 62, 0x9f, 2) && - !test_dimm(dimm, 62, 0x9f, 3) && - !test_dimm(dimm, 62, 0x9f, 5)) + if (!test_dimm(sysinfo, dimm, 62, 0x9f, 0) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 1) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 2) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 3) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 5)) die("Only raw card types A, B, C, D and F are supported.\n"); } /* For every detected DIMM, test if it's suitable for the chipset. */ -static void verify_ddr3(int mask) +static void verify_ddr3(sysinfo_t *const sysinfo, int mask) { int cur = 0; while (mask) { if (mask & 1) { - verify_ddr3_dimm(cur); + verify_ddr3_dimm(sysinfo, cur); } mask >>= 1; cur++; @@ -321,14 +322,15 @@ typedef struct { * This function collects RAM characteristics from SPD, assuming that RAM * is generally within chipset's requirements, since verify_ddr3() passed. */ -static void collect_ddr3(spdinfo_t *const config) +static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config) { int mask = config->dimm_mask; int cur = 0; while (mask != 0) { - if (mask & 1) { + /* FIXME: support several dimms on same channel. */ + if ((mask & 1) && sysinfo->spd_map[2 * cur]) { int tmp; - const int smb_addr = DIMM0 + cur*2; + const int smb_addr = sysinfo->spd_map[2 * cur]; config->channel[cur].rows = ((smbus_read_byte(smb_addr, 5) >> 3) & 7) + 12; config->channel[cur].cols = (smbus_read_byte(smb_addr, 5) & 7) + 9; @@ -358,7 +360,7 @@ static void collect_ddr3(spdinfo_t *const config) config->channel[cur].raw_card = smbus_read_byte(smb_addr, 62) & 0x1f; } cur++; - mask >>= 2; /* Only every other address is used. */ + mask >>= 2; } } @@ -590,17 +592,20 @@ static void collect_dimm_config(sysinfo_t *const sysinfo) spdinfo.dimm_mask = 0; sysinfo->spd_type = 0; - /* at most 2 dimms, on even slots */ - for (i = 0; i < 4; i += 2) { - const u8 spd = smbus_read_byte(DIMM0 + i, 2); - if ((spd == 7) || (spd == 8) || (spd == 0xb)) { - spdinfo.dimm_mask |= 1 << i; - if (sysinfo->spd_type && sysinfo->spd_type != spd) { - die("Multiple types of DIMM installed in the system, don't do that!\n"); + for (i = 0; i < 4; i++) + if (sysinfo->spd_map[i]) { + const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2); + printk (BIOS_DEBUG, "%x:%x:%x\n", + i, sysinfo->spd_map[i], + spd); + if ((spd == 7) || (spd == 8) || (spd == 0xb)) { + spdinfo.dimm_mask |= 1 << i; + if (sysinfo->spd_type && sysinfo->spd_type != spd) { + die("Multiple types of DIMM installed in the system, don't do that!\n"); + } + sysinfo->spd_type = spd; } - sysinfo->spd_type = spd; } - } if (spdinfo.dimm_mask == 0) { die("Could not find any DIMM.\n"); } @@ -612,8 +617,8 @@ static void collect_dimm_config(sysinfo_t *const sysinfo) if (sysinfo->spd_type == DDR2) { die("DDR2 not supported at this time.\n"); } else if (sysinfo->spd_type == DDR3) { - verify_ddr3(spdinfo.dimm_mask); - collect_ddr3(&spdinfo); + verify_ddr3(sysinfo, spdinfo.dimm_mask); + collect_ddr3(sysinfo, &spdinfo); } else { die("Will never support DDR1.\n"); }

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Patch set updated for coreboot: f87cb0b northbridge/intel/sandybridge/raminit_native: Remove stale FIXME.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6407 -gerrit commit f87cb0bdf659527dca618920ff7996cff24d2df7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:07:59 2014 +0200 northbridge/intel/sandybridge/raminit_native: Remove stale FIXME. S3 works just fine. Change-Id: Icd7ae5ad8941bf749a4450efc61e7cede52bf5ef Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/raminit_native.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index c6e5e77..9b49f11 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -44,7 +44,6 @@ /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ -/* FIXME: no S3. */ #define BASEFREQ 133 #define tDLLK 512

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New patch to review for coreboot: 7cac149 LZMA: Add a version of ulzma which takes the input and output buffer sizes.
by Isaac Christensen 29 Jul '14

29 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6408 -gerrit commit 7cac149531cfceff4a6087fcdf1db1c8c56dab2c Author: Gabe Black <gabeblack(a)google.com> Date: Sat Aug 10 09:35:56 2013 -0700 LZMA: Add a version of ulzma which takes the input and output buffer sizes. This version is used to implement the version which doesn't. Old-Change-Id: I8935024aca0849bc939263d7fc3036c586e63c68 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65510 Reviewed-by: Kees Cook <keescook(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 465d167ad2f6a67d0b2c91fb6c68c8f9a09dd395) libpayload: Make lzma truncation non-fatal. If the size the lzma header claims it needs is bigger than the space we have, print a message and continue rather than erroring out. Apparently the encoder is lazy sometimes and just puts a large value there regardless of what the actual size is. This was the original intention for this code, but an outdated version of the patch ended up being submitted. Old-Change-Id: Ibcf7ac0fd4b65ce85377421a4ee67b82d92d29d3 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66235 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 30c628eeada274fc8b94f8f69f9df4f33cbfc773) Squashed two related commits. Change-Id: I484b5c1e3809781033d146609a35a9e5e666c8ed Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/include/lzma.h | 12 ++++++++++-- payloads/libpayload/liblzma/lzma.c | 18 ++++++++++++++---- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/lzma.h b/payloads/libpayload/include/lzma.h index 818c16d..523bc8c 100644 --- a/payloads/libpayload/include/lzma.h +++ b/payloads/libpayload/include/lzma.h @@ -30,10 +30,18 @@ #ifndef _LZMA_H #define _LZMA_H -/* decompresses the data stream at src to dst, determining its length from +/* Decompresses the data stream at src to dst. The sizes of the source and + * destination buffers are in srcn and dstn. + * + * Returns the decompressed size, or 0 on error + */ +unsigned long ulzman(const unsigned char *src, unsigned long srcn, + unsigned char *dst, unsigned long dstn); + +/* Decompresses the data stream at src to dst, determining its length from * the data stream itself. * - * returns the decompressed size, or 0 on error + * Returns the decompressed size, or 0 on error */ unsigned long ulzma(const unsigned char *src, unsigned char *dst); diff --git a/payloads/libpayload/liblzma/lzma.c b/payloads/libpayload/liblzma/lzma.c index 0b97213..23c9562 100644 --- a/payloads/libpayload/liblzma/lzma.c +++ b/payloads/libpayload/liblzma/lzma.c @@ -14,9 +14,11 @@ #include <string.h> #include "lzmadecode.c" -unsigned long ulzma(const unsigned char * src, unsigned char * dst) +unsigned long ulzman(const unsigned char *src, unsigned long srcn, + unsigned char *dst, unsigned long dstn) { unsigned char properties[LZMA_PROPERTIES_SIZE]; + const int data_offset = LZMA_PROPERTIES_SIZE + 8; UInt32 outSize; SizeT inProcessed; SizeT outProcessed; @@ -27,7 +29,10 @@ unsigned long ulzma(const unsigned char * src, unsigned char * dst) memcpy(properties, src, LZMA_PROPERTIES_SIZE); memcpy(&outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize)); - if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { + if (outSize > dstn) + outSize = dstn; + if (LzmaDecodeProperties(&state.Properties, properties, + LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { printf("lzma: Incorrect stream properties.\n"); return 0; } @@ -37,11 +42,16 @@ unsigned long ulzma(const unsigned char * src, unsigned char * dst) return 0; } state.Probs = (CProb *)scratchpad; - res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed, - dst, outSize, &outProcessed); + res = LzmaDecode(&state, src + data_offset, srcn - data_offset, + &inProcessed, dst, outSize, &outProcessed); if (res != 0) { printf("lzma: Decoding error = %d\n", res); return 0; } return outSize; } + +unsigned long ulzma(const unsigned char *src, unsigned char *dst) +{ + return ulzman(src, (unsigned long)(-1), dst, (unsigned long)(-1)); +}

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New patch to review for coreboot: 6476750 northbridge/intel/sandybridge/raminit_native: Remove stale FIXME.
by Vladimir Serbinenko 29 Jul '14

29 Jul '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6407 -gerrit commit 6476750576e0067992ab334ed7c1c411287e0b32 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jul 29 22:07:59 2014 +0200 northbridge/intel/sandybridge/raminit_native: Remove stale FIXME. S3 works just fine. Change-Id: Icd7ae5ad8941bf749a4450efc61e7cede52bf5ef Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/raminit_native.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index c6e5e77..9b49f11 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -44,7 +44,6 @@ /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ -/* FIXME: no S3. */ #define BASEFREQ 133 #define tDLLK 512

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New patch to review for coreboot: 3260f12 timer: Add functions to initialize absolute timer structures.
by Isaac Christensen 29 Jul '14

29 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6406 -gerrit commit 3260f12e3dd6c9798a77dcb14e2522f3e796d3a3 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Aug 9 00:48:06 2013 -0700 timer: Add functions to initialize absolute timer structures. Otherwise there's no good way to create an absolute timer structure without fiddling with its internal structure or assuming a zero initialized structure has a value of zero. Old-Change-Id: Iffe3b6b25ed7963fcfb66f749c531ea445ea4aeb Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65301 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit e2e5c1ef3bb2df95fdf0e33cb2d975a990d07a4a) exynos: Simplify the monotonic timer implementation. The previous implementation was overly complicated, and when used in the timestamp implementation produced some weird and broken results. Old-Change-Id: I3048028ddea0657b01b0c94f312764b38d1397e4 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65302 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit 6a3fde9a5b80cdac76d79c65d20d7dd1f1d9e557) Squashed two closely related commits. Change-Id: Ifc32d773f4f93d34275a81781001d080357fe8ef Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/cpu/samsung/exynos5250/monotonic_timer.c | 28 ++++------------------------ src/cpu/samsung/exynos5420/monotonic_timer.c | 28 ++++------------------------ src/include/timer.h | 12 ++++++++++++ 3 files changed, 20 insertions(+), 48 deletions(-) diff --git a/src/cpu/samsung/exynos5250/monotonic_timer.c b/src/cpu/samsung/exynos5250/monotonic_timer.c index 57e3ae3..267d9c3 100644 --- a/src/cpu/samsung/exynos5250/monotonic_timer.c +++ b/src/cpu/samsung/exynos5250/monotonic_timer.c @@ -18,40 +18,20 @@ */ #include <stdint.h> -#include <delay.h> #include <timer.h> #include "clk.h" -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint64_t last_value; -} mono_counter; +static int initialized; static const uint32_t clocks_per_usec = MCT_HZ/1000000; void timer_monotonic_get(struct mono_time *mt) { - uint64_t current_tick; - uint64_t usecs_elapsed; - - if (!mono_counter.initialized) { + if (!initialized) { mct_start(); - mono_counter.last_value = mct_raw_value(); - mono_counter.initialized = 1; - } - - current_tick = mct_raw_value(); - usecs_elapsed = (current_tick - mono_counter.last_value) / - clocks_per_usec; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; + initialized = 1; } - /* Save result. */ - *mt = mono_counter.time; + mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec); } diff --git a/src/cpu/samsung/exynos5420/monotonic_timer.c b/src/cpu/samsung/exynos5420/monotonic_timer.c index 57e3ae3..267d9c3 100644 --- a/src/cpu/samsung/exynos5420/monotonic_timer.c +++ b/src/cpu/samsung/exynos5420/monotonic_timer.c @@ -18,40 +18,20 @@ */ #include <stdint.h> -#include <delay.h> #include <timer.h> #include "clk.h" -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint64_t last_value; -} mono_counter; +static int initialized; static const uint32_t clocks_per_usec = MCT_HZ/1000000; void timer_monotonic_get(struct mono_time *mt) { - uint64_t current_tick; - uint64_t usecs_elapsed; - - if (!mono_counter.initialized) { + if (!initialized) { mct_start(); - mono_counter.last_value = mct_raw_value(); - mono_counter.initialized = 1; - } - - current_tick = mct_raw_value(); - usecs_elapsed = (current_tick - mono_counter.last_value) / - clocks_per_usec; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; + initialized = 1; } - /* Save result. */ - *mt = mono_counter.time; + mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec); } diff --git a/src/include/timer.h b/src/include/timer.h index 06128ce..b37cea4 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -67,6 +67,18 @@ int timers_run(void); * 0 returned on success, < 0 on error. */ int timer_sched_callback(struct timeout_callback *tocb, unsigned long us); +/* Set an absolute time to a number of microseconds. */ +static inline void mono_time_set_usecs(struct mono_time *mt, long us) +{ + mt->microseconds = us; +} + +/* Set an absolute time to a number of milliseconds. */ +static inline void mono_time_set_msecs(struct mono_time *mt, long ms) +{ + mt->microseconds = ms * USECS_PER_MSEC; +} + /* Add microseconds to an absolute time. */ static inline void mono_time_add_usecs(struct mono_time *mt, long us) {

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New patch to review for coreboot: cfa1311 armv7/exynos5420: Configure CPU cores for kernel to enable SMP.
by Isaac Christensen 29 Jul '14

29 Jul '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6405 -gerrit commit cfa131147fc87846e0d8957c427ecb7c8ade3e82 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Aug 6 20:37:55 2013 +0800 armv7/exynos5420: Configure CPU cores for kernel to enable SMP. The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/armv7/include/arch/cpu.h | 6 + src/cpu/samsung/exynos5420/Kconfig | 9 +- src/cpu/samsung/exynos5420/Makefile.inc | 1 + src/cpu/samsung/exynos5420/cpu.h | 6 +- src/cpu/samsung/exynos5420/smp.c | 305 ++++++++++++++++++++++++++++++++ src/mainboard/google/pit/romstage.c | 1 + 6 files changed, 324 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h index 2613025..ec37a96 100644 --- a/src/arch/armv7/include/arch/cpu.h +++ b/src/arch/armv7/include/arch/cpu.h @@ -98,4 +98,10 @@ inline static void sev(void) asm volatile ("sev"); } +/* puts CPU into SVC32 mode and disable interrupts. */ +inline static void set_svc32_mode(void) +{ + asm volatile("msr cpsr_c, %0" :: "r"(0x13 | 0xc0)); +} + #endif /* __ARCH_CPU_H__ */ diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index d7adf6c..6066040 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -46,6 +46,11 @@ config CBFS_ROM_OFFSET # 0x0202_4400: variable length bootblock checksum header. # 0x0202_4410: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. +# 0x0206_0000: cache for CBFS data. +# 0x0207_3000: shared (with kernel) page for cpu & secondary core states. +# the shared data is currently only <0x50 bytes so we can share +# this page with stack. +# 0x0207_3100: stack bottom # 0x0207_4000: stack pointer config BOOTBLOCK_BASE @@ -71,11 +76,11 @@ config STACK_TOP config STACK_BOTTOM hex - default 0x02073000 + default 0x02073100 config STACK_SIZE hex - default 0x1000 + default 0x0f00 # TODO We may probably move this to board-specific implementation files instead # of KConfig values. diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 279e803..3191627 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c romstage-y += spi.c +romstage-y += smp.c romstage-y += clock.c romstage-y += clock_init.c romstage-y += pinmux.c # required by s3c24x0_i2c and uart. diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 22ef8db..08f315a 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -224,8 +224,6 @@ #define EXYNOS5_SPI_NUM_CONTROLLERS 5 #define EXYNOS_I2C_MAX_CONTROLLERS 8 -void exynos5420_config_l2_cache(void); - extern struct tmu_info exynos5420_tmu_info; /* TODO clean up defines. */ @@ -264,4 +262,8 @@ static inline u32 get_fb_base_kb(void) return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; } +/* Procedures to setup Exynos5420 CPU */ +void exynos5420_config_l2_cache(void); +void exynos5420_config_smp(void); + #endif /* _EXYNOS5420_CPU_H */ diff --git a/src/cpu/samsung/exynos5420/smp.c b/src/cpu/samsung/exynos5420/smp.c new file mode 100644 index 0000000..392f82d --- /dev/null +++ b/src/cpu/samsung/exynos5420/smp.c @@ -0,0 +1,305 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <stdlib.h> +#include <string.h> + +#include <cpu/samsung/exynos5420/cpu.h> +#include <cpu/samsung/exynos5420/power.h> + +/* ACTLR, L2CTLR L2ACTLR constants used in SMP core power up. */ + +#define ACTLR_SMP (1 << 6) + +#define L2CTLR_ECC_PARITY (1 << 21) +#define L2CTLR_DATA_RAM_LATENCY_MASK (7 << 0) +#define L2CTLR_TAG_RAM_LATENCY_MASK (7 << 6) +#define L2CTLR_DATA_RAM_LATENCY_CYCLES_3 (2 << 0) +#define L2CTLR_TAG_RAM_LATENCY_CYCLES_3 (2 << 6) + +#define L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL (1 << 3) +#define L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (1 << 7) +#define L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE (1 << 27) + +/* Part number in CPU ID (MPIDR). */ +#define PART_NUMBER_CORTEX_A15 (0xc0f) + +/* State of CPU cores in Exynos 5420. */ +#define CORE_STATE_RESET (1 << 0) +#define CORE_STATE_SECONDARY_RESET (1 << 1) +#define CORE_STATE_SWITCH_CLUSTER (1 << 4) + +/* The default address to re-power on a code. */ +#define CORE_RESET_INIT_ADDRESS ((void*)0x00000000) + +/* Vectors in BL1 (0x02020000 = base of iRAM). */ +#define VECTOR_CORE_SEV_HANDLER ((void*)(intptr_t)0x02020004) +#define VECTOR_LOW_POWER_FLAG ((void*)(intptr_t)0x02020028) +#define VECTOR_LOW_POWER_ADDRESS ((void*)(intptr_t)0x0202002C) + +/* The data structure for the "CPU state" memory page (shared with kernel) + * controlling cores in active cluster. Kernel will put starting address for one + * core in "hotplug_address" before power on. Note the address is hard-coded in + * kernel (EXYNOS5420_PA_SYSRAM_NS = 0x02073000). */ +volatile struct exynos5420_cpu_states +{ + uint32_t _reserved[2]; /* RESV, +0x00 */ + uint32_t resume_address; /* REG0, +0x08 */ + uint32_t resume_flag; /* REG1, +0x0C */ + uint32_t _reg2; /* REG2, +0x10 */ + uint32_t _reg3; /* REG3, +0x14 */ + uint32_t switch_address; /* REG4, +0x18, cluster switching */ + uint32_t hotplug_address; /* REG5, +0x1C, core hotplug */ + uint32_t _reg6; /* REG6, +0x20 */ + uint32_t c2_address; /* REG7, +0x24, C2 state change */ + + /* Managed per core status for active cluster, offset: +0x28~0x38 */ + uint32_t cpu_states[4]; + + /* Managed per core GIC status for active cluster, offset: 0x38~0x48 */ + uint32_t cpu_gic_states[4]; +} *exynos_cpu_states = (volatile struct exynos5420_cpu_states*)0x02073000; + +/* When leaving core handlers and jump to hot-plug address (or cluster + * switching), we are not sure if the destination is Thumb or ARM mode. + * So a BX command is required. + */ +inline static void jump_bx(void *address) +{ + asm volatile ("bx %0" : : "r"(address)); + /* never returns. */ +} + +/* Extracts arbitrary bits from a 32-bit unsigned int. */ +inline static uint32_t get_bits(uint32_t value, uint32_t start, uint32_t len) +{ + return ((value << (sizeof(value) * 8 - len - start)) >> + (sizeof(value) * 8 - len)); +} + +/* Waits the referenced address to be ready (non-zero) and then jump into it. */ +static void wait_and_jump(volatile uint32_t* reference) +{ + while (!*reference) { + wfe(); + } + jump_bx((void*)*reference); +} + +/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ +static void configure_l2ctlr(void) +{ + uint32_t val; + + val = read_l2ctlr(); + val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); + val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | + L2CTLR_ECC_PARITY); + write_l2ctlr(val); +} + +/* Configures L2 Auxiliary Control Register for Cortex A15. */ +static void configure_l2actlr(void) +{ + uint32_t val; + + val = read_l2actlr(); + val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); + write_l2actlr(val); +} + +/* Initializes the CPU states to reset state. */ +static void init_exynos_cpu_states(void) { + memset((void*)exynos_cpu_states, 0, sizeof(*exynos_cpu_states)); + exynos_cpu_states->cpu_states[0] = CORE_STATE_RESET; + exynos_cpu_states->cpu_states[1] = CORE_STATE_SECONDARY_RESET; + exynos_cpu_states->cpu_states[2] = CORE_STATE_SECONDARY_RESET; + exynos_cpu_states->cpu_states[3] = CORE_STATE_SECONDARY_RESET; +} + +/* + * Ensures that the L2 logic has been used within the previous 256 cycles + * before modifying the ACTLR.SMP bit. This is required during boot before + * MMU has been enabled, or during a specified reset or power down sequence. + */ +static void enable_smp(void) +{ + uint32_t actlr, val; + + /* Enable SMP mode */ + actlr = read_actlr(); + actlr |= ACTLR_SMP; + + /* Dummy read to assure L2 access */ + val = readl((void*)INF_REG_BASE); + val &= 0; + actlr |= val; + + write_actlr(actlr); + dsb(); + isb(); +} + +/* Starts the core and jumps to correct location by its state. */ +static void core_start_execution(void) +{ + u32 cpu_id, cpu_state; + struct exynos5_power *power = samsung_get_base_power(); + + enable_smp(); + set_svc32_mode(); + + cpu_id = read_mpidr() & 0x3; /* up to 4 processors for one cluster. */ + cpu_state = exynos_cpu_states->cpu_states[cpu_id]; + + if (cpu_state & CORE_STATE_SWITCH_CLUSTER) { + wait_and_jump(&exynos_cpu_states->switch_address); + /* never returns. */ + } + + /* Standard Exynos suspend/resume. */ + if (power->inform1) { + power->inform1 = 0; + jump_bx((void*)power->inform0); + /* never returns. */ + } + + if (cpu_state & CORE_STATE_RESET) { + /* For Reset, U-Boot jumps to its starting address; + * on Coreboot, seems ok to ignore for now. */ + } + wait_and_jump(&exynos_cpu_states->hotplug_address); + /* never returns. */ +} + +/* The entry point for hotplug-in and cluster switching. */ +static void low_power_start(void) +{ + uint32_t sctlr, reg_val; + + /* On warm reset, because iRAM is not cleared, all cores will enter + * low_power_start, not the initial address. So we need to check reset + * status again, and jump to 0x0 in that case. */ + reg_val = readl((void*)RST_FLAG_REG); + if (reg_val != RST_FLAG_VAL) { + writel(0x0, VECTOR_LOW_POWER_FLAG); + jump_bx(CORE_RESET_INIT_ADDRESS); + /* restart cpu execution and never returns. */ + } + + /* Workaround for iROM EVT1. A7 core execution may flow into incorrect + * path, bypassing first jump address and makes final jump address 0x0, + * so we try to make any core set again low_power_start address, if that + * becomes zero. */ + reg_val = readl(VECTOR_CORE_SEV_HANDLER); + if (reg_val != (intptr_t)low_power_start) { + writel((intptr_t)low_power_start, VECTOR_CORE_SEV_HANDLER); + dsb(); + /* ask all cores to power on again. */ + sev(); + } + + set_svc32_mode(); + + /* Whenever a Cortex A-15 core powers on, iROM resets its L2 cache + * so we need to configure again. */ + if (get_bits(read_midr(), 4, 12) == PART_NUMBER_CORTEX_A15) { + configure_l2ctlr(); + configure_l2actlr(); + } + + /* Invalidate L1 & TLB */ + tlbiall(); + iciallu(); + + /* Disable MMU stuff and caches */ + sctlr = read_sctlr(); + sctlr &= ~(SCTLR_V | SCTLR_M | SCTLR_C); + sctlr |= (SCTLR_I | SCTLR_Z | SCTLR_A); + write_sctlr(sctlr); + + core_start_execution(); + /* The core should not return. But in order to prevent unexpected + * errors, a WFI command will help to put CPU back to idle state. */ + wfi(); +} + +/* Callback to shutdown a core, safe to be set as hot-plug address. */ +static void power_down_core(void) +{ + uint32_t mpidr, core_id; + + /* MPIDR: 0~2=ID, 8~11=cluster. On Exynos 5420, cluster will be only 0 + * or 1. */ + mpidr = read_mpidr(); + core_id = get_bits(mpidr, 0, 2) | (get_bits(mpidr, 8, 4) << 2); + + /* Set the status of the core to low. + * S5E5420A User Manual, 8.8.1.202, ARM_CORE0_CONFIGURATION, two bits to + * control power state in each power down level. + */ + writel(0x0, (void*)(ARM_CORE0_CONFIG + core_id * CORE_CONFIG_OFFSET)); + + /* S5E5420A User Manual, 8.4.2.5, after ARM_CORE*_CONFIGURATION has been + * set to zero, PMU will detect and wait for WFI then run power-down + * sequence. */ + wfi(); +} + +/* Configures the CPU states shard memory page and then shutdown all cores. */ +static void configure_secondary_cores(void) +{ + configure_l2ctlr(); + + /* Currently we use power_down_core as callback for each core to + * shutdown itself, but it is also ok to directly set ARM_CORE*_CONFIG + * to zero by CPU0 because every secondary cores should be already in + * WFI state (in bootblock). The power_down_core will be more helpful + * when we want to use SMP inside firmware. */ + + /* Clear boot reg (hotplug address) in cpu states */ + writel(0, (void*)&exynos_cpu_states->hotplug_address); + + /* set low_power flag and address */ + writel((intptr_t)low_power_start, VECTOR_LOW_POWER_ADDRESS); + writel(RST_FLAG_VAL, VECTOR_LOW_POWER_FLAG); + writel(RST_FLAG_VAL, (void*)RST_FLAG_REG); + + /* On next SEV, shutdown all cores. */ + writel((intptr_t)power_down_core, VECTOR_CORE_SEV_HANDLER); + + /* Ask all cores in WFE mode to shutdown. */ + dsb(); + sev(); +} + +/* Configures the SMP cores on Exynos 5420 SOC (and shutdown all secondary + * cores) */ +void exynos5420_config_smp(void) +{ + init_exynos_cpu_states(); + configure_secondary_cores(); +} + diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 7733eca..7037112 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -246,6 +246,7 @@ void main(void) int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); int power_init_failed; + exynos5420_config_smp(); power_init_failed = setup_power(is_resume); /* Clock must be initialized before console_init, otherwise you may need

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Patch merged into coreboot/master: 77acf42 pit: setup voltage rails before system clocks
by gerrit＠coreboot.org 29 Jul '14

29 Jul '14

the following patch was just integrated into master: commit 77acf42819ed93f77706089b024a771323d34c7a Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Aug 5 21:04:16 2013 -0700 pit: setup voltage rails before system clocks This moves the call to setup_power() before system_clock_init(). This causes the PMIC to set up the voltage rails earlier so that the CPU clock can be set up at a faster rate (in the follow-up patch). After system clock init, we re-initialize the PMIC's I2C bus since the input clock rate will have changed. Old-Change-Id: Ieb828ac25daad7ee95bfa4823aaaf161028c9c92 Reviewed-on: https://gerrit.chromium.org/gerrit/64744 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 6c133a84ef4a32c35577a266905e02af8c2d9278) pit: save setup_power() status and die later if needed Since system clock and console initialization now happen after power setup, we cannot print error messages in setup_power(). This patch re-factors the code a little bit to save the status of setup_power() so that if we get an error during setup_power() we will wait until we can actually print something before dying. Old-Change-Id: Id7ff477224b104b3c7e221c1d2df460ca9125f3b Reviewed-on: https://gerrit.chromium.org/gerrit/65009 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 0c89f922b20bc1291ac7ba7b2c22bdce911be7a4) Squashed two closely related commits. Change-Id: I3efe29412738959e698c89d26e682536ceabdff8 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6403 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6403 for details. -gerrit

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Patch set updated for coreboot: fe34abf payloads/external/SeaBIOS: Update makefile for olddefconfig
by Martin Roth 29 Jul '14

29 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6362 -gerrit commit fe34abfa41a86d5224f3dd2d539428d4ced6ebff Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:24:32 2014 -0600 payloads/external/SeaBIOS: Update makefile for olddefconfig Instead of creating the SeaBIOS .config file for QEMU, then changing things to be coreboot specific, create a default config for coreboot, then run olddefconfig to use the SeaBIOS defaults as they're set for coreboot. This leads to a cleaner config. Note that CONFIG_THREAD_OPTIONROMS defaults to enabled for SeaBIOS if we're building for coreboot, so I reversed the logic. I *ASSUMED* that leaving CONFIG_QEMU_HARDWARE=y and CONFIG_DEBUG_IO=y previously was an oversight. If this is not correct, please let me know and I'll add them it back in. SeaBIOS disables these by default if building for coreboot. Change-Id: I42c6a56205bb15c6693a5f3a716b7876a4d78abe Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- payloads/external/SeaBIOS/Makefile.inc | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 48ca582..e981309 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -24,20 +24,14 @@ checkout: fetch config: checkout echo " CONFIG SeaBIOS $(TAG-y)" - $(MAKE) -C $(OUT)/seabios defconfig OUT=$(OUT)/seabios/out/ - echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config -ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - echo "CONFIG_THREAD_OPTIONROMS=y" >> $(OUT)/seabios/.config -endif + echo "CONFIG_COREBOOT=y" > $(OUT)/seabios/.config echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config - echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config - echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config - echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config - echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config - echo "CONFIG_DEBUG_COREBOOT=y" >> $(OUT)/seabios/.config +ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) + echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config + $(MAKE) -C $(OUT)/seabios olddefconfig OUT=$(OUT)/seabios/out/ build: config echo " MAKE SeaBIOS $(TAG-y)"

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Patch set updated for coreboot: 4363be0 payloads/external/SeaBIOS: Use coreboot’s serial console settings
by Martin Roth 29 Jul '14

29 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6363 -gerrit commit 4363be07fe7ca58318bed4ae07c841697ba684fb Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:33:49 2014 -0600 payloads/external/SeaBIOS: Use coreboot’s serial console settings Set up the serial console on SeaBIOS to match coreboot's settings. Previously, we were just forcing it on, and setting it to 0x3f8. Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- payloads/external/SeaBIOS/Makefile.inc | 5 +++++ src/arch/x86/Makefile.inc | 2 ++ 2 files changed, 7 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index e981309..21f933a 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -25,7 +25,12 @@ checkout: fetch config: checkout echo " CONFIG SeaBIOS $(TAG-y)" echo "CONFIG_COREBOOT=y" > $(OUT)/seabios/.config +ifeq ($(CONFIG_CONSOLE_SERIAL),y) echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> $(OUT)/seabios/.config +else + echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config +endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config endif diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c0e908d..2e92d89 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -350,6 +350,8 @@ seabios: CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ + CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ + CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo:

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coreboot-gerrit July 2014