coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 3fe4814 haswell: keep ROM cache enabled
by Aaron Durbin 03 Apr '13

03 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3008 -gerrit commit 3fe48146cd3dd8a2e2f1010e39cd682d3e79ddc3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 1 16:49:31 2013 -0500 haswell: keep ROM cache enabled The MP code on haswell was mirroring the BSPs MTRRs. In addition it was cleaning up the ROM cache so that the MTRR register values were the same once the OS was booted. Since the hyperthread sibling of the BSP was going through this path the ROM cache was getting torn down once the hyperthread was brought up. That said, there was no differnce in observed boot time keeping the ROM cache enabled. Change-Id: I2a59988fcfeea9291202c961636ea761c2538837 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/mp_init.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index cc13892..ddcff6c 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -181,8 +181,12 @@ ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* Cleanup ROM caching. */ - cleanup_rom_caching(); + /* The MTRR resources are core scoped. Therefore, there is no need + * to do the same work twice. Additionally, this check keeps the + * ROM cache enabled on the BSP since its hyperthread sibling won't + * call cleanup_rom_caching(). */ + if ((lapicid() & 1) == 0) + cleanup_rom_caching(); /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */

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Patch set updated for coreboot: a85f3b1 haswell: use new interface to disable rom caching
by Aaron Durbin 03 Apr '13

03 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3007 -gerrit commit a85f3b132c3142e6052b7262e03063559352519c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 1 15:40:45 2013 -0500 haswell: use new interface to disable rom caching The haswell code was using the old assumption of which MTRR was used for the ROM cache. Now that there is an API for doing this use it as the old assumption is no longer valid. Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/mp_init.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index c8bd5c2..cc13892 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -145,28 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel) * ensure the caching is disabled for tha APs before going to sleep. */ static void cleanup_rom_caching(void) { -#if CONFIG_CACHE_ROM - msr_t msr; - unsigned int last_var_mtrr; - - msr = rdmsr(MTRRcap_MSR); - last_var_mtrr = (msr.lo & 0xff) - 1; - - /* Check if the MTRR is valid. */ - msr = rdmsr(MTRRphysMask_MSR(last_var_mtrr)); - if ((msr.lo & MTRRphysMaskValid) == 0) - return; - msr = rdmsr(MTRRphysBase_MSR(last_var_mtrr)); - /* Assum that if the MTRR is of write protected type, the MTRR is used - * to cache the ROM. */ - if ((msr.lo & MTRR_NUM_TYPES) == MTRR_TYPE_WRPROT) { - msr.lo = msr.hi = 0; - disable_cache(); - wrmsr(MTRRphysMask_MSR(last_var_mtrr), msr); - wrmsr(MTRRphysBase_MSR(last_var_mtrr), msr); - enable_cache(); - } -#endif + x86_mtrr_disable_rom_caching(); } /* By the time APs call ap_init() caching has been setup, and microcode has

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Patch set updated for coreboot: 7145d14 Add PXE ROM selection to Kconfig menu
by Siyuan Wang 03 Apr '13

03 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3013 -gerrit commit 7145d141503f4898de895a41974c6236bdd089c7 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 3 17:02:58 2013 +0800 Add PXE ROM selection to Kconfig menu Adding a pxe rom manually is inconvenient. With this patch, PXE ROM can be added automatically by selecting PXE_ROM in Kconfig. I have tested this patch on AMD Parmer and Thatcher with iPXE. iPXE would be a boot device in Seabios when pressing F12. iPXE works well with coreboot and Seabios. Change-Id: I2c4fc73fd9ae6c979f0af2290d410935f600e2c8 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/arch/x86/Makefile.inc | 3 +++ src/device/Kconfig | 31 +++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bbf2336..ee2bc47 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,6 +113,9 @@ endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB_ELF) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) endif +ifeq ($(CONFIG_PXE_ROM),y) + $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/device/Kconfig b/src/device/Kconfig index 159bc0e..ca2fb33 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -467,3 +467,34 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. endmenu + +menu "PXE ROM" +config PXE_ROM + bool "Add a PXE ROM image" + help + Select this option if you have a PXE ROM image that you would + like to add to your ROM. + +config PXE_ROM_FILE + string "PXE ROM filename" + depends on PXE_ROM + default "pxe.rom" + help + The path and filename of the file to use as PXE ROM. + +config PXE_ROM_ID + string "network card PCI IDs" + depends on PXE_ROM + default "10ec,8168" + help + The comma-separated PCI vendor and device ID that would associate + your PXE ROM to your network card. + + Example: 10ec,8168 + + In the above example 10ec is the PCI vendor ID (in hex, but without + the "0x" prefix) and 8168 specifies the PCI device ID of the + network card (also in hex, without "0x" prefix). + + Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. +endmenu

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New patch to review for coreboot: 9d0e635 inteltool: pcie.c: Cast `0xff` to `uint64_t` to avoid shift overflow
by Paul Menzel 03 Apr '13

03 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3015 -gerrit commit 9d0e63535e228d2d4bd0d5ed523c2d7ac692202c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Apr 3 10:00:33 2013 +0200 inteltool: pcie.c: Cast `0xff` to `uint64_t` to avoid shift overflow When building inteltool with Clang, it warns about the following. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ CC=clang make […] clang -O2 -g -Wall -W -c -o pcie.o pcie.c pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0xff << 28); ~~~~ ^ ~~ pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0x1ff << 27); ~~~~~ ^ ~~ pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0x3ff << 26); ~~~~~ ^ ~~ 3 warnings generated. […] Casting the numbers to `(uint64_t)` fixes these issues as now enough bits are available. These issues were introduced in commit 1162f25a [1]. commit 1162f25a49e8f39822123d664cda10fef466b351 Author: Stefan Reinauer <stepan(a)coresystems.de> Date: Thu Dec 4 15:18:20 2008 +0000 Patch to util/inteltool: * PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39… Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/pcie.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 752d7b0..29e1759 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -294,15 +294,15 @@ int print_pciexbar(struct pci_dev *nb) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar_phys = pciexbar_reg & (0xff << 28); + pciexbar_phys = pciexbar_reg & ((uint64_t)0xff << 28); max_busses = 256; break; case 1: // 128M - pciexbar_phys = pciexbar_reg & (0x1ff << 27); + pciexbar_phys = pciexbar_reg & ((uint64_t)0x1ff << 27); max_busses = 128; break; case 2: // 64M - pciexbar_phys = pciexbar_reg & (0x3ff << 26); + pciexbar_phys = pciexbar_reg & ((uint64_t)0x3ff << 26); max_busses = 64; break; default: // RSVD

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New patch to review for coreboot: f723fd1 ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors
by Paul Menzel 03 Apr '13

03 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3014 -gerrit commit f723fd1143c4242cf22cc8d5fabcaece2e9c0d26 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Apr 3 11:36:50 2013 +0200 ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors Now that the ASRock E350M1 builds without any warnings, remove the config option `WARNINGS_ARE_ERRORS` set to no by default from the file `Kconfig` so warnings are treated as errors to prevent code from being added in the future introducing warnings. Change-Id: Idfecfb1434158969334a4b37972b5fc6fd76e72a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 96f6712..a308850 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -108,9 +108,5 @@ config DRIVERS_PS2_KEYBOARD bool default n -config WARNINGS_ARE_ERRORS - bool - default n - endif # BOARD_ASROCK_E350M1

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Patch set updated for coreboot: 92ba16c intel/bd82x6x: Support mobile 5 southbridge
by Vladimir Serbinenko 03 Apr '13

03 Apr '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2995 -gerrit commit 92ba16cf9fabcf478c225dff687ae717666b502d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 31 22:22:10 2013 +0200 intel/bd82x6x: Support mobile 5 southbridge Adjust bd82x6x to support mobile 5 revision as well. Successfully tested on Lenovo X201. Change-Id: I18054cf7edae92f2d8776561661d5b87599ece25 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/parrot/devicetree.cb | 11 ++ src/mainboard/intel/emeraldlake2/devicetree.cb | 11 ++ src/mainboard/samsung/lumpy/devicetree.cb | 11 ++ src/mainboard/samsung/stumpy/devicetree.cb | 11 ++ src/southbridge/intel/bd82x6x/Kconfig | 20 ++++ src/southbridge/intel/bd82x6x/Makefile.inc | 1 + src/southbridge/intel/bd82x6x/azalia.c | 2 +- src/southbridge/intel/bd82x6x/chip.h | 49 +++++++++ src/southbridge/intel/bd82x6x/early_smbus.c | 15 +++ src/southbridge/intel/bd82x6x/lpc.c | 103 +++++++++++++++++- src/southbridge/intel/bd82x6x/me.c | 17 ++- src/southbridge/intel/bd82x6x/me.h | 1 + src/southbridge/intel/bd82x6x/pch.h | 47 ++------ src/southbridge/intel/bd82x6x/sata.c | 46 +++++--- src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/bd82x6x/smbus.h | 144 +++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/spi.c | 3 +- src/southbridge/intel/bd82x6x/thermal.c | 84 +++++++++++++++ src/southbridge/intel/bd82x6x/usb_debug.c | 9 +- src/southbridge/intel/bd82x6x/usb_ehci.c | 41 ++++--- 20 files changed, 549 insertions(+), 79 deletions(-) diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..32d7c54 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -64,6 +64,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C register "gen1_dec" = "0x0004fd61" diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..cf82e45 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -53,6 +53,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..26b6d73 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -62,6 +62,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # EC range is 0xa00-0xa3f register "gen1_dec" = "0x003c0a01" diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..cf308e9 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -52,6 +52,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 5dd492c..71881f3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -72,4 +72,24 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config USBDEBUG_DEV + int + default 29 + +config USBDEBUG_FUNC + int + default 7 + +config USBDEBUG_DEFAULT_PORT + int + default 2 + +config IO_APIC_ID + int + default 2 + +config PMCON_RAMINIT_REVERSED + int + default 1 + endif diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index bc3ff4b..366b7e4 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c ramstage-y += smbus.c +ramstage-y += thermal.c ramstage-y += me_status.c ramstage-y += reset.c diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 2d854a4..17141d6 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -362,7 +362,7 @@ static struct device_operations azalia_ops = { .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; +static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 }; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..96d0b02 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -20,6 +20,44 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) + +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) + struct southbridge_intel_bd82x6x_config { /** * Interrupt Routing configuration @@ -69,6 +107,17 @@ struct southbridge_intel_bd82x6x_config { uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; + uint8_t sata_irq_line; + uint16_t ide_tim_pri; + uint32_t ide_config; + uint16_t ide_sdma_cnt; + uint16_t ide_sdma_tim; + uint32_t sir4; + uint32_t sir28; + uint32_t sir54; + uint32_t sir64; + uint32_t sir88; + int set98; /** * SATA Interface Speed Support Configuration diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 9de97e7..d8aff92 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -60,3 +60,18 @@ int smbus_read_byte(unsigned device, unsigned address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +int smbus_write_byte(unsigned device, unsigned address, u8 data) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); +} + +int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf) +{ + return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + +int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df37ddc..835f0c8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -52,7 +52,7 @@ static void pch_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (CONFIG_IO_APIC_ID << 24); /* affirm full set of redirection table entries ("write once") */ *ioapic_index = 1; @@ -63,7 +63,7 @@ static void pch_enable_apic(struct device *dev) *ioapic_index = 0; reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) + if (reg32 != (CONFIG_IO_APIC_ID << 24)) die("APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); @@ -391,6 +391,96 @@ static void ppt_pm_init(struct device *dev) RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } +static void mobile5_pm_init(struct device *dev) +{ + int i; + + printk(BIOS_DEBUG, "Mobile 5 PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + + RCBA32 (0x1d44) = 0x00000000; + (void) RCBA32 (0x1d44); + RCBA32 (0x1d48) = 0x00030000; + (void) RCBA32 (0x1d48); + RCBA32 (0x1e80) = 0x000c0801; + (void) RCBA32 (0x1e80); + RCBA32 (0x1e84) = 0x000200f0; + (void) RCBA32 (0x1e84); + + const u32 rcba2010[] = + { + /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, + /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 + }; + for (i = 0; i < sizeof (rcba2010) / sizeof (rcba2010[0]); i++) + { + RCBA32 (0x2010 + 4 * i) = rcba2010[i]; + RCBA32 (0x2010 + 4 * i); + } + + RCBA32 (0x2100) = 0x00000000; + (void) RCBA32 (0x2100); + RCBA32 (0x2104) = 0x00000757; + (void) RCBA32 (0x2104); + RCBA32 (0x2108) = 0x00170001; + (void) RCBA32 (0x2108); + + RCBA32 (0x211c) = 0x00000000; + (void) RCBA32 (0x211c); + RCBA32 (0x2120) = 0x00010000; + (void) RCBA32 (0x2120); + + RCBA32 (0x21fc) = 0x00000000; + (void) RCBA32 (0x21fc); + RCBA32 (0x2200) = 0x20000044; + (void) RCBA32 (0x2200); + RCBA32 (0x2204) = 0x00000001; + (void) RCBA32 (0x2204); + RCBA32 (0x2208) = 0x00003457; + (void) RCBA32 (0x2208); + + const u32 rcba2210[] = + { + /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, + /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, + /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, + /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, + /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 + }; + + for (i = 0; i < sizeof (rcba2210) / sizeof (rcba2210[0]); i++) + { + RCBA32 (0x2210 + 4 * i) = rcba2210[i]; + RCBA32 (0x2210 + 4 * i); + } + + const u32 rcba2300[] = + { + /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, + /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, + /* 2320: */ 0xcccc0cfc, 0x0fbb0fff + }; + + for (i = 0; i < sizeof (rcba2300) / sizeof (rcba2300[0]); i++) + { + RCBA32 (0x2300 + 4 * i) = rcba2300[i]; + RCBA32 (0x2300 + 4 * i); + } + + RCBA32 (0x37fc) = 0x00000000; + (void) RCBA32 (0x37fc); + RCBA32 (0x3dfc) = 0x00000000; + (void) RCBA32 (0x3dfc); + RCBA32 (0x3e7c) = 0xffffffff; + (void) RCBA32 (0x3e7c); + RCBA32 (0x3efc) = 0x00000000; + (void) RCBA32 (0x3efc); + RCBA32 (0x3f00) = 0x0000010b; + (void) RCBA32 (0x3f00); +} + static void enable_hpet(void) { u32 reg32; @@ -503,12 +593,14 @@ static void pch_disable_smm_only_flashing(struct device *dev) static void pch_fixups(struct device *dev) { +#if CONFIG_PMCON_RAMINIT_REVERSED u8 gen_pmcon_2; /* Indicate DRAM init done for MRC S3 to know it can resume */ gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); gen_pmcon_2 |= (1 << 7); pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); +#endif /* * Enable DMI ASPM in the PCH @@ -537,6 +629,9 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + if (pch_silicon_type() == PCH_TYPE_MOBILE5) + mobile5_pm_init (dev); + /* IO APIC initialization. */ pch_enable_apic(dev); @@ -556,6 +651,8 @@ static void lpc_init(struct device *dev) case PCH_TYPE_PPT: /* PantherPoint */ ppt_pm_init(dev); break; + case PCH_TYPE_MOBILE5: + break; default: printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); } @@ -700,7 +797,7 @@ static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c52, 0x1c54, 0x1e55, 0x1c56, 0x1e57, 0x1c5c, - 0x1e5d, 0x1e5e, 0x1e5f, + 0x1e5d, 0x1e5e, 0x1e5f, 0x3b07, 0 }; static const struct pci_driver pch_lpc __pci_driver = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..123fc73 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -724,10 +724,13 @@ static void intel_me_init(device_t dev) break; #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); + if (dev->device == 0x1c3a) + { + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); + } #endif /* @@ -768,10 +771,14 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64, + 0 }; + + static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c3a, + .devices = pci_device_ids }; #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index aaeb24d..6e2062d 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -194,6 +194,7 @@ struct mei_header { #define MKHI_MDES_ENABLE 0x09 #define MKHI_GET_FW_VERSION 0x02 +#define MKHI_SET_UMA 0x08 #define MKHI_END_OF_POST 0x0c #define MKHI_FEATURE_OVERRIDE 0x14 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7f64571..f533bc4 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -22,8 +22,9 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H /* PCH types */ -#define PCH_TYPE_CPT 0x1c /* CougarPoint */ -#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_CPT 0x1c /* CougarPoint */ +#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_MOBILE5 0x3b /* PCH stepping values for LPC device */ #define PCH_STEP_A0 0 @@ -73,6 +74,9 @@ void pch_log_state(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); +int smbus_write_byte(unsigned device, unsigned address, u8 data); +int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); +int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); int early_spi_read(u32 offset, u32 size, u8 *buffer); #endif #endif @@ -150,54 +154,22 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ +#define SKPAD_ACPI_S3_MAGIC 0xcafed00d +#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe + /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -342,6 +314,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ #define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_UNKIP 16 #define D31IP_SMIP 12 /* SMBUS Pin */ #define D31IP_SIP 8 /* SATA Pin */ #define D30IP 0x3104 /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..9655711 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <delay.h> #include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; @@ -96,27 +97,26 @@ static void sata_init(struct device *dev) ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if(config->sata_ahci) { u32 abar; + int i; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); + udelay (1000); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); + pci_write_config8(dev, INTR_LN, config->sata_irq_line); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_PRI, config->ide_tim_pri); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + pci_write_config16(dev, IDE_SDMA_CNT, config->ide_sdma_cnt); + pci_write_config16(dev, IDE_SDMA_TIM, config->ide_sdma_tim); /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config32(dev, IDE_CONFIG, config->ide_config); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); @@ -126,10 +126,14 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + ((config->sata_port_map ^ 0x3f) << 24) | 0x183 | (config->set98 << 30)); + if (config->set98) + pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + udelay (1000); + printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); @@ -143,6 +147,16 @@ static void sata_init(struct device *dev) << 20; } write32(abar + 0x00, reg32); + + /* AHCI enable. */ + for (i = 0; i < 5; i++) + { + write32(abar + 0x04, read32 (abar + 0x04) | 0x80000000); + mdelay (1); + if (read32 (abar + 0x04) & 0x80000000) + break; + } + /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ @@ -212,13 +226,14 @@ static void sata_init(struct device *dev) config->sata_port1_gen3_tx); /* Additional Programming Requirements */ - sir_write(dev, 0x04, 0x00001600); - sir_write(dev, 0x28, 0xa0000033); + sir_write(dev, 0x04, config->sir4); + sir_write(dev, 0x28, config->sir28); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; - reg32 |= 0x5555aa; + reg32 |= config->sir54; + sir_write(dev, 0x54, reg32); - sir_write(dev, 0x64, 0xcccc8484); + sir_write(dev, 0x64, config->sir64); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0xcccc; @@ -226,9 +241,10 @@ static void sata_init(struct device *dev) reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); sir_write(dev, 0x84, 0x001c7000); - sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0x88, config->sir88); sir_write(dev, 0xa0, 0x001c7000); // a4 sir_write(dev, 0xc4, 0x0c0c0c0c); @@ -287,7 +303,7 @@ static struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, 0x1e00, 0x1e01, 0x1e02, 0x1e03, - 0 }; + 0x3b2e, 0 }; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 4786d8b..ad7c8f9 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -100,7 +100,7 @@ static struct device_operations smbus_ops = { .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 }; +static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 }; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/bd82x6x/smbus.h b/src/southbridge/intel/bd82x6x/smbus.h index 81e5949..d6e4ce5 100644 --- a/src/southbridge/intel/bd82x6x/smbus.h +++ b/src/southbridge/intel/bd82x6x/smbus.h @@ -98,3 +98,147 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add return byte; } +#ifdef __PRE_RAM__ + +static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) +{ + unsigned char global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(data, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + if (global_status_register != (1 << 1)) + return SMBUS_ERROR; + + return 0; +} + +static int do_smbus_block_write(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, const u8 *buf) +{ + u8 status; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* set number of bytes to transfer */ + outb(bytes, smbus_base + SMBHSTDAT0); + + outb(*buf++, smbus_base + SMBBLKDAT); + bytes--; + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + outb(*buf++, smbus_base + SMBBLKDAT); + outb(status, smbus_base + SMBHSTSTAT); + } + } while(status & 0x01); + + return 0; +} + +static int do_smbus_block_read(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, u8 *buf) +{ + u8 status; + int bytes_read = 0; + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + *buf = inb(smbus_base + SMBBLKDAT); + buf++; + bytes_read++; + outb(status, smbus_base + SMBHSTSTAT); + if (--bytes == 1) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | 0x20, + smbus_base + SMBHSTCTL); + } + } + } while(status & 0x01); + + return bytes_read; +} +#endif diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..26553fe 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -315,7 +315,8 @@ static inline int get_ich_version(uint16_t device_id) if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) + || device_id == 0x3b07) return 9; return 0; diff --git a/src/southbridge/intel/bd82x6x/thermal.c b/src/southbridge/intel/bd82x6x/thermal.c new file mode 100644 index 0000000..c1040c5 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/thermal.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "pch.h" +#include <usbdebug.h> +#include <arch/io.h> + +static void thermal_init(struct device *dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "Thermal init start.\n"); + + res = find_resource(dev, 0x10); + if (!res) return; + + write32 (res->base + 4, 0x3a2b); + write8 (res->base + 0xe, 0x40); + write32 (res->base + 0x12, 0x1a40); + write16 (res->base + 0x16, 0x7746); + write16 (res->base + 0x1a, 0x10f0); + write16 (res->base + 0x56, 0xffff); + write16 (res->base + 0x64, 0xffff); + write16 (res->base + 0x66, 0xffff); + write16 (res->base + 0x68, 0xfa); + + write8 (res->base + 1, 0xb8); + + printk(BIOS_DEBUG, "Thermal init done.\n"); +} + + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations thermal_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = thermal_init, + .scan_bus = 0, + .ops_pci = &pci_ops, +}; + +static const unsigned short pci_device_ids[] = { 0x3b32, 0 }; + +static const struct pci_driver pch_thermal __pci_driver = { + .ops = &thermal_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 79a43bd..22ab83b 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -28,16 +28,17 @@ void enable_usbdebug(unsigned int port) { u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ + device_t dev = PCI_DEV(0, CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC); + device_t bdev = PCI_DEV(0, 0, 0); /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + pci_write_config16(bdev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Force ownership of the Debug Port to the EHCI controller. */ - printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); @@ -47,6 +48,6 @@ void enable_usbdebug(unsigned int port) /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) { - /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ + /* Not needed, the ICH* southbridges hardcode physical USB port 2. */ } diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index aec230c..4723ce9 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -36,6 +36,17 @@ static void usb_ehci_init(struct device *dev) RCBA32(0x35b0) = reg32; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); + + if (dev->device == 0x3b34 || dev->device == 0x3b3c) + { + pci_write_config32 (dev, 0x84, 0x130c8911); + pci_write_config32 (dev, 0x88, 0xa0); + pci_write_config32 (dev, 0xf4, 0x80808588); + pci_write_config32 (dev, 0xf4, 0x00808588); + pci_write_config32 (dev, 0xf4, 0x00808588); + pci_write_config32 (dev, 0xfc, 0x301b1728); + } + reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; //reg32 |= PCI_COMMAND_SERR; @@ -68,22 +79,28 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic static void usb_ehci_set_resources(struct device *dev) { #if CONFIG_USBDEBUG - struct resource *res; - u32 base; - u32 usb_debug; + u32 usb_debug = 0; - usb_debug = get_ehci_debug(); - set_ehci_debug(0); + if (dev->path.pci.devfn == PCI_DEVFN (CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC)) + { + usb_debug = get_ehci_debug(); + set_ehci_debug(0); + } #endif pci_dev_set_resources(dev); #if CONFIG_USBDEBUG - res = find_resource(dev, 0x10); - set_ehci_debug(usb_debug); - if (!res) return; - base = res->base; - set_ehci_base(base); - report_resource_stored(dev, res, ""); + if (dev->path.pci.devfn == PCI_DEVFN (CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC)) + { + struct resource *res; + u32 base; + res = find_resource(dev, 0x10); + if (!res) return; + base = res->base; + set_ehci_debug(usb_debug); + set_ehci_base(base); + report_resource_stored(dev, res, ""); + } #endif } @@ -103,7 +120,7 @@ static struct device_operations usb_ehci_ops = { }; static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, - 0 }; + 0x3b34, 0x3b3c, 0 }; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops,

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Patch merged into coreboot/master: a8db717 inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit a8db717d4af799fabd26383e6a748de94318d280 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 31 22:02:16 2013 +0200 inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t` When buidling inteltool with GCC, the following warning is printed. $ make […] gcc -O2 -g -Wall -W -c -o memory.o memory.c memory.c: In function ‘print_mchbar’: memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat] […] This was introduced in commit »inteltool: Add support for H65 Express chipset« (c7fc4422) [1]. Address this warning, by using `%llx` instead of `%lx`. [1] http://review.coreboot.org/1258 Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2994 Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 2 01:22:51 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Sun Mar 31 22:38:33 2013, giving +2 See http://review.coreboot.org/2994 for details. -gerrit

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New patch to review for coreboot: 438f77d Add PXE ROM on config menu
by Siyuan Wang 03 Apr '13

03 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3013 -gerrit commit 438f77dfdd0b3e1dd9d5f8ee895204522d94055e Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 3 17:02:58 2013 +0800 Add PXE ROM on config menu Adding a pxe rom manually is inconvenient. With this patch, PXE ROM can be added automatically. I have tested this patch on AMD Parmer and Thatcher with iPXE. Change-Id: I2c4fc73fd9ae6c979f0af2290d410935f600e2c8 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/arch/x86/Makefile.inc | 3 +++ src/device/Kconfig | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bbf2336..ee2bc47 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,6 +113,9 @@ endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB_ELF) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) endif +ifeq ($(CONFIG_PXE_ROM),y) + $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/device/Kconfig b/src/device/Kconfig index 159bc0e..12ff3aa 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -467,3 +467,32 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. endmenu + +menu "PXE ROM" +config PXE_ROM + bool "Add a PXE ROM image" + help + Select this option if you have a PXE ROM image that you would + like to add to your ROM. + +config PXE_ROM_FILE + string "PXE ROM filename" + depends on PXE_ROM + default "10ec8168.rom" + help + The path and filename of the file to use as PXE ROM. + +config PXE_ROM_ID + string "network card PCI IDs" + depends on PXE_ROM + default "10ec,8168" + help + The comma-separated PCI vendor and device ID that would associate + your PXE ROM to your network card. + + Example: 10ec,8168 + + In the above example 10ec is the PCI vendor ID (in hex, but without + the "0x" prefix) and 8168 specifies the PCI device ID of the + network card (also in hex, without "0x" prefix). +endmenu

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Patch set updated for coreboot: 830d213 inteltool: Cast to `intptr_t` instead of `uint64_t`
by Paul Menzel 03 Apr '13

03 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3002 -gerrit commit 830d213b3da006c488a83e1fcae36e7c0b087ed0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 1 18:26:58 2013 +0200 inteltool: Cast to `intptr_t` instead of `uint64_t` When building inteltool under x86-32, the following warnings are shown. $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] Nico Huber commented the following [1]. I don't see those warnings because I build for x86-64. I guess they could be fixed by casting to `ptrdiff_t` (from stddef.h) instead of `uint64_t`. And indeed, using `ptrdiff_t` fixes the warning. But as Stefan Reinauer commented in [2], `intptr_t` is more appropriate as this is just a pointer and no pointer difference. So `intptr_t` is taken, which fixes these issues warned about too. These warnings were introduced in commit »inteltool: Add support for dumping AMB registers« (4b7b320f) [3]. [1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG [2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c [3] http://review.coreboot.org/525 Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/amb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c index a3ee01d..a1761ee 100644 --- a/util/inteltool/amb.c +++ b/util/inteltool/amb.c @@ -17,7 +17,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - +#include <stddef.h> #include <stdio.h> #include <stdlib.h> #include "inteltool.h" @@ -28,7 +28,7 @@ static uint32_t amb_read_config32(volatile void *base, int fn, int reg) { - return *(uint32_t *)(AMB_ADDR((uint64_t)base, fn, reg)); + return *(uint32_t *)(AMB_ADDR((intptr_t)base, fn, reg)); } static void amb_printreg32(volatile void *base, int fn, int reg, @@ -42,7 +42,7 @@ static void amb_printreg32(volatile void *base, int fn, int reg, static uint16_t amb_read_config16(volatile void *base, int fn, int reg) { - return *(uint16_t *)(AMB_ADDR((uint64_t)base, fn, reg)); + return *(uint16_t *)(AMB_ADDR((intptr_t)base, fn, reg)); } static void amb_printreg16(volatile void *base, int fn, int reg, @@ -57,7 +57,7 @@ static void amb_printreg16(volatile void *base, int fn, int reg, static uint8_t amb_read_config8(volatile void *base, int fn, int reg) { - return *(uint8_t *)(AMB_ADDR((uint64_t)base, fn, reg)); + return *(uint8_t *)(AMB_ADDR((intptr_t)base, fn, reg)); } static void amb_printreg8(volatile void *base, int fn, int reg,

1 0

New patch to review for coreboot: 8a4eab9 Partially revert "AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`"
by Jens Rottmann 03 Apr '13

03 Apr '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3012 -gerrit commit 8a4eab961e543cc679d048e9523f3f992180debf Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Apr 3 10:12:55 2013 +0200 Partially revert "AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`" Commit 5d741567 added a prototype to broadcom.c to fix a warning. This part is fine. It also changed mainboard.c to #include broadcom.c. But broadcom.c is already in Makefile.inc, now building will fail because the linker gets broadcom_init() twice. Undo the change to mainboard.c but keep the change to broadcom.c. Change-Id: Ieccc098f477ffacccf4174056998034a220a9744 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/inagua/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 7e9f1d9..dc23007 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -26,8 +26,8 @@ #include <device/pci_def.h> #include <southbridge/amd/sb800/sb800.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ -// #include "broadcom.c" /* broadcom_init() */ +void broadcom_init(void); void set_pcie_reset(void); void set_pcie_dereset(void);

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coreboot-gerrit April 2013