coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c6f2722 sandybridge: enable ROM caching
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit c6f27226a84434182771dbbcd593d223072801f7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 3 09:56:57 2013 -0500 sandybridge: enable ROM caching If ROM caching is selected the sandybridge chipset code will will enable ROM caching after all other CPU threads are brought up. Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Apr 3 18:53:12 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 3 19:26:24 2013, giving +2 See http://review.coreboot.org/3017 for details. -gerrit

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Patch merged into coreboot/master: 23f5016 haswell: enable ROM caching
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit 23f50166c64be0c1d3656ca67839843bf11a5274 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 3 09:55:22 2013 -0500 haswell: enable ROM caching If ROM caching is selected the haswell CPU initialization code will enable ROM caching after all other CPU threads are brought up. Change-Id: I75424bb75174bfeca001468c3272e6375e925122 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Apr 3 18:28:38 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 3 19:26:05 2013, giving +2 See http://review.coreboot.org/3016 for details. -gerrit

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Patch merged into coreboot/master: 13cc952 haswell: keep ROM cache enabled
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit 13cc952a13ea29d9c5016a861d97da8326c87c4e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 1 16:49:31 2013 -0500 haswell: keep ROM cache enabled The MP code on haswell was mirroring the BSPs MTRRs. In addition it was cleaning up the ROM cache so that the MTRR register values were the same once the OS was booted. Since the hyperthread sibling of the BSP was going through this path the ROM cache was getting torn down once the hyperthread was brought up. That said, there was no differnce in observed boot time keeping the ROM cache enabled. Change-Id: I2a59988fcfeea9291202c961636ea761c2538837 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3008 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Apr 3 18:04:58 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 3 19:25:41 2013, giving +2 See http://review.coreboot.org/3008 for details. -gerrit

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Patch merged into coreboot/master: 0f0fe10 haswell: use new interface to disable rom caching
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit 0f0fe100cb27770d615a70d5a78310ad47cb1abf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 1 15:40:45 2013 -0500 haswell: use new interface to disable rom caching The haswell code was using the old assumption of which MTRR was used for the ROM cache. Now that there is an API for doing this use it as the old assumption is no longer valid. Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Apr 3 17:36:21 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 3 19:25:16 2013, giving +2 See http://review.coreboot.org/3007 for details. -gerrit

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Patch merged into coreboot/master: d46161e intel/microcode.h: Fix typo in comment: micr*o*code
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit d46161e9eaaca8ec1d95f52461feb9647a99d5f3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 30 21:01:13 2013 +0100 intel/microcode.h: Fix typo in comment: micr*o*code Introduced in commit »intel microcode: split up microcode loading stages« (98ffb426) [1]. [1] http://review.coreboot.org/2778 Change-Id: I626508b10f3998b43aaabd49853090b36f5d3eb0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2992 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 2 06:13:06 2013, giving +1 See http://review.coreboot.org/2992 for details. -gerrit

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Patch merged into coreboot/master: 64a7ed6 Add PXE ROM selection to Kconfig menu
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit 64a7ed6dfae7e8d780930aad153f15e2c48753c3 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 3 17:02:58 2013 +0800 Add PXE ROM selection to Kconfig menu Adding a pxe rom manually is inconvenient. With this patch, PXE ROM can be added automatically by selecting PXE_ROM in Kconfig. I have tested this patch on AMD Parmer and Thatcher with iPXE. iPXE would be a boot device in Seabios when pressing F12. iPXE works well with coreboot and Seabios. Change-Id: I2c4fc73fd9ae6c979f0af2290d410935f600e2c8 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/3013 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 3 16:04:09 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Apr 3 17:04:26 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Apr 3 18:01:44 2013, giving +2 See http://review.coreboot.org/3013 for details. -gerrit

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Patch merged into coreboot/master: b81754b ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors
by gerrit＠coreboot.org 03 Apr '13

03 Apr '13

the following patch was just integrated into master: commit b81754becae18d54915a3d724ee5c0f1dfb096d5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Apr 3 11:36:50 2013 +0200 ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors Now that the ASRock E350M1 builds without any warnings, remove the config option `WARNINGS_ARE_ERRORS` set to no by default from the file `Kconfig` so warnings are treated as errors to prevent code from being added in the future introducing warnings. Change-Id: Idfecfb1434158969334a4b37972b5fc6fd76e72a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3014 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Apr 3 14:57:59 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Apr 3 17:20:03 2013, giving +2 See http://review.coreboot.org/3014 for details. -gerrit

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New patch to review for coreboot: 5ec50ef mtrr: add rom caching comment about hyperthreads
by Aaron Durbin 03 Apr '13

03 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3018 -gerrit commit 5ec50ef9f0339df0bae1fd2185e31153ae439a48 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 3 09:57:53 2013 -0500 mtrr: add rom caching comment about hyperthreads Explicitly call out the effects of hyperthreads running the MTRR code and its impact on the enablement of ROM caching. Change-Id: I14b8f3fdc112340b8f483f2e554c5680576a8a7c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/mtrr.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 15a5cad..747c1e9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -74,7 +74,11 @@ int x86_mtrr_check(void); /* ROM caching can be used after variable MTRRs are set up. Beware that * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. */ + * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that + * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the + * rom caching will be disabled if all thread run the MTRR code. Therefore, + * one needs to call x86_mtrr_enable_rom_caching() after all threads of the + * same core have run the MTRR code. */ #if CONFIG_CACHE_ROM void x86_mtrr_enable_rom_caching(void); void x86_mtrr_disable_rom_caching(void);

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New patch to review for coreboot: a7e6b04 sandybridge: enable ROM caching
by Aaron Durbin 03 Apr '13

03 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3017 -gerrit commit a7e6b0428be611e36c265b87e9ef9ef2c8bf1901 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 3 09:56:57 2013 -0500 sandybridge: enable ROM caching If ROM caching is selected the sandybridge chipset code will will enable ROM caching after all other CPU threads are brought up. Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/sandybridge/northbridge.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index c39933f..b8022b8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -25,6 +25,7 @@ #include <delay.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -486,6 +487,8 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev)

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New patch to review for coreboot: dfd02e5 haswell: enable ROM caching
by Aaron Durbin 03 Apr '13

03 Apr '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3016 -gerrit commit dfd02e5d90a03f711063f1dc67be1531fbe518e4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 3 09:55:22 2013 -0500 haswell: enable ROM caching If ROM caching is selected the haswell CPU initialization code will enable ROM caching after all other CPU threads are brought up. Change-Id: I75424bb75174bfeca001468c3272e6375e925122 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 0bb11a8..18636b0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -551,6 +551,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); + + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = {

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coreboot-gerrit April 2013