coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 916c0cc superiotool: add CR dump for W83627UHG = NCT6627UD
by Frank Rysanek 05 Apr '13

05 Apr '13

Frank Rysanek (Frantisek.Rysanek(a)post.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3027 -gerrit commit 916c0cc6a4448a81cb513fb6a630ae842c0def06 Author: Frank Rysanek <Frantisek.Rysanek(a)post.cz> Date: Fri Apr 5 10:44:10 2013 +0200 superiotool: add CR dump for W83627UHG = NCT6627UD This commit adds "register dump capability" to superiotool for a specific chip by Winbond/Nuvoton: the W83627UHG AKA NCT6627UD (same chip, different package). In other words, it fills in the "CR map" definitions in winbond.c, which so far have been void for this chip. Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56 Signed-off-by: Frank Rysanek <Frantisek.Rysanek(a)post.cz> --- util/superiotool/winbond.c | 66 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index 96b082e..aca6b57 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -233,7 +233,71 @@ static const struct superio_registers reg_table[] = { {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00, EOT}}, {EOT}}}, - {0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */ + {0xa23, "W83627UHG = NCT6627UD", { /* TODO: Not yet in sensors-detect */ + {NOLDN, NULL, /* CR2B (485) is only valid for chip rev.E */ + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0xa2,NANA,0xff,0xF0,MISC,0x00,MISC,RSVD,0x00, + 0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, + EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, + EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x2, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x3, "UART B", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}}, + {0x6, "UART C", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xE0,0x04,0x00,EOT}}, + {0x7, "GPIO 3, GPIO 4", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,EOT}}, + {0x8, "WDTO#, PLED, GPIO 5,6 & GPIO Base Address", + {0x30,0x60,0x61, + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7, + 0xF5,0xF6,0xF7,EOT}, + {0x02,0x00,0x00, + 0xFF,0x00,0x00,0x00,0xFF,0x1F,0x00,0x00, + 0x00,0x00,0x00,EOT}}, + {0x9, "GPIO 1, GPIO 2 and SUSLED", + {0x30, + 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xF3,EOT}, + {0x00, + 0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,EOT}}, + {0xa, "ACPI", + {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x00,0x00,0x01,0x00,0xff,0x08,0x00,0x00,0x1c,0x00, + RSVD,RSVD,0x3e,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xb, "Hardware monitor", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x00,0x00,RSVD,RSVD,0x00,EOT}}, + {0xc, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xf1,0xf2,0xf3,0xfe,0xff,EOT}, + {0x00,0x48,0x48,0x48,0x48,0x00,RSVD,RSVD,0x00, + 0x48,0x50,0x10,0x23,0x5A,EOT}}, + {0xD, "UART D", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x02,0xe0,0x03,0x00,EOT}}, + {0xE, "UART E", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0xe8,0x04,0x00,EOT}}, + {0xF, "UART F", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x02,0xe8,0x03,0x00,EOT}}, {EOT}}}, {0xa51, "W83667HG", { /* See also: http://lists.lm-sensors.org/pipermail/lm-sensors/2008-July/023683.html */

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New patch to review for coreboot: 091e71f inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
by Paul Menzel 05 Apr '13

05 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3026 -gerrit commit 091e71f569c07e03180e3e8c9caf00c1fa562a30 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Apr 5 00:12:21 2013 +0200 inteltool: cpu.c: Use conversion specifier `u` for unsigned integers Cppcheck [1], a static code analysis tool, warns about the following. $ cppcheck --version Cppcheck 1.59 $ cppcheck --enable=all . […] Checking cpu.c... [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. […] And indeed, `core` is an unsigned integer and `man 3 printf` tells the following about conversion specifiers. d, i The int argument is converted to signed decimal notation. […] o, u, x, X The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or unsigned hexadecimal (x and X) notation. So use `u` and Cppcheck does not complain anymore. [1] http://cppcheck.sourceforge.net/ Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index e73f096..80e1ed6 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -948,7 +948,7 @@ int print_intel_core_msrs(void) #ifndef __DARWIN__ char msrfilename[64]; memset(msrfilename, 0, 64); - sprintf(msrfilename, "/dev/cpu/%d/msr", core); + sprintf(msrfilename, "/dev/cpu/%u/msr", core); fd_msr = open(msrfilename, O_RDWR); @@ -959,7 +959,7 @@ int print_intel_core_msrs(void) break; #endif if (cpu->num_per_core_msrs) - printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); + printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core); for (i = 0; i < cpu->num_per_core_msrs; i++) { msr = rdmsr(cpu->per_core_msrs[i].number);

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Patch set updated for coreboot: 73a2008 inteltool: clean up file descriptors a bit
by Stefan Tauner 05 Apr '13

05 Apr '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3025 -gerrit commit 73a20080249239a7b3fd3e04d910335f780b5040 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Apr 5 01:23:32 2013 +0200 inteltool: clean up file descriptors a bit Paul Menzel reported that Cppcheck 1.59 reported an unused variable io_fd. While that is true, the underlying issue is that the file descriptors are not closed properly at the end. "a bit" refers to the numerous exit calls all around that of course circumvent the cleanup. Arguably one could live without cleaning up because it is done automatically anyway. Change-Id: Ifd46314672ca431d820fb3842bfbf12decc90f9b Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 2396eb0..6c073ce 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -26,9 +26,7 @@ #include <fcntl.h> #include <sys/mman.h> #include "inteltool.h" -#if defined(__FreeBSD__) #include <unistd.h> -#endif /* * http://pci-ids.ucw.cz/read/PC/8086 @@ -307,9 +305,6 @@ int main(int argc, char *argv[]) #if defined(__FreeBSD__) int io_fd; -#endif - -#if defined(__FreeBSD__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { perror("/dev/io"); #else @@ -450,5 +445,12 @@ int main(int argc, char *argv[]) // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" pci_cleanup(pacc); +#if defined(__FreeBSD__) + close(io_fd); +#endif + +#ifndef __DARWIN__ + close(fd_mem); +#endif return 0; }

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New patch to review for coreboot: bad39f9 inteltool: clean up file descriptors a bit
by Stefan Tauner 05 Apr '13

05 Apr '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3025 -gerrit commit bad39f9d389d17a30d8460c26e7fd4018b169a5c Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Apr 5 01:23:32 2013 +0200 inteltool: clean up file descriptors a bit Paul Menzel reported that Cppcheck 1.59 reported an unused variable io_fd. While that is true, the underlying issue is that the file descriptors are not closed properly at the end. "a bit" referes to the numerous exit calls all around that of course circumvent the cleanup. Arguably one could live without cleaning up because it is done automatically anyway. Change-Id: Ifd46314672ca431d820fb3842bfbf12decc90f9b Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/inteltool.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 2396eb0..6c073ce 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -26,9 +26,7 @@ #include <fcntl.h> #include <sys/mman.h> #include "inteltool.h" -#if defined(__FreeBSD__) #include <unistd.h> -#endif /* * http://pci-ids.ucw.cz/read/PC/8086 @@ -307,9 +305,6 @@ int main(int argc, char *argv[]) #if defined(__FreeBSD__) int io_fd; -#endif - -#if defined(__FreeBSD__) if ((io_fd = open("/dev/io", O_RDWR)) < 0) { perror("/dev/io"); #else @@ -450,5 +445,12 @@ int main(int argc, char *argv[]) // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" pci_cleanup(pacc); +#if defined(__FreeBSD__) + close(io_fd); +#endif + +#ifndef __DARWIN__ + close(fd_mem); +#endif return 0; }

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Patch set updated for coreboot: 0194586 samsung/exynos5: init display port and LCD
by David Hendricks 05 Apr '13

05 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2931 -gerrit commit 01945869655858c409f3288f8ef1f8d6ca66683b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: init display port and LCD This adds resources for the display port controller and attempts to go thru the init sequence. TODO: split this apart when we have something working... Change-Id: I2caa350f8c0e681f71e9646898dcdb36e10115b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/Makefile.inc | 1 - src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 - .../exynos5-common/displayport/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/displayport/chip.h | 40 ---- .../exynos5-common/displayport/displayport.c | 107 ----------- src/cpu/samsung/exynos5-common/exynos-fb.c | 7 +- src/cpu/samsung/exynos5-common/i2c.c | 10 +- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 1 + src/cpu/samsung/exynos5250/Kconfig | 2 +- src/cpu/samsung/exynos5250/chip.h | 40 ++++ src/cpu/samsung/exynos5250/cpu.c | 81 +++++++- src/mainboard/google/snow/devicetree.cb | 37 ++-- src/mainboard/google/snow/ramstage.c | 203 ++++++++++++++++++++- 13 files changed, 339 insertions(+), 194 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index 7abd75c..eb08fb6 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -22,4 +22,3 @@ ramstage-y += i2c.c ramstage-y += s5p-dp-reg.c ramstage-y += exynos-fb.c -subdirs-y += displayport diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig deleted file mode 100644 index 26d1422..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config EXYNOS_DISPLAYPORT - bool diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc deleted file mode 100644 index 7c52eaf..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c - diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h deleted file mode 100644 index 53b7836..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H -#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H - -struct cpu_samsung_exynos5_common_displayport_config { - /* special magic numbers! */ - int clkval_f; - int upper_margin; - int lower_margin; - int vsync; - int left_margin; - int right_margin; - int hsync; - - int xres; - int yres; - int bpp; - - u32 lcdbase; -}; - -#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c deleted file mode 100644 index 1c08bc7..0000000 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <device/device.h> - -/* we distinguish a display port device from a raw graphics device because there are - * dramatic differences in startup depending on graphics usage. To make startup fast - * and easier to understand and debug we explicitly name this common case. The alternate - * approach, involving lots of machine and callbacks, is hard to debug and verify. - */ -static void exynos_displayport_init(void) -{ - struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info; - /* put these on the stack. If, at some point, we want to move this code to a - * pre-ram stage, it will be much easier. - */ - vidinfo_t vi; - struct exynos5_fimd_panel panel; - void *lcdbase; - - memset(vi, 0, sizeof(vi)); - memset(panel, 0, sizeof(panel)); - - panel.is_dp = 1; /* Display I/F is eDP */ - /* while it is true that we did a memset to zero, - * we leave some 'set to zero' entries here to make - * it clear what's going on. Graphics is confusing. - */ - panel.is_mipi = 0; - panel.fixvclk = 0; - panel.ivclk = 0; - panel.clkval_f = conf->clkval_f; - panel.upper_margin = conf->upper_margin; - panel.lower_margin = conf->lower_margin; - panel.vsync = conf->vsync; - panel.left_margin = conf->left_margin; - panel.right_margin = conf->right_margin; - panel.hsync = conf->hsync; - - vi->vl_col = conf->xres; - vi->fl_row = conf->yres; - vi->vl_bpix = conf->bpp; - vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ - - lcdbase = conf->lcdbase; - printk(BIOS_DEBUG, "Initializing exynos VGA\n"); - ret = lcd_ctrl_init(&vi, &panel, lcdbase); -#if 0 - ret = board_dp_lcd_vdd(blob, &wait_ms); - ret = board_dp_bridge_setup(blob, &wait_ms); - while (tries < 5) { - ret = board_dp_bridge_init(blob, &wait_ms); - ret = board_dp_hotplug(blob, &wait_ms); - if (ret) { - ret = board_dp_bridge_reset(blob, &wait_ms); - continue; - } - ret = dp_controller_init(blob, &wait_ms); - ret = board_dp_backlight_vdd(blob, &wait_ms); - ret = board_dp_backlight_pwm(blob, &wait_ms); - ret = board_dp_backlight_en(blob, &wait_ms); - } -#endif -} - -static void exynos_displayport_noop(device_t dummy) -{ -} - -static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, - .init = exynos_displayport_init, - .scan_bus = exynos_displayport_noop, -}; - -static void exynos_displayport_enable(struct device *dev) -{ - if (dev->link_list != NULL) - dev->ops = &exynos_displayport_operations; -} - -struct chip_operations drivers_i2c_exynos_displayport_ops = { - CHIP_NAME("exynos displayport") - .enable_dev = exynos_displayport_enable; -}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..d8cd99b 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -582,11 +582,10 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, { int ret = 0; - //vi->res = panel_info->vl_col; - //vi->yres = panel_info->vl_row; - fimd_bypass(); + printk(BIOS_SPEW, "fimd_bypass\n"); fb_init(panel_info, lcdbase, panel_data); + printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5-common/i2c.c b/src/cpu/samsung/exynos5-common/i2c.c index 7384b50..e09496d 100644 --- a/src/cpu/samsung/exynos5-common/i2c.c +++ b/src/cpu/samsung/exynos5-common/i2c.c @@ -93,6 +93,7 @@ void i2c_set_early_reg(unsigned int base) g_early_i2c_config = (struct s3c24x0_i2c *)base; } +#include <console/console.h> static struct s3c24x0_i2c_bus *get_bus(int bus_idx) { /* If an early i2c config exists we just use that */ @@ -105,7 +106,7 @@ static struct s3c24x0_i2c_bus *get_bus(int bus_idx) if (bus_idx < i2c_busses) return &i2c_bus[bus_idx]; - debug("Undefined bus: %d\n", bus_idx); + printk(BIOS_ERR, "Undefined bus: %d, busses: %d\n", bus_idx, i2c_busses); return NULL; } @@ -233,6 +234,7 @@ int i2c_set_bus_num(unsigned int bus) struct s3c24x0_i2c_bus *i2c; i2c = get_bus(bus); + printk(BIOS_DEBUG, "%s: bus: %u, i2c: %p\n", __func__, bus, i2c); if (!i2c) return -1; g_current_bus = bus; @@ -522,17 +524,21 @@ int i2c_probe(unsigned char chip) return ret != I2C_OK; } +#include <console/console.h> /* FIXME: remove this */ int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; int ret; + printk(BIOS_DEBUG, "%s: entered, chip: 0x%02x, addr: 0x%02x\n", + __func__, chip, addr); if (alen > 4) { debug("I2C read: addr len %d not supported\n", alen); return 1; } + printk(BIOS_DEBUG, "%s: checkpoint 1\n", __func__); if (alen > 0) { xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; @@ -559,8 +565,10 @@ int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buf i2c = get_bus(g_current_bus); if (!i2c) return -1; + printk(BIOS_DEBUG, "%s: checkpoint 2\n", __func__); ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], alen, buffer, len); + printk(BIOS_DEBUG, "%s: bus: %u, ret %d\n", __func__, i2c->bus_num, ret); if (ret) { debug("I2c read: failed %d\n", ret); return 1; diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 67c1990..2988d5d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ +struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index ca306b6..cc67abd 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -96,4 +96,4 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex - default 0x100000 + default 0x4000000 diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 4bb06e8..0a85322 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,13 +1,77 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> #include <device/device.h> -#include <arch/cache.h> -#include <cpu/samsung/exynos5250/cpu.h> +#include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "chip.h" +#include "cpu.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + unsigned long int fb_size; + u32 lcdbase; + + printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + /* + * The size is a magic number from hardware. Allocate enough for the + * frame buffer and color map. + */ + fb_size = conf->xres * conf->yres * sizeof(unsigned long); + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); + printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); + mmio_resource(dev, 0, lcdbase/KiB, 64); + vi.cmap = (void *)lcdbase; + + lcdbase += 64*KiB; + mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); + printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); +} + static void cpu_init(device_t dev) { + exynos_displayport_init(dev); ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); } @@ -18,22 +82,19 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, .set_resources = cpu_noop, - .enable_resources = cpu_noop, - .init = cpu_init, + .enable_resources = cpu_init, + .init = cpu_noop, .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_exynos5250_dev(device_t dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_ops; - } + dev->ops = &cpu_ops; } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_dev, + .enable_dev = enable_exynos5250_dev, }; void exynos5250_config_l2_cache(void) diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..41ed45e 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,30 +17,17 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - -device cpu_cluster 0 on -end - -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x10000000" - end -end + device cpu_cluster 0 on end + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" end diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 9081629..0618a86 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -18,13 +18,20 @@ */ #include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> /* FIXME: for backlight FET enable */ #include <cbmem.h> +#include <delay.h> +#include <arch/cache.h> #include <arch/exception.h> +#include <arch/gpio.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/gpio.h> #include <cpu/samsung/exynos5250/power.h> -#include <arch/cache.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> + /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) @@ -68,3 +75,197 @@ void main(void) hardwaremain(0); } + +/* TODO: transplanted DP stuff, clean up once we have something that works */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ + +static void exynos_dp_bridge_setup(void) +{ +#if 0 + if (fdt_gpio_isvalid(&local.dp_rst)) { + fdtdec_set_gpio(&local.dp_rst, 1); + gpio_cfg_pin(local.dp_rst.gpio, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(local.dp_rst.gpio, EXYNOS_GPIO_PULL_NONE); + udelay(10); + fdtdec_set_gpio(&local.dp_rst, 0); + } +#endif + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); + + gpio_set_value(dp_pd_l, 1); + gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE); + + gpio_set_value(dp_rst_l, 0); + gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE); + udelay(10); + gpio_set_value(dp_rst_l, 1); + + udelay(90000); /* FIXME: this might be unnecessary */ +} + +static void exynos_dp_bridge_init(void) +{ + /* De-assert PD (and possibly RST) to power up the bridge */ + gpio_set_value(dp_pd_l, 1); + gpio_set_value(dp_rst_l, 1); + + /* + * We need to wait for 90ms after bringing up the bridge since there + * is a phantom "high" on the HPD chip during its bootup. The phantom + * high comes within 7ms of de-asserting PD and persists for at least + * 15ms. The real high comes roughly 50ms after PD is de-asserted. The + * phantom high makes it hard for us to know when the NXP chip is up. + */ + udelay(90000); /* FIXME: this might be unnecessary */ +} + +static int exynos_dp_hotplug(void) +{ + /* Check HPD. If it's high, we're all good. */ + if (gpio_get_value(dp_hpd)) + return 0; + return -1; +} + +static void exynos_dp_reset(void) +{ + gpio_set_value(dp_pd_l, 0); + gpio_set_value(dp_rst_l, 0); + /* paranoid delay period (300ms) */ + udelay(300 * 1000); +} + +#define LCD_T5_DELAY_MS 10 +#define LCD_T6_DELAY_MS 10 + +static void snow_backlight_pwm(void) +{ + /*Configure backlight PWM as a simple output high (100% brightness) */ + gpio_direction_output(GPIO_B20, 1); + udelay(LCD_T6_DELAY_MS * 1000); +} + +static void snow_backlight_en(void) +{ + /* * Configure GPIO for LCD_BL_EN */ + gpio_direction_output(GPIO_X30, 1); +} + +#define TPS69050_BUS 4 /* Snow-specific */ + +#define TPS69050_ADDR 0x48 +#define FET1_CTRL 0x0f +#define FET6_CTRL 0x14 + +static void snow_lcd_vdd(void) +{ + uint8_t val = 0xbb; + printk(BIOS_DEBUG, "%s: attempting to enable FET6\n", __func__); + i2c_set_bus_num(TPS69050_BUS); + i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET6_CTRL before: 0x%02x\n", __func__, val); + val |= 1; + i2c_write(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + + i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET6_CTRL after: 0x%02x\n", __func__, val); +// return board_ldo_enable(6); /* Enable FET6, lcd panel */ +} + +static void snow_backlight_vdd(void) +{ + uint8_t val = 0xbb; +// return board_ldo_enable(1); /* Enable FET1, backlight */ + /* FIXME: implement more paranoid tps65090EXYNOS5250_DP1_ADDR fet routine */ +// ret = tps65090_fet_enable(1); + printk(BIOS_DEBUG, "%s: attempting to enable FET1\n", __func__); + i2c_set_bus_num(TPS69050_BUS); + i2c_read(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET1_CTRL before: 0x%02x\n", __func__, val); + val |= 1; + i2c_write(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val)); + udelay(LCD_T5_DELAY_MS * 1000); + + i2c_read(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET1_CTRL after: 0x%02x\n", __func__, val); +} + +//static struct video_info smdk5250_dp_config = { +static struct video_info snow_dp_video_info = { + /* FIXME: fix video_info struct to use const for name */ + .name = (char *)"eDP-LVDS NXP PTN3460", + + .h_sync_polarity = 0, + .v_sync_polarity = 0, + .interlaced = 0, + + .color_space = COLOR_RGB, + .dynamic_range = VESA, + .ycbcr_coeff = COLOR_YCBCR601, + .color_depth = COLOR_8, + + .link_rate = LINK_RATE_2_70GBPS, + .lane_count = LANE_COUNT2, +}; + +/* FIXME: move some place more appropriate */ +#define EXYNOS5250_DP1_BASE 0x145b0000 +#define SNOW_MAX_DP_TRIES 5 + +static void mainboard_init(device_t dev) +{ + int dp_tries; + unsigned int wait_ms; + struct s5p_dp_device dp_device = { + .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, + .video_info = &snow_dp_video_info, + }; + + /* this happens after cpu_init where exynos resources are set */ + /* Set the i2c register address base so i2c works before FDT */ + + /* FIXME: fix the braindead i2c crap leftover from u-boot */ + i2c_set_early_reg(0x12ca0000); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + snow_lcd_vdd(); + exynos_dp_bridge_setup(); + for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { + if (wait_ms) { + udelay(wait_ms); + wait_ms = 0; + } + + exynos_dp_bridge_init(); + if (exynos_dp_hotplug()) { + exynos_dp_reset(); + continue; + } + + if (dp_controller_init(&dp_device, &wait_ms)) + continue; + + snow_backlight_vdd(); + snow_backlight_pwm(); + snow_backlight_en(); + /* if we're here, we're successful */ + break; + } + + if (dp_tries > SNOW_MAX_DP_TRIES) + printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM Chromebook", + .enable_dev = mainboard_enable, +};

1 0

New patch to review for coreboot: 2c52d6a inteltool: use inttypes for prints in memory.c
by Stefan Tauner 05 Apr '13

05 Apr '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3024 -gerrit commit 2c52d6afacf60278f3f3952178adbe49fa536191 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Apr 5 01:15:04 2013 +0200 inteltool: use inttypes for prints in memory.c This fixes at least one warning on my machine where "llx" is replaced by PRIx64. Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/inteltool/memory.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 6847e5c..506620d 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -197,25 +197,25 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) for (i = 0; i < size; i++) { switch (mch_registers[i].size) { case 8: - printf("mchbase+0x%04x: 0x%016llx (%s)\n", + printf("mchbase+0x%04x: 0x%016"PRIx64" (%s)\n", mch_registers[i].addr, *(uint64_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 4: - printf("mchbase+0x%04x: 0x%08x (%s)\n", + printf("mchbase+0x%04x: 0x%08"PRIx32" (%s)\n", mch_registers[i].addr, *(uint32_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 2: - printf("mchbase+0x%04x: 0x%04x (%s)\n", + printf("mchbase+0x%04x: 0x%04"PRIx16" (%s)\n", mch_registers[i].addr, *(uint16_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); break; case 1: - printf("mchbase+0x%04x: 0x%02x (%s)\n", + printf("mchbase+0x%04x: 0x%02"PRIx8" (%s)\n", mch_registers[i].addr, *(uint8_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name); @@ -225,7 +225,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) } else { for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); + printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i)); } }

1 0

New patch to review for coreboot: f79f561 i945: Make it compile with CONFIG_DYNAMIC_CBMEM=y
by Denis Carikli 04 Apr '13

04 Apr '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3023 -gerrit commit f79f561c1e91ab44ca89f654871684dc6ca77a87 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Apr 4 22:57:07 2013 +0200 i945: Make it compile with CONFIG_DYNAMIC_CBMEM=y The get_top_of_ram function was adapted from the same function in raminit.c in the same directory. Change-Id: I4ee6b2a5f44860f51b96aa506398a516930d14f4 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/northbridge/intel/i945/northbridge.c | 47 ++++++++++++++++++++++++++++++++ src/northbridge/intel/i945/raminit.c | 7 +++++ 2 files changed, 54 insertions(+) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c..9e6896a 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -29,8 +29,53 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <arch/acpi.h> +#include "raminit.h" #include "i945.h" +#if CONFIG_DYNAMIC_CBMEM + +unsigned long get_top_of_ram(void) +{ + u32 tom; + device_t dev0, dev2; + + dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); + dev2 = dev_find_slot(0, PCI_DEVFN(2, 0)); + + if (pci_read_config8(dev0, DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(dev2, 0x5c); + } else { + tom = (pci_read_config8(dev0, TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(dev0, ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} + +void *cbmem_top(void) +{ + return (void *)get_top_of_ram(); +} +#endif + static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; @@ -88,6 +133,8 @@ static void pci_domain_set_resources(device_t dev) uint16_t reg16; unsigned long long tomk, tomk_stolen; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; + extern uint64_t high_tables_base; + extern uint64_t high_tables_size; /* Can we find out how much memory we can use at most * this way? diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..e2137d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,10 +28,17 @@ #include "i945.h" #include <cbmem.h> +#if CONFIG_DYNAMIC_CBMEM +void *cbmem_top(void) +{ + return (void *)get_top_of_ram(); +} +#else struct cbmem_entry *get_cbmem_toc(void) { return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); } +#endif /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP

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Patch set updated for coreboot: a51859c Lenovo X60: Make it compile with CONFIG_DYNAMIC_CBMEM=y
by Denis Carikli 04 Apr '13

04 Apr '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3022 -gerrit commit a51859c1a4816692c66b880e2b533f3812ddccce Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Apr 4 16:50:03 2013 +0200 Lenovo X60: Make it compile with CONFIG_DYNAMIC_CBMEM=y This change was inspired by the google/link device romstage.c code. Change-Id: I8c6fbce07b86cb8ca112d5c10cf892ef05955bbc Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/romstage.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 8d5f922..cca44cf 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -216,6 +216,7 @@ void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -313,15 +314,13 @@ void main(unsigned long bist) #endif MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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New patch to review for coreboot: 4c68796 Lenovo X60: Make it compile with CONFIG_DYNAMIC_CBMEM=y
by Denis Carikli 04 Apr '13

04 Apr '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3022 -gerrit commit 4c687964c29ae60c971b85744834664c361b6c36 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Apr 4 16:50:03 2013 +0200 Lenovo X60: Make it compile with CONFIG_DYNAMIC_CBMEM=y Note that while the code in src/mainboard/lenovo/x60 compiles, it still doesn't fix the i945/raminit.c code which fails like that: i945/raminit.c:31:21: error: no previous prototype for 'get_cbmem_toc' [-Werror=missing-prototypes] and may have more failures(since I cound't compile coreboot fully). Change-Id: I8c6fbce07b86cb8ca112d5c10cf892ef05955bbc Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/romstage.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 8d5f922..cca44cf 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -216,6 +216,7 @@ void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -313,15 +314,13 @@ void main(unsigned long bist) #endif MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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Patch merged into coreboot/master: 72ef888 libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line
by gerrit＠coreboot.org 04 Apr '13

04 Apr '13

the following patch was just integrated into master: commit 72ef8881a319de48464e640ccd37e8e282320284 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Apr 4 14:12:26 2013 +0200 libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line Nico Huber spotted [1], that commit (4d6ab4e2) [1] updating superiotools’s `README` with the Git command line superiotool: Update README with Git repository URL and directory location missed, that after `git clone` one sitll has to change into the cloned directory. So prepend the path with `coreboot/` to fix that. The same error happened in the commit (e1ea5151) for libpayload [2] libpayload: Update README with Git repository URL and directory location and is fixed in this patch too. [1] http://review.coreboot.org/#/c/3019/ [2] http://review.coreboot.org/2228 Change-Id: Ib6e8b678af6276556a40ccfd52ae35ca7e674455 Reported-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3021 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Build-Tested: build bot (Jenkins) at Thu Apr 4 15:07:20 2013, giving +1 Reviewed-By: Nico Huber <nico.huber(a)secunet.com> at Thu Apr 4 17:22:14 2013, giving +2 See http://review.coreboot.org/3021 for details. -gerrit

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coreboot-gerrit April 2013