coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 0c8b7d1 inteltool: remove unused file descriptor variable and ifdefs
by gerrit＠coreboot.org 08 Apr '13

08 Apr '13

the following patch was just integrated into master: commit 0c8b7d1ac272d5578e61c260a14f4fabbf3f53eb Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Apr 5 20:38:08 2013 +0200 inteltool: remove unused file descriptor variable and ifdefs Change-Id: I6a119b1f362f481914377e8d14c713159f895130 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/3030 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Apr 5 21:46:02 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 18:17:57 2013, giving +2 See http://review.coreboot.org/3030 for details. -gerrit

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Patch merged into coreboot/master: db9eaf4 snow/exynos5250: move board-specific power stuff to mainboard dir
by gerrit＠coreboot.org 08 Apr '13

08 Apr '13

the following patch was just integrated into master: commit db9eaf4cb2a2fe65b0d08dc5b47426f7399d6757 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 5 15:38:12 2013 -0700 snow/exynos5250: move board-specific power stuff to mainboard dir This moves highly board-specific code out from the Exynos5250 power_init() into Snow's romstage.c. There's no reason the CPU- specific code should care about which PMIC we are using and which bus it is on. Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Apr 6 03:53:00 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 18:16:04 2013, giving +2 See http://review.coreboot.org/3034 for details. -gerrit

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Patch set updated for coreboot: e5d9918 AMD Thatcher: Fix PCIE link issues
by Siyuan Wang 08 Apr '13

08 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3011 -gerrit commit e5d9918c23626bd237f0b217e141784ddfb8a96b Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Apr 2 10:49:09 2013 +0800 AMD Thatcher: Fix PCIE link issues 1). Thatcher PCIE x8 slot is reverse order. Although the PCIE slot is x16, it actually uses 8 lanes(15:8). Because the PCIE slot is configured by PortList[0], fix this item can enable the slot. A x1 PCIE network adapter works well in this slot. 2). Fix DdiList to detect DP monitor or HDMI monitor. GPIO50 can be used to detect DP0/HDMI0 monitor. If GPIO50 is 1, it is DP monitor. If GPIO50 is 0, it is HDMI monitor. GPIO51 can be used to detect DP1/HDMI1 in the same way. 3). Disable unused PCIE port and clean up code in PlatformGnbPcie.c and devicetree.cb. PCIE port 3 and 7 are not used in Thatcher. Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 75 ++++++++++++---------------- src/mainboard/amd/thatcher/devicetree.cb | 12 ++--- 2 files changed, 37 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 8ee6707..ade2840 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -23,100 +23,79 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "Fch.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */ { 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ + /* PCIe port, Lanes 4, PCI Device Number 4, LAN */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ + /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ + /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */ { - 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ + 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, -#if 1 - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, -#endif }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // DP0 to HDMI0/DP + // DP0 to HDMI0/DP0 { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - // DP1 to FCH + // DP1 to HDMI1/DP1 { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) }, - // DP2 to HDMI1/DP + // DP2 to MINI-DDI Card { - 0, -// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) - }, - // GFX Lane 15-12 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - // GFX Lane 11-8 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) }, - // GFX Lane 7-4 - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -151,6 +130,7 @@ OemCustomizeInitEarly ( VOID *TrinityPcieComplexListPtr; VOID *TrinityPciePortPtr; VOID *TrinityPcieDdiPtr; + UINT8 Value; ALLOCATE_HEAP_PARAMS AllocHeapParams; @@ -161,7 +141,7 @@ OemCustomizeInitEarly ( // AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + sizeof (PCIe_DDI_DESCRIPTOR)) * 3; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -192,12 +172,19 @@ OemCustomizeInitEarly ( LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 50, &Value, &InitEarly->StdHeader); + if (!(Value & 0x80)) + DdiList[0].Ddi.ConnectorType = ConnectorTypeHDMI; + LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 51, &Value, &InitEarly->StdHeader); + if (!(Value & 0x80)) + DdiList[1].Ddi.ConnectorType = ConnectorTypeHDMI; + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 69dc0f8..330ee6b 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -32,12 +32,12 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 on end # PCIE SLOT0 x16 - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN + device pci 2.0 on end # PCIE SLOT0 x8 + device pci 3.0 off end + device pci 4.0 on end # LAN + device pci 5.0 on end # PCIE MINI0 + device pci 6.0 on end # PCIE MINI1 + device pci 7.0 off end device pci 8.0 off end # NB/SB Link P2P bridge end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex

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Patch set updated for coreboot: 509eab1 armv7: specify condition code for msr instruction
by David Hendricks 08 Apr '13

08 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3037 -gerrit commit 509eab148b71fc36833aa0feb6bb63e74dd056a5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Apr 7 17:26:34 2013 -0700 armv7: specify condition code for msr instruction This adds condition codes when using the msr instruction. Although described as "optional" in the Cortex-A series programmer's guide, our experience with using the msr instruction in the payload suggests that the condition code is not optional and that this only worked in coreboot (and u-boot) because the processor comes up in SVC32 mode. (credit to Gabe Black for finding this, I'm only uploading the patch) Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b --- src/arch/armv7/bootblock.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c647834..faf5475 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -58,7 +58,7 @@ reset: mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0xd3 - msr cpsr,r0 + msr cpsr_cxsf,r0 /* * From Cortex-A Series Programmer's Guide:

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Patch set updated for coreboot: eff28f9 exynos5250: add missing address-of operator in UART driver
by David Hendricks 08 Apr '13

08 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3038 -gerrit commit eff28f992c90119e71692f0705c5c8f153ec345d Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Apr 7 17:38:32 2013 -0700 exynos5250: add missing address-of operator in UART driver This adds a missing address-of operator. This was a subtle bug that didn't seem to cause problems at first since the serial console appeared to work. However it caused an imprecise external abort which became apparent later on when aborts were unmasked in the kernel via the CPSR_A bit. (credit goes to Gabe Black for finding this) Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I80a33b147d92d559fa8fefbe7d5642235deb9aea --- src/cpu/samsung/exynos5250/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index d23087a..75c5763 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -185,7 +185,7 @@ static void exynos5_uart_tx_byte(unsigned char data) struct s5p_uart *uart = (struct s5p_uart *)base_port; /* wait for room in the tx FIFO */ - while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { + while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(1)) return; }

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New patch to review for coreboot: 32ad472 exynos5250: add missing address-of operator in UART driver
by David Hendricks 08 Apr '13

08 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3038 -gerrit commit 32ad472aa1b52549eae47a0f21746c8e41eff871 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Apr 7 17:38:32 2013 -0700 exynos5250: add missing address-of operator in UART driver This adds a missing address-of operator. This was a subtle bug that didn't seem to cause problems at first since the serial console appeared to work. However it caused an imprecise external abort which became apparent later on when aborts were unmasked in the kernel via the CPSR_A bit. (credit goes to Gabe Black for finding this) Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I80a33b147d92d559fa8fefbe7d5642235deb9aea --- src/cpu/samsung/exynos5250/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index d23087a..75c5763 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -185,7 +185,7 @@ static void exynos5_uart_tx_byte(unsigned char data) struct s5p_uart *uart = (struct s5p_uart *)base_port; /* wait for room in the tx FIFO */ - while ((readl(uart->ufstat) & TX_FIFO_FULL_MASK)) { + while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (exynos5_uart_err_check(1)) return; }

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New patch to review for coreboot: c4a0546 armv7: specify operational condition codes for msr instruction
by David Hendricks 08 Apr '13

08 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3037 -gerrit commit c4a05467636ba94ead652be9588e9c96c85aa2a4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Apr 7 17:26:34 2013 -0700 armv7: specify operational condition codes for msr instruction This adds condition codes when using the msr instruction. Although described as "optional" in the Cortex-A series programmer's guide, our experience with using the msr instruction in the payload suggests that the condition code is not optional and that this only worked in coreboot (and u-boot) because the processor comes up in SVC32 mode. (credit to Gabe Black for finding this, I'm only uploading the patch) Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b --- src/arch/armv7/bootblock.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index c647834..faf5475 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -58,7 +58,7 @@ reset: mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0xd3 - msr cpsr,r0 + msr cpsr_cxsf,r0 /* * From Cortex-A Series Programmer's Guide:

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New patch to review for coreboot: d4eb3b2 Add Azalia support for non-AGESA sb700 and enable it for M4A785T-M
by Denis Carikli 06 Apr '13

06 Apr '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3035 -gerrit commit d4eb3b284c8b29366a7ab3d900b784a2bb73d55c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Apr 6 16:52:12 2013 +0200 Add Azalia support for non-AGESA sb700 and enable it for M4A785T-M The code was took and converted from configureAzaliaSetConfigD4Dword in src/vendorcode/amd/cimx/sb700/AZALIA.c TODO: split that commit in two(one for my board and one generic). TODO: better commit message Change-Id: I333b2ebe595aacd9562ad8f4f7f7efab0386619a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785-m/hda.h | 38 +++++++++++++++++++++++++++++++++ src/mainboard/asus/m4a785-m/mainboard.c | 25 ++++++++++++++++++++++ src/southbridge/amd/sb700/hda.c | 28 ++++++++++++++++++++++++ src/southbridge/amd/sb700/hda.h | 31 +++++++++++++++++++++++++++ 4 files changed, 122 insertions(+) diff --git a/src/mainboard/asus/m4a785-m/hda.h b/src/mainboard/asus/m4a785-m/hda.h new file mode 100644 index 0000000..77d3afb --- /dev/null +++ b/src/mainboard/asus/m4a785-m/hda.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef M4A785T_M_HDA_H +#define M4A785T_M_HDA_H +static CODECENTRY m4a785t_m_codec_vt1708s[] = /* VIA VT1708S */ +{ + {0x19, 0x01011012}, + {0x1a, 0x01a19026}, + {0x1b, 0x0181302e}, + {0x1c, 0x01014010}, + {0x1d, 0x0221401f}, + {0x1e, 0x02a19027}, + {0x1f, 0x593311f8}, + {0x20, 0x074411f0}, + {0x21, 0x985601f0}, + {0x22, 0x01016011}, + {0x23, 0x01012014}, + {0xff, 0xffffffff} /* end of table */ +}; +#endif diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index b1154ab..bc9167a 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -25,7 +25,9 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/hda.h" #include "southbridge/amd/sb700/smbus.h" +#include "hda.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ @@ -186,6 +188,28 @@ static void set_thermal_config(void) */ } +static void audio_setup(void) +{ + struct device *dev; + u8 dbPinRouting, dbChannelNum=0; + u32 bar0 = 0; + + printk(BIOS_INFO, "Configuring Azalia Started...\n"); + + /* find the BAR 0 */ + dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); + bar0 = dev->resource_list[0].base; + + dbPinRouting = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0x14, 0)), 0xfc /* SB_SMBUS_REGFC */ ); + do{ + if ( ( !(dbPinRouting & 0x1 /* BIT0 */) ) && (dbPinRouting & 0x2 /* BIT1 */ ) ) + azalia_set_config(m4a785t_m_codec_vt1708s, dbChannelNum, bar0); + dbPinRouting >>= 2; + dbChannelNum++; + } while (dbChannelNum != 4); + printk(BIOS_INFO, "Configuring Azalia Ended...\n"); +} + /************************************************* * enable the dedicated function in this board. * This function called early than rs780_enable. @@ -197,6 +221,7 @@ static void mainboard_enable(device_t dev) set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); + audio_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index 98cb75f..d02aed1 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -24,12 +24,40 @@ #include <device/pci_ops.h> #include <arch/io.h> #include <delay.h> +#include "../../../vendorcode/amd/cimx/sb700/SB700.h" #include "sb700.h" +#include "hda.h" #define HDA_ICII_REG 0x68 #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) +void azalia_set_config(CODECENTRY* tempAzaliaCodecEntryPtr, u32 ddChannelNum, u32 ddBAR0){ + u8 dbtemp1,dbtemp2, i; + u32 ddtemp=0,ddtemp2=0; + + while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){ + dbtemp1=0x20; + if ((tempAzaliaCodecEntryPtr->Nid) == 0x1) + dbtemp1=0x24; + ddtemp = tempAzaliaCodecEntryPtr->Nid; + ddtemp &= 0xff; + ddtemp <<= 20; + ddtemp |= ddChannelNum; + ddtemp |= (0x700 << 8); + for(i=4; i>0; i--){ + do{ + ddtemp2 = read32(ddBAR0 + SB_AZ_BAR_REG68); + } while (ddtemp2 & 0x1 /* Bit 0 */); + dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff; + ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2; + write32(ddBAR0 + SB_AZ_BAR_REG60 /*, AccWidthUint32 | S3_SAVE, */, ddtemp); + // delay(60); + } + ++tempAzaliaCodecEntryPtr; + } +} + static int set_bits(u32 port, u32 mask, u32 val) { u32 dword; diff --git a/src/southbridge/amd/sb700/hda.h b/src/southbridge/amd/sb700/hda.h new file mode 100644 index 0000000..e7d3009 --- /dev/null +++ b/src/southbridge/amd/sb700/hda.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SB700_HDA_H +#define SB700_HDA_H + +typedef struct _CODECENTRY{ + u8 Nid; + u32 Byte40; +}CODECENTRY; + +void azalia_set_config(CODECENTRY* tempAzaliaCodecEntryPtr, u32 ddChannelNum, u32 ddBAR0); + +#endif

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Patch merged into coreboot/master: 161ccc7 exynos5250: add a chip.h file for the display register settings
by gerrit＠coreboot.org 06 Apr '13

06 Apr '13

the following patch was just integrated into master: commit 161ccc76ea0f8941a34c5bed323cc9ba1fe0221d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Apr 5 13:35:29 2013 -0700 exynos5250: add a chip.h file for the display register settings Display hardware is part of this SOC, and we need to be able to set certain variables in devicetree.cb. This chip file contains the initial things we think we need to set. Change-Id: I16f2d4228c87116dbeb53a3c9f3f359a6444f552 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/3031 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Apr 6 01:22:14 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Sat Apr 6 00:34:56 2013, giving +2 See http://review.coreboot.org/3031 for details. -gerrit

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Patch set updated for coreboot: 8687b8a snow/exynos5250: move board-specific power stuff to mainboard dir
by David Hendricks 05 Apr '13

05 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3034 -gerrit commit 8687b8aa6c915ce41dbb344f9aa4ca5a91c94117 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 5 15:38:12 2013 -0700 snow/exynos5250: move board-specific power stuff to mainboard dir This moves highly board-specific code out from the Exynos5250 power_init() into Snow's romstage.c. There's no reason the CPU- specific code should care about which PMIC we are using and which bus it is on. Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/power.c | 60 +----------------------------------- src/mainboard/google/snow/romstage.c | 54 +++++++++++++++++++++++++++++--- 2 files changed, 50 insertions(+), 64 deletions(-) diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 953bf5c..ffba8c5 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -30,10 +30,6 @@ #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/sysreg.h> -#include <drivers/maxim/max77686/max77686.h> - -#include "device/i2c.h" -#include "cpu/samsung/exynos5-common/i2c.h" static void ps_hold_setup(void) { @@ -130,64 +126,10 @@ void power_exit_wakeup(void) ((resume_func)power->inform0)(); } -/** - * Initialize the pmic voltages to power up the system - * This also calls i2c_init so that we can program the pmic - * - * REG_ENABLE = 0, needed to set the buck/ldo enable bit ON - * - * @return Return 0 if ok, else -1 - */ int power_init(void) { - int error = 0; - - /* - * FIXME(dhendrix): We will re-factor the caller of power_init() - * to start from a board-specific romstage file and do the i2c - * early setup. There is no reason CPU power init code should - * mess with board-specific i2c parameters. - */ - /* Set the i2c register address base so i2c works before FDT */ - i2c_set_early_reg(0x12c60000); - ps_hold_setup(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* - * We're using CR1616 coin cell battery that is non-rechargeable - * battery. But, BBCHOSTEN bit of the BBAT Charger Register in - * MAX77686 is enabled by default for charging coin cell. - * - * Also, we cannot meet the coin cell reverse current spec. in UL - * standard if BBCHOSTEN bit is enabled. - * - * Disable Coin BATT Charging - */ - error = max77686_disable_backup_batt(); - - error |= max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, - REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, - REG_ENABLE, MAX77686_MV); - if (error != 0) { - power_shutdown(); - printk(BIOS_ERR, "power init failed\n"); - } - - return error; + return 0; } void power_enable_xclkout(void) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 39069b2..ca7ba9c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -35,6 +35,9 @@ #include <console/console.h> #include <arch/stages.h> +#include <drivers/maxim/max77686/max77686.h> +#include <device/i2c.h> + #include "mainboard.h" #define MMC0_GPIO_PIN (58) @@ -52,6 +55,45 @@ static int board_wakeup_permitted(void) } #endif +static int setup_pmic(void) +{ + int error = 0; + + /* + * We're using CR1616 coin cell battery that is non-rechargeable + * battery. But, BBCHOSTEN bit of the BBAT Charger Register in + * MAX77686 is enabled by default for charging coin cell. + * + * Also, we cannot meet the coin cell reverse current spec. in UL + * standard if BBCHOSTEN bit is enabled. + * + * Disable Coin BATT Charging + */ + error = max77686_disable_backup_batt(); + + error |= max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, + REG_ENABLE, MAX77686_UV); + error |= max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, + REG_ENABLE, MAX77686_MV); + + if (error) + printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); + + return error; +} + static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -90,11 +132,13 @@ void main(void) system_clock_init(mem, arm_ratios); console_init(); - /* - * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. - * Also, we should only call power_init() on cold boot. - */ - power_init(); + + i2c_set_early_reg(0x12c60000); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (power_init()) + power_shutdown(); + if (setup_pmic()) + power_shutdown(); if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n");

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coreboot-gerrit April 2013