the following patch was just integrated into master:
commit 33e83caff59f7b6ff2ba62d3b496235ef5c4e543
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Apr 8 11:20:55 2013 -0700
cbfstool: completely initialize input and output streams
The LZMA glue code in cbfstool was recently rewritten from C++
to plain C code in:
commit aa3f7ba36ebe3a933aa664f826382f60b31e86f1
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Mar 28 16:51:45 2013 -0700
cbfstool: Replace C++ code with C code
Reviewed-on: http://review.coreboot.org/3010
In the progress of doing so, the stream position for the
input stream and output stream was not reset properly. This
would cause LZMA producing corrupt data when running the
compression function multiple times.
Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/3040
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Apr 8 21:33:33 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 21:36:37 2013, giving +2
See http://review.coreboot.org/3040 for details.
-gerrit
the following patch was just integrated into master:
commit bb2cc714809150e1f1d6a502e29ef524232ee7a9
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Apr 5 13:51:11 2013 -0700
Fix read_option invocation in uart8250mem.c
read_option was unified between ramstage and romstage a while ago.
However, it seems some invocations were not fixed accordingly.
This patch switches uart8250mem.c to use the new scheme.
Change-Id: I03cef4f6ee9188a6412c61d7ed34fbaff808a32b
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/3033
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Sat Apr 6 02:16:00 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 21:36:00 2013, giving +2
See http://review.coreboot.org/3033 for details.
-gerrit
the following patch was just integrated into master:
commit 84463efb9448425c9c498425a4fc80b53ed5db73
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Apr 5 13:49:55 2013 -0700
Fix compilation when coverage debugging is enabled
With CONFIG_DEBUG_COVERAGE enabled, the build currently fails with
src/lib/gcov-glue.c: In function 'fseek':
src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format]
src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format]
Change-Id: Iddaa601748c210d9dad06ae9dab2a3deaa635b2c
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: http://review.coreboot.org/3032
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Sat Apr 6 01:47:58 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 21:35:22 2013, giving +2
See http://review.coreboot.org/3032 for details.
-gerrit
the following patch was just integrated into master:
commit 9e8af58263b7c84ee276354b97c19ad31992c8e9
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Nov 8 19:31:23 2012 -0800
libpayload: Handle multifunction bridge devices better.
This change modifies the code in libpayload that scans the PCI hierarchy for
USB controllers. Previously, if a devices primary function (function 0) was a
bridge, then none of the other functions, if any, would be looked at. If one
of the other functions was a bridge, that wouldn't be handled either. The new
version looks at each function that's present no matter what, and if it
discovers that it's a bridge it scans the other side.
Change-Id: I37f269a4fe505fd32d9594e2daf17ddd78609c15
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: http://review.coreboot.org/2517
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Build-Tested: build bot (Jenkins) at Sat Apr 6 00:33:33 2013, giving +1
See http://review.coreboot.org/2517 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3040
-gerrit
commit da6a69416014e34d1d8ed799841ac8727d592487
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Apr 8 11:20:55 2013 -0700
cbfstool: completely initialize input and output streams
The LZMA glue code in cbfstool was recently rewritten from C++
to plain C code in:
commit aa3f7ba36ebe3a933aa664f826382f60b31e86f1
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Mar 28 16:51:45 2013 -0700
cbfstool: Replace C++ code with C code
Reviewed-on: http://review.coreboot.org/3010
In the progress of doing so, the stream position for the
input stream and output stream was not reset properly. This
would cause LZMA producing corrupt data when running the
compression function multiple times.
Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
---
util/cbfstool/lzma/lzma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/cbfstool/lzma/lzma.c b/util/cbfstool/lzma/lzma.c
index 914d8b7..579784e 100644
--- a/util/cbfstool/lzma/lzma.c
+++ b/util/cbfstool/lzma/lzma.c
@@ -61,7 +61,7 @@ static ISzAlloc LZMAalloc = { SzAlloc, SzFree };
/* Streaming API */
-typedef struct vector {
+typedef struct {
char *p;
size_t pos;
size_t size;
@@ -147,9 +147,11 @@ void do_lzma_compress(char *in, int in_len, char *out, int *out_len)
}
instream.p = in;
+ instream.pos = 0;
instream.size = in_len;
outstream.p = out;
+ outstream.pos = 0;
outstream.size = in_len;
put_64(propsEncoded + LZMA_PROPS_SIZE, in_len);
Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3035
-gerrit
commit ddeefe51f59d54a7898b29adacc359d663bf00f5
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Mon Apr 8 19:29:11 2013 +0200
Add Azalia support for non-AGESA sb700
The code was taken and converted from configureAzaliaSetConfigD4Dword
in src/vendorcode/amd/cimx/sb700/AZALIA.c
Change-Id: I333b2ebe595aacd9562ad8f4f7f7efab0386619a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
---
src/southbridge/amd/sb700/hda.c | 30 ++++++++++++++++++++++++++++++
src/southbridge/amd/sb700/hda.h | 31 +++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 98cb75f..04ffd1f 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -24,12 +24,42 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include <delay.h>
+#include "../../../vendorcode/amd/cimx/sb700/SB700.h"
#include "sb700.h"
+#include "hda.h"
#define HDA_ICII_REG 0x68
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
+void azalia_set_config(CODECENTRY* tempAzaliaCodecEntryPtr, u32 ddChannelNum, u32 ddBAR0)
+{
+ u8 dbtemp1,dbtemp2, i;
+ u32 ddtemp=0,ddtemp2=0;
+
+ while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF)
+ {
+ dbtemp1=0x20;
+ if ((tempAzaliaCodecEntryPtr->Nid) == 0x1)
+ dbtemp1=0x24;
+ ddtemp = tempAzaliaCodecEntryPtr->Nid;
+ ddtemp &= 0xff;
+ ddtemp <<= 20;
+ ddtemp |= ddChannelNum;
+ ddtemp |= (0x700 << 8);
+ for(i = 4; i > 0; i-- ){
+ do {
+ ddtemp2 = read32(ddBAR0 + SB_AZ_BAR_REG68);
+ } while (ddtemp2 & 0x1 /* Bit 0 */);
+ dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff;
+ ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2;
+ write32(ddBAR0 + SB_AZ_BAR_REG60 /*, AccWidthUint32 | S3_SAVE, */, ddtemp);
+ udelay(60);
+ }
+ ++tempAzaliaCodecEntryPtr;
+ }
+}
+
static int set_bits(u32 port, u32 mask, u32 val)
{
u32 dword;
diff --git a/src/southbridge/amd/sb700/hda.h b/src/southbridge/amd/sb700/hda.h
new file mode 100644
index 0000000..ed632e7
--- /dev/null
+++ b/src/southbridge/amd/sb700/hda.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SB700_HDA_H
+#define SB700_HDA_H
+
+typedef struct _CODECENTRY {
+ u8 Nid;
+ u32 Byte40;
+} CODECENTRY;
+
+void azalia_set_config(CODECENTRY* tempAzaliaCodecEntryPtr, u32 ddChannelNum, u32 ddBAR0);
+
+#endif
Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3035
-gerrit
commit d655dc139abc9005f79c06387fb756d9e49835eb
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Sat Apr 6 16:52:12 2013 +0200
Add Azalia support for non-AGESA sb700 and enable it for M4A785T-M
The code was taken and converted from configureAzaliaSetConfigD4Dword
in src/vendorcode/amd/cimx/sb700/AZALIA.c
TODO: split that commit in two(one for my board and one generic).
TODO: better commit message
TODO: make the mainboard pin mapping semantic.
Change-Id: I333b2ebe595aacd9562ad8f4f7f7efab0386619a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
---
src/mainboard/asus/m4a785-m/hda.h | 38 +++++++++++++++++++++++++++++++++
src/mainboard/asus/m4a785-m/mainboard.c | 25 ++++++++++++++++++++++
src/southbridge/amd/sb700/hda.c | 30 ++++++++++++++++++++++++++
src/southbridge/amd/sb700/hda.h | 31 +++++++++++++++++++++++++++
4 files changed, 124 insertions(+)
diff --git a/src/mainboard/asus/m4a785-m/hda.h b/src/mainboard/asus/m4a785-m/hda.h
new file mode 100644
index 0000000..77d3afb
--- /dev/null
+++ b/src/mainboard/asus/m4a785-m/hda.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef M4A785T_M_HDA_H
+#define M4A785T_M_HDA_H
+static CODECENTRY m4a785t_m_codec_vt1708s[] = /* VIA VT1708S */
+{
+ {0x19, 0x01011012},
+ {0x1a, 0x01a19026},
+ {0x1b, 0x0181302e},
+ {0x1c, 0x01014010},
+ {0x1d, 0x0221401f},
+ {0x1e, 0x02a19027},
+ {0x1f, 0x593311f8},
+ {0x20, 0x074411f0},
+ {0x21, 0x985601f0},
+ {0x22, 0x01016011},
+ {0x23, 0x01012014},
+ {0xff, 0xffffffff} /* end of table */
+};
+#endif
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index b1154ab..a8030d1 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -25,7 +25,9 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/hda.h"
#include "southbridge/amd/sb700/smbus.h"
+#include "hda.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
@@ -186,6 +188,28 @@ static void set_thermal_config(void)
*/
}
+static void audio_setup(void)
+{
+ struct device *dev;
+ u8 dbPinRouting, dbChannelNum=0;
+ u32 bar0 = 0;
+
+ printk(BIOS_INFO, "Configuring Azalia\n");
+
+ /* find BAR 0 */
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
+ bar0 = dev->resource_list[0].base;
+
+ dbPinRouting = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0x14, 0)), 0xfc /* SB_SMBUS_REGFC */ );
+ do {
+ if ( ( !(dbPinRouting & 0x1 /* BIT0 */) ) && (dbPinRouting & 0x2 /* BIT1 */ ) )
+ azalia_set_config(m4a785t_m_codec_vt1708s, dbChannelNum, bar0);
+ dbPinRouting >>= 2;
+ dbChannelNum++;
+ } while (dbChannelNum != 4);
+ printk(BIOS_INFO, "Configuring Azalia DONE...\n");
+}
+
/*************************************************
* enable the dedicated function in this board.
* This function called early than rs780_enable.
@@ -197,6 +221,7 @@ static void mainboard_enable(device_t dev)
set_pcie_dereset();
/* get_ide_dma66(); */
set_thermal_config();
+ audio_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 98cb75f..04ffd1f 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -24,12 +24,42 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include <delay.h>
+#include "../../../vendorcode/amd/cimx/sb700/SB700.h"
#include "sb700.h"
+#include "hda.h"
#define HDA_ICII_REG 0x68
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
+void azalia_set_config(CODECENTRY* tempAzaliaCodecEntryPtr, u32 ddChannelNum, u32 ddBAR0)
+{
+ u8 dbtemp1,dbtemp2, i;
+ u32 ddtemp=0,ddtemp2=0;
+
+ while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF)
+ {
+ dbtemp1=0x20;
+ if ((tempAzaliaCodecEntryPtr->Nid) == 0x1)
+ dbtemp1=0x24;
+ ddtemp = tempAzaliaCodecEntryPtr->Nid;
+ ddtemp &= 0xff;
+ ddtemp <<= 20;
+ ddtemp |= ddChannelNum;
+ ddtemp |= (0x700 << 8);
+ for(i = 4; i > 0; i-- ){
+ do {
+ ddtemp2 = read32(ddBAR0 + SB_AZ_BAR_REG68);
+ } while (ddtemp2 & 0x1 /* Bit 0 */);
+ dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff;
+ ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2;
+ write32(ddBAR0 + SB_AZ_BAR_REG60 /*, AccWidthUint32 | S3_SAVE, */, ddtemp);
+ udelay(60);
+ }
+ ++tempAzaliaCodecEntryPtr;
+ }
+}
+
static int set_bits(u32 port, u32 mask, u32 val)
{
u32 dword;
diff --git a/src/southbridge/amd/sb700/hda.h b/src/southbridge/amd/sb700/hda.h
new file mode 100644
index 0000000..ed632e7
--- /dev/null
+++ b/src/southbridge/amd/sb700/hda.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SB700_HDA_H
+#define SB700_HDA_H
+
+typedef struct _CODECENTRY {
+ u8 Nid;
+ u32 Byte40;
+} CODECENTRY;
+
+void azalia_set_config(CODECENTRY* tempAzaliaCodecEntryPtr, u32 ddChannelNum, u32 ddBAR0);
+
+#endif
the following patch was just integrated into master:
commit 6d0fe9cad003d752af3214ae9a91d7411d582950
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Apr 7 17:26:34 2013 -0700
armv7: specify condition code for msr instruction
This adds condition codes when using the msr instruction. Although
described as "optional" in the Cortex-A series programmer's guide,
our experience with using the msr instruction in the payload suggests
that the condition code is not optional and that this only worked
in coreboot (and u-boot) because the processor comes up in SVC32 mode.
(credit to Gabe Black for finding this, I'm only uploading the patch)
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b
Reviewed-on: http://review.coreboot.org/3037
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Apr 8 04:53:13 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 18:31:08 2013, giving +2
See http://review.coreboot.org/3037 for details.
-gerrit
the following patch was just integrated into master:
commit c7e5d798420bb00f2c1853ca6abc11a7ee027886
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Sun Apr 7 17:38:32 2013 -0700
exynos5250: add missing address-of operator in UART driver
This adds a missing address-of operator. This was a subtle bug that
didn't seem to cause problems at first since the serial console
appeared to work. However it caused an imprecise external abort which
became apparent later on when aborts were unmasked in the kernel via
the CPSR_A bit.
(credit goes to Gabe Black for finding this)
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: I80a33b147d92d559fa8fefbe7d5642235deb9aea
Reviewed-on: http://review.coreboot.org/3038
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Mon Apr 8 04:27:42 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 8 18:30:02 2013, giving +2
See http://review.coreboot.org/3038 for details.
-gerrit