coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

1 participants
506 discussions

New patch to review for coreboot: 071399a snow/exynos5250: move board-specific power stuff to mainboard dir
by David Hendricks 05 Apr '13

05 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3034 -gerrit commit 071399a33c195ad4720f88b5ca75b6fb970a75b3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 5 15:38:12 2013 -0700 snow/exynos5250: move board-specific power stuff to mainboard dir This moves highly board-specific code out from the Exynos5250 power_init() into Snow's romstage.c. There's no reason the CPU- specific code should be messing with board-specific I2C settings and configuring a particular PMIC which we happen to use on Snow. Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/power.c | 60 +----------------------------------- src/mainboard/google/snow/romstage.c | 54 +++++++++++++++++++++++++++++--- 2 files changed, 50 insertions(+), 64 deletions(-) diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 953bf5c..ffba8c5 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -30,10 +30,6 @@ #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/sysreg.h> -#include <drivers/maxim/max77686/max77686.h> - -#include "device/i2c.h" -#include "cpu/samsung/exynos5-common/i2c.h" static void ps_hold_setup(void) { @@ -130,64 +126,10 @@ void power_exit_wakeup(void) ((resume_func)power->inform0)(); } -/** - * Initialize the pmic voltages to power up the system - * This also calls i2c_init so that we can program the pmic - * - * REG_ENABLE = 0, needed to set the buck/ldo enable bit ON - * - * @return Return 0 if ok, else -1 - */ int power_init(void) { - int error = 0; - - /* - * FIXME(dhendrix): We will re-factor the caller of power_init() - * to start from a board-specific romstage file and do the i2c - * early setup. There is no reason CPU power init code should - * mess with board-specific i2c parameters. - */ - /* Set the i2c register address base so i2c works before FDT */ - i2c_set_early_reg(0x12c60000); - ps_hold_setup(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* - * We're using CR1616 coin cell battery that is non-rechargeable - * battery. But, BBCHOSTEN bit of the BBAT Charger Register in - * MAX77686 is enabled by default for charging coin cell. - * - * Also, we cannot meet the coin cell reverse current spec. in UL - * standard if BBCHOSTEN bit is enabled. - * - * Disable Coin BATT Charging - */ - error = max77686_disable_backup_batt(); - - error |= max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, - REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, - REG_ENABLE, MAX77686_MV); - if (error != 0) { - power_shutdown(); - printk(BIOS_ERR, "power init failed\n"); - } - - return error; + return 0; } void power_enable_xclkout(void) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 39069b2..ca7ba9c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -35,6 +35,9 @@ #include <console/console.h> #include <arch/stages.h> +#include <drivers/maxim/max77686/max77686.h> +#include <device/i2c.h> + #include "mainboard.h" #define MMC0_GPIO_PIN (58) @@ -52,6 +55,45 @@ static int board_wakeup_permitted(void) } #endif +static int setup_pmic(void) +{ + int error = 0; + + /* + * We're using CR1616 coin cell battery that is non-rechargeable + * battery. But, BBCHOSTEN bit of the BBAT Charger Register in + * MAX77686 is enabled by default for charging coin cell. + * + * Also, we cannot meet the coin cell reverse current spec. in UL + * standard if BBCHOSTEN bit is enabled. + * + * Disable Coin BATT Charging + */ + error = max77686_disable_backup_batt(); + + error |= max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, + REG_ENABLE, MAX77686_UV); + error |= max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, + REG_ENABLE, MAX77686_MV); + error |= max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, + REG_ENABLE, MAX77686_MV); + + if (error) + printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__); + + return error; +} + static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -90,11 +132,13 @@ void main(void) system_clock_init(mem, arm_ratios); console_init(); - /* - * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. - * Also, we should only call power_init() on cold boot. - */ - power_init(); + + i2c_set_early_reg(0x12c60000); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (power_init()) + power_shutdown(); + if (setup_pmic()) + power_shutdown(); if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n");

1 0

Patch set updated for coreboot: 9cb3cfc Intel: Return on missing microcode file to fix null pointer dereference
by Stefan Reinauer 05 Apr '13

05 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit 9cb3cfcc7446fefd2819c240a2a708ba385566ba Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Intel: Return on missing microcode file to fix null pointer dereference Selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS results in a null pointer dereference later on resulting in a crash. for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Fix this by returning if `microcode_updates` is `NULL`, that means no file is found. This patch is successfully tested on the Lenovo X201. Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/microcode/microcode.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..1991ed8 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -21,6 +21,7 @@ /* Microcode update for Intel PIII and later CPUs */ #include <stdint.h> +#include <stddef.h> #if !defined(__ROMCC__) #include <console/console.h> #endif @@ -131,7 +132,7 @@ const void *intel_microcode_find(void) #endif if (!microcode_updates) - return microcode_updates; + return NULL; /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; @@ -202,6 +203,13 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) { +#if !defined(__ROMCC__) + printk(BIOS_WARNING, "No microcode updates found.\n"); +#endif + return; + } + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

1 0

New patch to review for coreboot: 816c6bc Fix read_option invocation in uart8250mem.c
by Stefan Reinauer 05 Apr '13

05 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3033 -gerrit commit 816c6bce99efa6eaadb24007317e2d2d0f615017 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 5 13:51:11 2013 -0700 Fix read_option invocation in uart8250mem.c read_option was unified between ramstage and romstage a while ago. However, it seems some invocations were not fixed accordingly. This patch switches uart8250mem.c to use the new scheme. Change-Id: I03cef4f6ee9188a6412c61d7ed34fbaff808a32b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/uart8250mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index b98cb0e..8224843 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -116,7 +116,7 @@ u32 uart_mem_init(void) static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; unsigned b_index = 0; #if defined(__PRE_RAM__) - b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); + b_index = read_option(baud_rate, 0); b_index &= 7; uart_baud = baud[b_index]; #else

1 0

New patch to review for coreboot: f3a5098 Fix compilation when coverage debugging is enabled
by Stefan Reinauer 05 Apr '13

05 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3032 -gerrit commit f3a50986fea88b65334a36d83a1c0b5d93021d46 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Apr 5 13:49:55 2013 -0700 Fix compilation when coverage debugging is enabled With CONFIG_DEBUG_COVERAGE enabled, the build currently fails with src/lib/gcov-glue.c: In function 'fseek': src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format] src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format] Change-Id: Iddaa601748c210d9dad06ae9dab2a3deaa635b2c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/gcov-glue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 7c069cb..4e2b290 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -84,7 +84,7 @@ static int fseek(FILE *stream, long offset, int whence) * to a freshly opened file. */ gcc_assert (offset == 0 && whence == SEEK_SET); #if CONFIG_DEBUG_COVERAGE - printk(BIOS_DEBUG, "fseek %s offset=%d whence=%d\n", + printk(BIOS_DEBUG, "fseek %s offset=%ld whence=%d\n", stream->filename, offset, whence); #endif return 0;

1 0

New patch to review for coreboot: 3eaa426 exynos5250: add a chip.h file for the display register settings
by Ronald G. Minnich 05 Apr '13

05 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3031 -gerrit commit 3eaa4269ef0e5ac732865b96ddc77d6fbeda1c93 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Apr 5 13:35:29 2013 -0700 exynos5250: add a chip.h file for the display register settings Display hardware is part of this SOC, and we need to be able to set certain variables in devicetree.cb. This chip file contains the initial things we think we need to set. Change-Id: I16f2d4228c87116dbeb53a3c9f3f359a6444f552 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/chip.h | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */

1 0

Patch set updated for coreboot: eedbccb Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES again
by Stefan Reinauer 05 Apr '13

05 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2707 -gerrit commit eedbccb54ce536870aad6e9457fc0a5afbb17f4c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 13 11:44:39 2013 +0200 Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES again These are not defined since commit »Drop HAVE_MAINBOARD_RESOURCES« (1c5071d1) [1] but were unfortunately introduced again in new ports. [1] http://review.coreboot.org/1414 Change-Id: I5eb61628141aefd08779615702d51ca155fa632a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/intel/baskingridge/Kconfig | 1 - src/mainboard/supermicro/h8scm/mainboard.c | 7 ------- 5 files changed, 11 deletions(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index b0ebe78..d41a9f5 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index dc97710..4bddc5f 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index d400c88..3081b5a 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 2463079..9608ea2 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER select CHROMEOS diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c index 819208c..23b1d72 100644 --- a/src/mainboard/supermicro/h8scm/mainboard.c +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -72,13 +72,6 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -#if CONFIG_HAVE_MAINBOARD_RESOURCES -int add_mainboard_resources(struct lb_memory *mem) -{ - return 0; -} -#endif - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };

1 0

Patch merged into coreboot/master: 6ccb1ab mtrr: add rom caching comment about hyperthreads
by gerrit＠coreboot.org 05 Apr '13

05 Apr '13

the following patch was just integrated into master: commit 6ccb1abfd4aff94711b9950f75b0eb6758c4f4d1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 3 09:57:53 2013 -0500 mtrr: add rom caching comment about hyperthreads Explicitly call out the effects of hyperthreads running the MTRR code and its impact on the enablement of ROM caching. Change-Id: I14b8f3fdc112340b8f483f2e554c5680576a8a7c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3018 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Apr 3 20:48:31 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 5 20:41:54 2013, giving +2 See http://review.coreboot.org/3018 for details. -gerrit

1 0

Patch set updated for coreboot: ac24401 libpayload: Handle multifunction bridge devices better.
by Stefan Reinauer 05 Apr '13

05 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2517 -gerrit commit ac24401af7c73862bf5a9b499c22a8d31c7ae9d0 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Nov 8 19:31:23 2012 -0800 libpayload: Handle multifunction bridge devices better. This change modifies the code in libpayload that scans the PCI hierarchy for USB controllers. Previously, if a devices primary function (function 0) was a bridge, then none of the other functions, if any, would be looked at. If one of the other functions was a bridge, that wouldn't be handled either. The new version looks at each function that's present no matter what, and if it discovers that it's a bridge it scans the other side. Change-Id: I37f269a4fe505fd32d9594e2daf17ddd78609c15 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/drivers/usb/usbinit.c | 56 +++++++++++++++++-------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 74358bb..76653ff 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -47,12 +47,12 @@ static int usb_controller_initialize(int bus, int dev, int func) u32 class; u32 devclass; u32 prog_if; - pcidev_t addr; + pcidev_t pci_device; u32 pciid; - addr = PCI_DEV (bus, dev, func); - class = pci_read_config32(addr, 8); - pciid = pci_read_config32(addr, 0); + pci_device = PCI_DEV (bus, dev, func); + class = pci_read_config32(pci_device, 8); + pciid = pci_read_config32(pci_device, 0); devclass = class >> 16; prog_if = (class >> 8) & 0xff; @@ -63,9 +63,9 @@ static int usb_controller_initialize(int bus, int dev, int func) if (devclass == 0xc03) { u32 pci_command; - pci_command = pci_read_config32(addr, PCI_COMMAND); + pci_command = pci_read_config32(pci_device, PCI_COMMAND); pci_command |= PCI_COMMAND_MASTER; - pci_write_config32(addr, PCI_COMMAND, pci_command); + pci_write_config32(pci_device, PCI_COMMAND, pci_command); usb_debug("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); @@ -73,7 +73,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x00: #ifdef CONFIG_USB_UHCI usb_debug("UHCI controller\n"); - uhci_init (addr); + uhci_init (pci_device); #else usb_debug("UHCI controller (not supported)\n"); #endif @@ -82,7 +82,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x10: #ifdef CONFIG_USB_OHCI usb_debug("OHCI controller\n"); - ohci_init(addr); + ohci_init(pci_device); #else usb_debug("OHCI controller (not supported)\n"); #endif @@ -91,7 +91,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x20: #ifdef CONFIG_USB_EHCI usb_debug("EHCI controller\n"); - ehci_init(addr); + ehci_init(pci_device); #else usb_debug("EHCI controller (not supported)\n"); #endif @@ -100,7 +100,7 @@ static int usb_controller_initialize(int bus, int dev, int func) case 0x30: #ifdef CONFIG_USB_XHCI usb_debug("xHCI controller\n"); - xhci_init(addr); + xhci_init(pci_device); #else usb_debug("xHCI controller (not supported)\n"); #endif @@ -121,31 +121,37 @@ static void usb_scan_pci_bus(int bus) int dev, func; for (dev = 0; dev < 32; dev++) { u8 header_type; - pcidev_t addr = PCI_DEV(bus, dev, 0); + pcidev_t pci_device = PCI_DEV(bus, dev, 0); + /* Check if there's a device here at all. */ - if (pci_read_config32(addr, REG_VENDOR_ID) == 0xffffffff) - continue; - header_type = pci_read_config8(addr, REG_HEADER_TYPE); - /* If this is a bridge, scan the bus on the other side. */ - if ((header_type & ~HEADER_TYPE_MULTIFUNCTION) == - HEADER_TYPE_BRIDGE) { - int sub_bus = - pci_read_config8(addr, REG_SECONDARY_BUS); - usb_scan_pci_bus(sub_bus); + if (pci_read_config32(pci_device, REG_VENDOR_ID) == 0xffffffff) continue; - } + /* * EHCI is defined by standards to be at a higher function * than the USB1 controllers. We don't want to init USB1 + * devices just to "steal" those for USB2, so make sure USB2 - * comes first. + * comes first by scanning multifunction devices from 7 to 0. */ + /* Check for a multifunction device. */ + header_type = pci_read_config8(pci_device, REG_HEADER_TYPE); if (header_type & HEADER_TYPE_MULTIFUNCTION) - for (func = 7; func > 0; func--) + func = 7; + else + func = 0; + + for (; func >= 0; func--) { + pci_device = PCI_DEV(bus, dev, func); + header_type = pci_read_config8(pci_device, REG_HEADER_TYPE); + /* If this is a bridge, scan the other side. */ + if ((header_type & ~HEADER_TYPE_MULTIFUNCTION) == + HEADER_TYPE_BRIDGE) + usb_scan_pci_bus(pci_read_config8(pci_device, + REG_SECONDARY_BUS)); + else usb_controller_initialize(bus, dev, func); - /* Initialize function 0. */ - usb_controller_initialize(bus, dev, 0); + } } }

1 0

Patch set updated for coreboot: 6a762b8 util/cbmem: Don't output trailing garbage for cbmemc
by Stefan Reinauer 05 Apr '13

05 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2991 -gerrit commit 6a762b8c0fd53424454763f44731611b730b6833 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:15:12 2013 +0100 util/cbmem: Don't output trailing garbage for cbmemc Current code outputs the whole cbmemc buffer even if only part of it is really used. Fix it to output only the used part and notify the user if the buffer was too small for the required data. Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/cbmem/cbmem.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index bc6bd6b..f3f5add 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -314,6 +314,7 @@ static void dump_console(void) void *console_p; char *console_c; uint32_t size; + uint32_t cursor; if (console.tag != LB_TAG_CBMEM_CONSOLE) { fprintf(stderr, "No console found in coreboot table.\n"); @@ -328,6 +329,12 @@ static void dump_console(void) * Hence we have to add 8 to get to the actual console string. */ size = *(uint32_t *)console_p; + cursor = *(uint32_t *) (console_p + 4); + /* Cursor continues to go on even after no more data fits in + * the buffer but the data is dropped in this case. + */ + if (size > cursor) + size = cursor; console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); @@ -337,7 +344,10 @@ static void dump_console(void) memcpy(console_c, console_p + 8, size); console_c[size] = 0; - printf("%s", console_c); + printf("%s\n", console_c); + if (size < cursor) + printf("%d %s lost\n", cursor - size, + (cursor - size) == 1 ? "byte":"bytes"); free(console_c);

1 0

Patch set updated for coreboot: 7a596e2 samsung/exynos5: init display port and LCD
by David Hendricks 05 Apr '13

05 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2931 -gerrit commit 7a596e2c224bd30d181b8f8b0166281e091496da Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 18 09:49:54 2013 -0700 samsung/exynos5: init display port and LCD This adds resources for the display port controller and attempts to go thru the init sequence. TODO: split this apart when we have something working... Change-Id: I2caa350f8c0e681f71e9646898dcdb36e10115b2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 6 +- src/cpu/samsung/exynos5-common/i2c.c | 10 +- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 1 + src/cpu/samsung/exynos5250/Kconfig | 2 +- src/cpu/samsung/exynos5250/chip.h | 40 ++++++ src/cpu/samsung/exynos5250/cpu.c | 81 +++++++++-- src/mainboard/google/snow/devicetree.cb | 23 +-- src/mainboard/google/snow/ramstage.c | 203 ++++++++++++++++++++++++++- 8 files changed, 338 insertions(+), 28 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..ea6c0f1 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); - /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -582,11 +582,9 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, { int ret = 0; - //vi->res = panel_info->vl_col; - //vi->yres = panel_info->vl_row; - fimd_bypass(); fb_init(panel_info, lcdbase, panel_data); + printk(BIOS_SPEW, "fb_init(%p, %p, %p) done\n", panel_info, lcdbase, panel_data); /* Enable flushing after LCD writes if requested */ // forget it. lcd_set_flush_dcache(1); diff --git a/src/cpu/samsung/exynos5-common/i2c.c b/src/cpu/samsung/exynos5-common/i2c.c index 7384b50..e09496d 100644 --- a/src/cpu/samsung/exynos5-common/i2c.c +++ b/src/cpu/samsung/exynos5-common/i2c.c @@ -93,6 +93,7 @@ void i2c_set_early_reg(unsigned int base) g_early_i2c_config = (struct s3c24x0_i2c *)base; } +#include <console/console.h> static struct s3c24x0_i2c_bus *get_bus(int bus_idx) { /* If an early i2c config exists we just use that */ @@ -105,7 +106,7 @@ static struct s3c24x0_i2c_bus *get_bus(int bus_idx) if (bus_idx < i2c_busses) return &i2c_bus[bus_idx]; - debug("Undefined bus: %d\n", bus_idx); + printk(BIOS_ERR, "Undefined bus: %d, busses: %d\n", bus_idx, i2c_busses); return NULL; } @@ -233,6 +234,7 @@ int i2c_set_bus_num(unsigned int bus) struct s3c24x0_i2c_bus *i2c; i2c = get_bus(bus); + printk(BIOS_DEBUG, "%s: bus: %u, i2c: %p\n", __func__, bus, i2c); if (!i2c) return -1; g_current_bus = bus; @@ -522,17 +524,21 @@ int i2c_probe(unsigned char chip) return ret != I2C_OK; } +#include <console/console.h> /* FIXME: remove this */ int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; int ret; + printk(BIOS_DEBUG, "%s: entered, chip: 0x%02x, addr: 0x%02x\n", + __func__, chip, addr); if (alen > 4) { debug("I2C read: addr len %d not supported\n", alen); return 1; } + printk(BIOS_DEBUG, "%s: checkpoint 1\n", __func__); if (alen > 0) { xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; @@ -559,8 +565,10 @@ int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buf i2c = get_bus(g_current_bus); if (!i2c) return -1; + printk(BIOS_DEBUG, "%s: checkpoint 2\n", __func__); ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], alen, buffer, len); + printk(BIOS_DEBUG, "%s: bus: %u, ret %d\n", __func__, i2c->bus_num, ret); if (ret) { debug("I2c read: failed %d\n", ret); return 1; diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 67c1990..2988d5d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ +struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index ca306b6..cc67abd 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -96,4 +96,4 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex - default 0x100000 + default 0x4000000 diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h new file mode 100644 index 0000000..798cd26 --- /dev/null +++ b/src/cpu/samsung/exynos5250/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5250_H +#define CPU_SAMSUNG_EXYNOS5250_H + +struct cpu_samsung_exynos5250_config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5250_H */ diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 4bb06e8..0a85322 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,13 +1,77 @@ +#include <stdlib.h> +#include <string.h> +#include <stddef.h> +#include <delay.h> #include <console/console.h> #include <device/device.h> -#include <arch/cache.h> -#include <cpu/samsung/exynos5250/cpu.h> +#include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> +#include "chip.h" +#include "cpu.h" #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(device_t dev) +{ + int ret; + struct cpu_samsung_exynos5250_config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + unsigned long int fb_size; + u32 lcdbase; + + printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf); + memset(&vi, 0, sizeof(vi)); + memset(&panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi.vl_col = conf->xres; + vi.vl_row = conf->yres; + vi.vl_bpix = conf->bpp; + /* + * The size is a magic number from hardware. Allocate enough for the + * frame buffer and color map. + */ + fb_size = conf->xres * conf->yres * sizeof(unsigned long); + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); + printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase)); + mmio_resource(dev, 0, lcdbase/KiB, 64); + vi.cmap = (void *)lcdbase; + + lcdbase += 64*KiB; + mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); + printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); +} + static void cpu_init(device_t dev) { + exynos_displayport_init(dev); ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); } @@ -18,22 +82,19 @@ static void cpu_noop(device_t dev) static struct device_operations cpu_ops = { .read_resources = cpu_noop, .set_resources = cpu_noop, - .enable_resources = cpu_noop, - .init = cpu_init, + .enable_resources = cpu_init, + .init = cpu_noop, .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_exynos5250_dev(device_t dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_ops; - } + dev->ops = &cpu_ops; } struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") - .enable_dev = enable_dev, + .enable_dev = enable_exynos5250_dev, }; void exynos5250_config_l2_cache(void) diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 4c88ea8..41ed45e 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,16 +17,17 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - -device cpu_cluster 0 on -end - -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end -end + device cpu_cluster 0 on end + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" end diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 9081629..0618a86 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -18,13 +18,20 @@ */ #include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> /* FIXME: for backlight FET enable */ #include <cbmem.h> +#include <delay.h> +#include <arch/cache.h> #include <arch/exception.h> +#include <arch/gpio.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/gpio.h> #include <cpu/samsung/exynos5250/power.h> -#include <arch/cache.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> + /* convenient shorthand (in MB) */ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) @@ -68,3 +75,197 @@ void main(void) hardwaremain(0); } + +/* TODO: transplanted DP stuff, clean up once we have something that works */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ + +static void exynos_dp_bridge_setup(void) +{ +#if 0 + if (fdt_gpio_isvalid(&local.dp_rst)) { + fdtdec_set_gpio(&local.dp_rst, 1); + gpio_cfg_pin(local.dp_rst.gpio, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(local.dp_rst.gpio, EXYNOS_GPIO_PULL_NONE); + udelay(10); + fdtdec_set_gpio(&local.dp_rst, 0); + } +#endif + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); + + gpio_set_value(dp_pd_l, 1); + gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE); + + gpio_set_value(dp_rst_l, 0); + gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT); + gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE); + udelay(10); + gpio_set_value(dp_rst_l, 1); + + udelay(90000); /* FIXME: this might be unnecessary */ +} + +static void exynos_dp_bridge_init(void) +{ + /* De-assert PD (and possibly RST) to power up the bridge */ + gpio_set_value(dp_pd_l, 1); + gpio_set_value(dp_rst_l, 1); + + /* + * We need to wait for 90ms after bringing up the bridge since there + * is a phantom "high" on the HPD chip during its bootup. The phantom + * high comes within 7ms of de-asserting PD and persists for at least + * 15ms. The real high comes roughly 50ms after PD is de-asserted. The + * phantom high makes it hard for us to know when the NXP chip is up. + */ + udelay(90000); /* FIXME: this might be unnecessary */ +} + +static int exynos_dp_hotplug(void) +{ + /* Check HPD. If it's high, we're all good. */ + if (gpio_get_value(dp_hpd)) + return 0; + return -1; +} + +static void exynos_dp_reset(void) +{ + gpio_set_value(dp_pd_l, 0); + gpio_set_value(dp_rst_l, 0); + /* paranoid delay period (300ms) */ + udelay(300 * 1000); +} + +#define LCD_T5_DELAY_MS 10 +#define LCD_T6_DELAY_MS 10 + +static void snow_backlight_pwm(void) +{ + /*Configure backlight PWM as a simple output high (100% brightness) */ + gpio_direction_output(GPIO_B20, 1); + udelay(LCD_T6_DELAY_MS * 1000); +} + +static void snow_backlight_en(void) +{ + /* * Configure GPIO for LCD_BL_EN */ + gpio_direction_output(GPIO_X30, 1); +} + +#define TPS69050_BUS 4 /* Snow-specific */ + +#define TPS69050_ADDR 0x48 +#define FET1_CTRL 0x0f +#define FET6_CTRL 0x14 + +static void snow_lcd_vdd(void) +{ + uint8_t val = 0xbb; + printk(BIOS_DEBUG, "%s: attempting to enable FET6\n", __func__); + i2c_set_bus_num(TPS69050_BUS); + i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET6_CTRL before: 0x%02x\n", __func__, val); + val |= 1; + i2c_write(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + + i2c_read(TPS69050_ADDR, FET6_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET6_CTRL after: 0x%02x\n", __func__, val); +// return board_ldo_enable(6); /* Enable FET6, lcd panel */ +} + +static void snow_backlight_vdd(void) +{ + uint8_t val = 0xbb; +// return board_ldo_enable(1); /* Enable FET1, backlight */ + /* FIXME: implement more paranoid tps65090EXYNOS5250_DP1_ADDR fet routine */ +// ret = tps65090_fet_enable(1); + printk(BIOS_DEBUG, "%s: attempting to enable FET1\n", __func__); + i2c_set_bus_num(TPS69050_BUS); + i2c_read(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET1_CTRL before: 0x%02x\n", __func__, val); + val |= 1; + i2c_write(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val)); + udelay(LCD_T5_DELAY_MS * 1000); + + i2c_read(TPS69050_ADDR, FET1_CTRL, 1, &val, sizeof(val)); + printk(BIOS_DEBUG, "%s: FET1_CTRL after: 0x%02x\n", __func__, val); +} + +//static struct video_info smdk5250_dp_config = { +static struct video_info snow_dp_video_info = { + /* FIXME: fix video_info struct to use const for name */ + .name = (char *)"eDP-LVDS NXP PTN3460", + + .h_sync_polarity = 0, + .v_sync_polarity = 0, + .interlaced = 0, + + .color_space = COLOR_RGB, + .dynamic_range = VESA, + .ycbcr_coeff = COLOR_YCBCR601, + .color_depth = COLOR_8, + + .link_rate = LINK_RATE_2_70GBPS, + .lane_count = LANE_COUNT2, +}; + +/* FIXME: move some place more appropriate */ +#define EXYNOS5250_DP1_BASE 0x145b0000 +#define SNOW_MAX_DP_TRIES 5 + +static void mainboard_init(device_t dev) +{ + int dp_tries; + unsigned int wait_ms; + struct s5p_dp_device dp_device = { + .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, + .video_info = &snow_dp_video_info, + }; + + /* this happens after cpu_init where exynos resources are set */ + /* Set the i2c register address base so i2c works before FDT */ + + /* FIXME: fix the braindead i2c crap leftover from u-boot */ + i2c_set_early_reg(0x12ca0000); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + snow_lcd_vdd(); + exynos_dp_bridge_setup(); + for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { + if (wait_ms) { + udelay(wait_ms); + wait_ms = 0; + } + + exynos_dp_bridge_init(); + if (exynos_dp_hotplug()) { + exynos_dp_reset(); + continue; + } + + if (dp_controller_init(&dp_device, &wait_ms)) + continue; + + snow_backlight_vdd(); + snow_backlight_pwm(); + snow_backlight_en(); + /* if we're here, we're successful */ + break; + } + + if (dp_tries > SNOW_MAX_DP_TRIES) + printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM Chromebook", + .enable_dev = mainboard_enable, +};

1 0

← Newer
1
...
38
39
40
41
42
43
44
...
51
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2013