Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990
-gerrit
commit 51d0cc0581f93ef85552b2ce73e8aee1f8d6ba58
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Mar 30 12:04:23 2013 +0100
Intel: Return on missing microcode file to fix null pointer dereference
Selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the
microcode blob `cpu_microcode_blob.bin` in CBFS results in a
null pointer dereference later on resulting in a crash.
for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
Fix this by returning if `microcode_updates` is `NULL`, that means
no file is found.
This patch is successfully tested on the Lenovo X201.
Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/cpu/intel/microcode/microcode.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index d908c25..7735e0d 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -131,7 +131,7 @@ const void *intel_microcode_find(void)
#endif
if (!microcode_updates)
- return microcode_updates;
+ return NULL;
/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
msr.lo = 0;
@@ -202,6 +202,13 @@ void intel_update_microcode(const void *microcode_updates)
const char *c;
msr_t msr;
+ if (!microcode_updates) {
+#if !defined(__ROMCC__)
+ printk(BIOS_WARNING, "No microcode updates found.\n");
+#endif
+ return;
+ }
+
/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
msr.lo = 0;
msr.hi = 0;
the following patch was just integrated into master:
commit 0dc775e894a3a7b3539eeeb4210bf8b796062274
Author: Stefan Tauner <stefan.tauner(a)gmx.at>
Date: Fri Apr 5 01:15:04 2013 +0200
inteltool: use inttypes for prints in memory.c
This fixes at least one warning on my machine where "llx" is replaced by PRIx64.
Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at>
Reviewed-on: http://review.coreboot.org/3024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Fri Apr 5 01:41:53 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 5 20:21:35 2013, giving +2
See http://review.coreboot.org/3024 for details.
-gerrit
the following patch was just integrated into master:
commit ce801b55fa21f119f19f39eacc15d8b63e639890
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Apr 5 09:56:18 2013 -0700
exynos5-common: get rid of displayport trial code
This was a first pass at display port support, we have
realized that it was ultimately a bad path. The display
hardware is intimately tied into a specific cpu and
mainboard combination, and the code has to be elsewhere.
The devicetree formatting is ugly, but it matters not:
it's changing soon.
Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Fri Apr 5 20:16:36 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 5 20:17:35 2013, giving +2
See http://review.coreboot.org/3029 for details.
-gerrit
the following patch was just integrated into master:
commit 5f3754e66dbe3b04c71c19fb106a92b30d475ab4
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Fri Apr 5 00:12:21 2013 +0200
inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
Cppcheck [1], a static code analysis tool, warns about the
following.
$ cppcheck --version
Cppcheck 1.59
$ cppcheck --enable=all .
[…]
Checking cpu.c...
[cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
[cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
[…]
And indeed, `core` is an unsigned integer and `man 3 printf` tells
the following about conversion specifiers.
d, i The int argument is converted to signed decimal notation. […]
o, u, x, X
The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or unsigned hexadecimal (x and X)
notation.
So use `u` and Cppcheck does not complain anymore.
[1] http://cppcheck.sourceforge.net/
Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Fri Apr 5 11:17:22 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 5 20:17:03 2013, giving +2
See http://review.coreboot.org/3026 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3029
-gerrit
commit 911093ead842dbaf6f24ac87460a25de6491f10d
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Apr 5 09:56:18 2013 -0700
exynos5-common: get rid of displayport trial code
This was a first pass at display port support, we have
realized that it was ultimately a bad path. The display
hardware is intimately tied into a specific cpu and
mainboard combination, and the code has to be elsewhere.
The devicetree formatting is ugly, but it matters not:
it's changing soon.
Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/cpu/samsung/exynos5-common/Makefile.inc | 2 -
src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 -
.../exynos5-common/displayport/Makefile.inc | 2 -
src/cpu/samsung/exynos5-common/displayport/chip.h | 40 --------
.../exynos5-common/displayport/displayport.c | 107 ---------------------
src/mainboard/google/snow/devicetree.cb | 14 ---
6 files changed, 167 deletions(-)
diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc
index 7abd75c..6911b70 100644
--- a/src/cpu/samsung/exynos5-common/Makefile.inc
+++ b/src/cpu/samsung/exynos5-common/Makefile.inc
@@ -21,5 +21,3 @@ ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += s5p-dp-reg.c
ramstage-y += exynos-fb.c
-
-subdirs-y += displayport
diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig
deleted file mode 100644
index 26d1422..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config EXYNOS_DISPLAYPORT
- bool
diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc
deleted file mode 100644
index 7c52eaf..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c
-
diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h
deleted file mode 100644
index 53b7836..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/chip.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
-#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
-
-struct cpu_samsung_exynos5_common_displayport_config {
- /* special magic numbers! */
- int clkval_f;
- int upper_margin;
- int lower_margin;
- int vsync;
- int left_margin;
- int right_margin;
- int hsync;
-
- int xres;
- int yres;
- int bpp;
-
- u32 lcdbase;
-};
-
-#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */
diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c
deleted file mode 100644
index 1c08bc7..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/displayport.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdlib.h>
-#include <string.h>
-#include <delay.h>
-#include <arch/io.h>
-#include <device/device.h>
-
-/* we distinguish a display port device from a raw graphics device because there are
- * dramatic differences in startup depending on graphics usage. To make startup fast
- * and easier to understand and debug we explicitly name this common case. The alternate
- * approach, involving lots of machine and callbacks, is hard to debug and verify.
- */
-static void exynos_displayport_init(void)
-{
- struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info;
- /* put these on the stack. If, at some point, we want to move this code to a
- * pre-ram stage, it will be much easier.
- */
- vidinfo_t vi;
- struct exynos5_fimd_panel panel;
- void *lcdbase;
-
- memset(vi, 0, sizeof(vi));
- memset(panel, 0, sizeof(panel));
-
- panel.is_dp = 1; /* Display I/F is eDP */
- /* while it is true that we did a memset to zero,
- * we leave some 'set to zero' entries here to make
- * it clear what's going on. Graphics is confusing.
- */
- panel.is_mipi = 0;
- panel.fixvclk = 0;
- panel.ivclk = 0;
- panel.clkval_f = conf->clkval_f;
- panel.upper_margin = conf->upper_margin;
- panel.lower_margin = conf->lower_margin;
- panel.vsync = conf->vsync;
- panel.left_margin = conf->left_margin;
- panel.right_margin = conf->right_margin;
- panel.hsync = conf->hsync;
-
- vi->vl_col = conf->xres;
- vi->fl_row = conf->yres;
- vi->vl_bpix = conf->bpp;
- vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */
-
- lcdbase = conf->lcdbase;
- printk(BIOS_DEBUG, "Initializing exynos VGA\n");
- ret = lcd_ctrl_init(&vi, &panel, lcdbase);
-#if 0
- ret = board_dp_lcd_vdd(blob, &wait_ms);
- ret = board_dp_bridge_setup(blob, &wait_ms);
- while (tries < 5) {
- ret = board_dp_bridge_init(blob, &wait_ms);
- ret = board_dp_hotplug(blob, &wait_ms);
- if (ret) {
- ret = board_dp_bridge_reset(blob, &wait_ms);
- continue;
- }
- ret = dp_controller_init(blob, &wait_ms);
- ret = board_dp_backlight_vdd(blob, &wait_ms);
- ret = board_dp_backlight_pwm(blob, &wait_ms);
- ret = board_dp_backlight_en(blob, &wait_ms);
- }
-#endif
-}
-
-static void exynos_displayport_noop(device_t dummy)
-{
-}
-
-static struct device_operations exynos_displayport_operations = {
- .read_resources = exynos_displayport_noop,
- .set_resources = exynos_displayport_noop,
- .enable_resources = exynos_displayport_noop,
- .init = exynos_displayport_init,
- .scan_bus = exynos_displayport_noop,
-};
-
-static void exynos_displayport_enable(struct device *dev)
-{
- if (dev->link_list != NULL)
- dev->ops = &exynos_displayport_operations;
-}
-
-struct chip_operations drivers_i2c_exynos_displayport_ops = {
- CHIP_NAME("exynos displayport")
- .enable_dev = exynos_displayport_enable;
-};
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index 5ad786e..4c88ea8 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -28,19 +28,5 @@ device domain 0 on
device i2c 6 on end # ?
device i2c 9 on end # ?
end
- chip cpu/samsung/exynos5-common/displayport
- register "xres" = "1366"
- register "yres" = "768"
- register "bpp" = "16"
- # complex magic timing!
- register "clkval_f" = "2"
- register "upper_margin" = "14"
- register "lower_margin" = "3"
- register "vsync" = "5"
- register "left_margin" = "80"
- register "right_margin" = "48"
- register "hsync" = "32"
- register "lcdbase" = "0x10000000"
- end
end
end
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3029
-gerrit
commit 663a707c69dcbb23f3edd5c2a9ba6fba8c3342cb
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Fri Apr 5 09:56:18 2013 -0700
exynos5-common: get rid of displayport trial code
This was a first pass at display port support, we have
realized that it was ultimately a bad path. The display
hardware is intimately tied into a specific cpu and
mainboard combination, and the code has to be elsewhere.
Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/cpu/samsung/exynos5-common/Makefile.inc | 2 -
src/cpu/samsung/exynos5-common/displayport/Kconfig | 2 -
.../exynos5-common/displayport/Makefile.inc | 2 -
src/cpu/samsung/exynos5-common/displayport/chip.h | 40 --------
.../exynos5-common/displayport/displayport.c | 107 ---------------------
5 files changed, 153 deletions(-)
diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc
index 7abd75c..6911b70 100644
--- a/src/cpu/samsung/exynos5-common/Makefile.inc
+++ b/src/cpu/samsung/exynos5-common/Makefile.inc
@@ -21,5 +21,3 @@ ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += s5p-dp-reg.c
ramstage-y += exynos-fb.c
-
-subdirs-y += displayport
diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig
deleted file mode 100644
index 26d1422..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config EXYNOS_DISPLAYPORT
- bool
diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc
deleted file mode 100644
index 7c52eaf..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c
-
diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h
deleted file mode 100644
index 53b7836..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/chip.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
-#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
-
-struct cpu_samsung_exynos5_common_displayport_config {
- /* special magic numbers! */
- int clkval_f;
- int upper_margin;
- int lower_margin;
- int vsync;
- int left_margin;
- int right_margin;
- int hsync;
-
- int xres;
- int yres;
- int bpp;
-
- u32 lcdbase;
-};
-
-#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */
diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c
deleted file mode 100644
index 1c08bc7..0000000
--- a/src/cpu/samsung/exynos5-common/displayport/displayport.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdlib.h>
-#include <string.h>
-#include <delay.h>
-#include <arch/io.h>
-#include <device/device.h>
-
-/* we distinguish a display port device from a raw graphics device because there are
- * dramatic differences in startup depending on graphics usage. To make startup fast
- * and easier to understand and debug we explicitly name this common case. The alternate
- * approach, involving lots of machine and callbacks, is hard to debug and verify.
- */
-static void exynos_displayport_init(void)
-{
- struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info;
- /* put these on the stack. If, at some point, we want to move this code to a
- * pre-ram stage, it will be much easier.
- */
- vidinfo_t vi;
- struct exynos5_fimd_panel panel;
- void *lcdbase;
-
- memset(vi, 0, sizeof(vi));
- memset(panel, 0, sizeof(panel));
-
- panel.is_dp = 1; /* Display I/F is eDP */
- /* while it is true that we did a memset to zero,
- * we leave some 'set to zero' entries here to make
- * it clear what's going on. Graphics is confusing.
- */
- panel.is_mipi = 0;
- panel.fixvclk = 0;
- panel.ivclk = 0;
- panel.clkval_f = conf->clkval_f;
- panel.upper_margin = conf->upper_margin;
- panel.lower_margin = conf->lower_margin;
- panel.vsync = conf->vsync;
- panel.left_margin = conf->left_margin;
- panel.right_margin = conf->right_margin;
- panel.hsync = conf->hsync;
-
- vi->vl_col = conf->xres;
- vi->fl_row = conf->yres;
- vi->vl_bpix = conf->bpp;
- vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */
-
- lcdbase = conf->lcdbase;
- printk(BIOS_DEBUG, "Initializing exynos VGA\n");
- ret = lcd_ctrl_init(&vi, &panel, lcdbase);
-#if 0
- ret = board_dp_lcd_vdd(blob, &wait_ms);
- ret = board_dp_bridge_setup(blob, &wait_ms);
- while (tries < 5) {
- ret = board_dp_bridge_init(blob, &wait_ms);
- ret = board_dp_hotplug(blob, &wait_ms);
- if (ret) {
- ret = board_dp_bridge_reset(blob, &wait_ms);
- continue;
- }
- ret = dp_controller_init(blob, &wait_ms);
- ret = board_dp_backlight_vdd(blob, &wait_ms);
- ret = board_dp_backlight_pwm(blob, &wait_ms);
- ret = board_dp_backlight_en(blob, &wait_ms);
- }
-#endif
-}
-
-static void exynos_displayport_noop(device_t dummy)
-{
-}
-
-static struct device_operations exynos_displayport_operations = {
- .read_resources = exynos_displayport_noop,
- .set_resources = exynos_displayport_noop,
- .enable_resources = exynos_displayport_noop,
- .init = exynos_displayport_init,
- .scan_bus = exynos_displayport_noop,
-};
-
-static void exynos_displayport_enable(struct device *dev)
-{
- if (dev->link_list != NULL)
- dev->ops = &exynos_displayport_operations;
-}
-
-struct chip_operations drivers_i2c_exynos_displayport_ops = {
- CHIP_NAME("exynos displayport")
- .enable_dev = exynos_displayport_enable;
-};
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3028
-gerrit
commit 5ea220f7056480a3415e548e2533d36cc18823a8
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Fri Apr 5 11:12:12 2013 +0200
cbmem: Makefile: Fix typo: s,CPPFLAGS,CFLAGS,
Commit »cbmem compilation needs to use the hardened toolchain«
(7c6b6bb5) [1] introduced `CPPFLAGS` but used `CFLAGS`, which gives
the following build error, which was not spotted by Jenkins,
because programs under `utils/` are not build tested.
cbmem.c:36:34: fatal error: boot/coreboot_tables.h: Datei oder Verzeichnis nicht gefunden
compilation terminated.
As this is a C program, change `CPPFLAGS` to `CFLAGS`, causing the
actual directories get passed to the compiler and the header file
is found then.
[1] http://review.coreboot.org/1791
Change-Id: I254d76c7d98b6f920501407239566e9655b2ddeb
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
util/cbmem/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
index bf74e08..e976d28 100644
--- a/util/cbmem/Makefile
+++ b/util/cbmem/Makefile
@@ -22,7 +22,7 @@ ROOT = ../../src
CC = $(CROSS_COMPILE)gcc
CFLAGS ?= -O2
CFLAGS += -Wall -Werror
-CPPFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
+CFLAGS += -iquote $(ROOT)/include -iquote $(ROOT)/src/arch/x86
OBJS = $(PROGRAM).o