coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d2be1f1 AMD hudson & SB800 - Fix issues with mawk
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit d2be1f11e11b68d88f9065ae75f32d7982cc3fe6 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Mar 11 13:17:27 2013 -0600 AMD hudson & SB800 - Fix issues with mawk When calculating the offsets of the various binary blobs within the coreboot.rom file, we noticed that using mawk as the awk tool instead of using gawk led to build issues. This was finally traced to the maximum value of the unsigned long variables within mawk - 0x7fff_ffff. Because we were doing calculations on values up in the 0xffxxxxxx range, these numbers would either be turned into floating point values and printed using scientific notation, or truncated at 0x7fff_ffff. To fix this, we print the values out as floating point, with no decimal digits. This works in gawk, mawk, and original-awk and as the testing below show, seems to be the best way to do this. printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}' mawk: 4294967295 2147483647 2147483647 original-awk: 4294967295 2147483648 4294967295 gawk: 4294967295 4294967295 4294967295 The issue of %d not matching gawk and original-awk has been reported to ubuntu. In the future, I'd recommend that whenever awk is used, a format is specified. It doesn't seem that we can count on the representation being the same between the different versions. Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2628 Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Mar 25 19:53:14 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 20:52:31 2013, giving +2 See http://review.coreboot.org/2628 for details. -gerrit

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New patch to review for coreboot: 45a346f inteltool: Cast to `ptrdiff_t` instead of `uint64_t`
by Paul Menzel 01 Apr '13

01 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3002 -gerrit commit 45a346f15b5ee549698fc6aa274c9f3ef91fd445 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 1 18:26:58 2013 +0200 inteltool: Cast to `ptrdiff_t` instead of `uint64_t` When building inteltool under x86-32, the following warnings are shown. $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] Nico Huber commented the following [1]. I don't see those warnings because I build for x86-64. I guess they could be fixed by casting to `ptrdiff_t` (from stddef.h) instead of `uint64_t`. And indeed, using `ptrdiff_t` fixes the warning. These warnings were introduced in commit »inteltool: Add support for dumping AMB registers« (4b7b320f) [2]. [1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG [2] http://review.coreboot.org/525 Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/amb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c index a3ee01d..9ff2977 100644 --- a/util/inteltool/amb.c +++ b/util/inteltool/amb.c @@ -17,7 +17,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - +#include <stddef.h> #include <stdio.h> #include <stdlib.h> #include "inteltool.h" @@ -28,7 +28,7 @@ static uint32_t amb_read_config32(volatile void *base, int fn, int reg) { - return *(uint32_t *)(AMB_ADDR((uint64_t)base, fn, reg)); + return *(uint32_t *)(AMB_ADDR((ptrdiff_t)base, fn, reg)); } static void amb_printreg32(volatile void *base, int fn, int reg, @@ -42,7 +42,7 @@ static void amb_printreg32(volatile void *base, int fn, int reg, static uint16_t amb_read_config16(volatile void *base, int fn, int reg) { - return *(uint16_t *)(AMB_ADDR((uint64_t)base, fn, reg)); + return *(uint16_t *)(AMB_ADDR((ptrdiff_t)base, fn, reg)); } static void amb_printreg16(volatile void *base, int fn, int reg, @@ -57,7 +57,7 @@ static void amb_printreg16(volatile void *base, int fn, int reg, static uint8_t amb_read_config8(volatile void *base, int fn, int reg) { - return *(uint8_t *)(AMB_ADDR((uint64_t)base, fn, reg)); + return *(uint8_t *)(AMB_ADDR((ptrdiff_t)base, fn, reg)); } static void amb_printreg8(volatile void *base, int fn, int reg,

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Patch set updated for coreboot: 84ce0eb inteltool: Allow to override Makefile variables
by Paul Menzel 01 Apr '13

01 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2996 -gerrit commit 84ce0eba178ee7636e7f333350bb60294ca7c1d6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 31 22:15:43 2013 +0200 inteltool: Allow to override Makefile variables Allow to override the variables `CC`, `INSTALL`, `PREFIX`, `CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`. This way for example a different compiler can easily be used. CC=clang make As a side note, Clang in contrast to GCC does *not* issue the following warnings. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] These are only shown under 32-bit and not 64-bit $ uname -m i686 and are going to be fixed in a separate patch. Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 6c94460..2028a4a 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -21,17 +21,17 @@ PROGRAM = inteltool -CC = gcc -INSTALL = /usr/bin/install -PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -LDFLAGS = -lpci -lz +CC ?= gcc +INSTALL ?= /usr/bin/install +PREFIX ?= /usr/local +CFLAGS ?= -O2 -g -Wall -W +LDFLAGS += -lpci -lz OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) -LDFLAGS = -framework DirectHW -lpci -lz +LDFLAGS += -framework DirectHW endif ifeq ($(OS_ARCH), FreeBSD) CFLAGS += -I/usr/local/include

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New patch to review for coreboot: fefcfdc inteltool: Add Cougar/Panther Point GPIO defaults
by Nico Huber 01 Apr '13

01 Apr '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3001 -gerrit commit fefcfdc1f1307a4138cfc896b28df9764d5bfcf6 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Apr 1 15:38:44 2013 +0200 inteltool: Add Cougar/Panther Point GPIO defaults This adds default values for the GPIO setup on Intel's Cougar Point and Panther Point platform controller hubs (PCH). Values are taken from [1] and [2], respectively. I've tested this with an H77 PCH. See below for the output. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/gpio.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 5 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index e42b9da..7ce9939 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -258,6 +258,79 @@ static const io_register_t pch_gpio_registers[] = { { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; +/* Default values for Cougar Point desktop chipsets */ +static const gpio_default_t cp_pch_desktop_defaults[] = { + { 0x00, 0xb96ba1ff }, + { 0x04, 0xf6ff6eff }, + { 0x0c, 0x02fe0100 }, + { 0x18, 0x00040000 }, + { 0x28, 0x00000000 }, + { 0x2c, 0x00000000 }, + { 0x30, 0x020300ff }, + { 0x34, 0x1f57fff4 }, + { 0x38, 0xa4aa0007 }, + { 0x40, 0x00000130 }, + { 0x44, 0x00000ff0 }, + { 0x48, 0x000000c0 }, + { 0x60, 0x01000000 }, + { 0x64, 0x00000000 }, + { 0x68, 0x00000000 }, +}; +/* Default values for Cougar Point mobile chipsets */ +static const gpio_default_t cp_pch_mobile_defaults[] = { + { 0x00, 0xb96ba1ff }, + { 0x04, 0xf6ff6eff }, + { 0x0c, 0x02fe0100 }, + { 0x18, 0x00040000 }, + { 0x28, 0x00000000 }, + { 0x2c, 0x00000000 }, + { 0x30, 0x020300fe }, + { 0x34, 0x1f57fff4 }, + { 0x38, 0xa4aa0007 }, + { 0x40, 0x00000030 }, + { 0x44, 0x00000ff0 }, + { 0x48, 0x000000c0 }, + { 0x60, 0x01000000 }, + { 0x64, 0x00000000 }, + { 0x68, 0x00000000 }, +}; +/* Default values for Panther Point desktop chipsets */ +static const gpio_default_t pp_pch_desktop_defaults[] = { + { 0x00, 0xb96ba1ff }, + { 0x04, 0xeeff6eff }, + { 0x0c, 0x02fe0100 }, + { 0x18, 0x00040000 }, + { 0x28, 0x00000000 }, + { 0x2c, 0x00000000 }, + { 0x30, 0x020300ff }, + { 0x34, 0x1f57fff4 }, + { 0x38, 0xa4aa0007 }, + { 0x40, 0x00000130 }, + { 0x44, 0x00000ff0 }, + { 0x48, 0x000000c0 }, + { 0x60, 0x01000000 }, + { 0x64, 0x00000000 }, + { 0x68, 0x00000000 }, +}; +/* Default values for Panther Point mobile chipsets */ +static const gpio_default_t pp_pch_mobile_defaults[] = { + { 0x00, 0xb96ba1ff }, + { 0x04, 0xeeff6eff }, + { 0x0c, 0x02fe0100 }, + { 0x18, 0x00040000 }, + { 0x28, 0x00000000 }, + { 0x2c, 0x00000000 }, + { 0x30, 0x020300fe }, + { 0x34, 0x1f57fff4 }, + { 0x38, 0xa4aa0007 }, + { 0x40, 0x00000030 }, + { 0x44, 0x00000ff0 }, + { 0x48, 0x000000c0 }, + { 0x60, 0x01000000 }, + { 0x64, 0x00000000 }, + { 0x68, 0x00000000 }, +}; + static uint16_t gpiobase; static void print_reg(const io_register_t *const reg) @@ -324,7 +397,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) { int i, j, size, defaults_size = 0; const io_register_t *gpio_registers; - const gpio_default_t *gpio_defaults; + const gpio_default_t *gpio_defaults = NULL; uint32_t gpio_diff; if (show_diffs && !show_all) @@ -335,19 +408,31 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: - case PCI_DEVICE_ID_INTEL_UM67: - case PCI_DEVICE_ID_INTEL_HM65: case PCI_DEVICE_ID_INTEL_H67: - case PCI_DEVICE_ID_INTEL_HM67: case PCI_DEVICE_ID_INTEL_Q65: case PCI_DEVICE_ID_INTEL_QS67: case PCI_DEVICE_ID_INTEL_Q67: - case PCI_DEVICE_ID_INTEL_QM67: case PCI_DEVICE_ID_INTEL_B65: case PCI_DEVICE_ID_INTEL_C202: case PCI_DEVICE_ID_INTEL_C204: case PCI_DEVICE_ID_INTEL_C206: case PCI_DEVICE_ID_INTEL_H61: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = cp_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(cp_pch_desktop_defaults); + break; + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_QM67: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = cp_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(cp_pch_mobile_defaults); + break; case PCI_DEVICE_ID_INTEL_Z77: case PCI_DEVICE_ID_INTEL_Z75: case PCI_DEVICE_ID_INTEL_Q77: @@ -355,6 +440,12 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_B75: case PCI_DEVICE_ID_INTEL_H77: case PCI_DEVICE_ID_INTEL_C216: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = pp_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults); + break; case PCI_DEVICE_ID_INTEL_QM77: case PCI_DEVICE_ID_INTEL_QS77: case PCI_DEVICE_ID_INTEL_HM77: @@ -365,6 +456,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = pp_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc;

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New patch to review for coreboot: c684efd inteltool: Add option to show differences in GPIO setup
by Nico Huber 01 Apr '13

01 Apr '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3000 -gerrit commit c684efdc5e5e996b4e512185dba58ad84f2d0e20 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Apr 1 15:08:04 2013 +0200 inteltool: Add option to show differences in GPIO setup This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings that differ from platform defaults. For differing registers, the current, the default, and an xor of the default and the current value is printed. A follow-up commit will add defaults for the Cougar/Panther Point platform controller hubs. If you specify both, -g and -G on the command line, all GPIO registers will be printed interleaved with the diff. Here's a preview: $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/inteltool/gpio.c | 112 +++++++++++++++++++++++++++++++++++---------- util/inteltool/inteltool.c | 16 +++++-- util/inteltool/inteltool.h | 2 +- 3 files changed, 103 insertions(+), 27 deletions(-) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 8b85593..e42b9da 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -20,6 +20,8 @@ #include <stdio.h> #include "inteltool.h" +typedef struct { uint16_t addr; uint32_t def; } gpio_default_t; + static const io_register_t ich0_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, @@ -256,14 +258,79 @@ static const io_register_t pch_gpio_registers[] = { { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; +static uint16_t gpiobase; + +static void print_reg(const io_register_t *const reg) +{ + switch (reg->size) { + case 4: + printf("gpiobase+0x%04x: 0x%08x (%s)\n", + reg->addr, inl(gpiobase+reg->addr), reg->name); + break; + case 2: + printf("gpiobase+0x%04x: 0x%04x (%s)\n", + reg->addr, inw(gpiobase+reg->addr), reg->name); + break; + case 1: + printf("gpiobase+0x%04x: 0x%02x (%s)\n", + reg->addr, inb(gpiobase+reg->addr), reg->name); + break; + } +} -int print_gpios(struct pci_dev *sb) +static uint32_t get_diff(const io_register_t *const reg, const uint32_t def) { - int i, size; - uint16_t gpiobase; + uint32_t gpio_diff = 0; + switch (reg->size) { + case 4: + gpio_diff = def ^ inl(gpiobase+reg->addr); + break; + case 2: + gpio_diff = (uint16_t)def ^ inw(gpiobase+reg->addr); + break; + case 1: + gpio_diff = (uint8_t)def ^ inb(gpiobase+reg->addr); + break; + } + return gpio_diff; +} + +static void print_diff(const io_register_t *const reg, + const uint32_t def, const uint32_t diff) +{ + switch (reg->size) { + case 4: + printf("gpiobase+0x%04x: 0x%08x (%s) DEFAULT\n", + reg->addr, def, reg->name); + printf("gpiobase+0x%04x: 0x%08x (%s) DIFF\n", + reg->addr, diff, reg->name); + break; + case 2: + printf("gpiobase+0x%04x: 0x%04x (%s) DEFAULT\n", + reg->addr, def, reg->name); + printf("gpiobase+0x%04x: 0x%04x (%s) DIFF\n", + reg->addr, diff, reg->name); + break; + case 1: + printf("gpiobase+0x%04x: 0x%02x (%s) DEFAULT\n", + reg->addr, def, reg->name); + printf("gpiobase+0x%04x: 0x%02x (%s) DIFF\n", + reg->addr, diff, reg->name); + break; + } +} + +int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) +{ + int i, j, size, defaults_size = 0; const io_register_t *gpio_registers; + const gpio_default_t *gpio_defaults; + uint32_t gpio_diff; - printf("\n============= GPIOS =============\n\n"); + if (show_diffs && !show_all) + printf("\n========== GPIO DIFFS ===========\n\n"); + else + printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_Z68: @@ -376,26 +443,25 @@ int print_gpios(struct pci_dev *sb) printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase); + j = 0; for (i = 0; i < size; i++) { - switch (gpio_registers[i].size) { - case 4: - printf("gpiobase+0x%04x: 0x%08x (%s)\n", - gpio_registers[i].addr, - inl(gpiobase+gpio_registers[i].addr), - gpio_registers[i].name); - break; - case 2: - printf("gpiobase+0x%04x: 0x%04x (%s)\n", - gpio_registers[i].addr, - inw(gpiobase+gpio_registers[i].addr), - gpio_registers[i].name); - break; - case 1: - printf("gpiobase+0x%04x: 0x%02x (%s)\n", - gpio_registers[i].addr, - inb(gpiobase+gpio_registers[i].addr), - gpio_registers[i].name); - break; + if (show_all) + print_reg(&gpio_registers[i]); + + if (show_diffs && + (j < defaults_size) && + (gpio_defaults[j].addr == gpio_registers[i].addr)) { + gpio_diff = get_diff(&gpio_registers[i], + gpio_defaults[j].def); + if (gpio_diff) { + if (!show_all) + print_reg(&gpio_registers[i]); + print_diff(&gpio_registers[i], + gpio_defaults[j].def, gpio_diff); + if (!show_all) + printf("\n"); + } + j++; } } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index d56d058..2396eb0 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -197,11 +197,12 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?grpmedPMa]\n", name); + printf("usage: %s [-vh?gGrpmedPMa]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" " -g | --gpio: dump soutbridge GPIO registers\n" + " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump soutbridge RCBA registers\n" " -p | --pmbase: dump soutbridge Power Management registers\n\n" " -m | --mchbar: dump northbridge Memory Controller registers\n" @@ -227,11 +228,13 @@ int main(int argc, char *argv[]) int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; + int show_gpio_diffs = 0; static struct option long_options[] = { {"version", 0, 0, 'v'}, {"help", 0, 0, 'h'}, {"gpios", 0, 0, 'g'}, + {"gpio-diffs", 0, 0, 'G'}, {"mchbar", 0, 0, 'm'}, {"rcba", 0, 0, 'r'}, {"pmbase", 0, 0, 'p'}, @@ -244,7 +247,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?grpmedPMaA", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaA", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -254,6 +257,9 @@ int main(int argc, char *argv[]) case 'g': dump_gpios = 1; break; + case 'G': + show_gpio_diffs = 1; + break; case 'm': dump_mchbar = 1; break; @@ -277,6 +283,7 @@ int main(int argc, char *argv[]) break; case 'a': dump_gpios = 1; + show_gpio_diffs = 1; dump_mchbar = 1; dump_rcba = 1; dump_pmbase = 1; @@ -393,7 +400,10 @@ int main(int argc, char *argv[]) /* Now do the deed */ if (dump_gpios) { - print_gpios(sb); + print_gpios(sb, 1, show_gpio_diffs); + printf("\n\n"); + } else if (show_gpio_diffs) { + print_gpios(sb, 0, show_gpio_diffs); printf("\n\n"); } diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index ac23fe1..5a6dcc8 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -164,7 +164,7 @@ int print_intel_core_msrs(void); int print_mchbar(struct pci_dev *nb, struct pci_access *pacc); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); -int print_gpios(struct pci_dev *sb); +int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb);

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New patch to review for coreboot: 9e4bc8f Minor Kconfig help text fix
by Stefan Tauner 01 Apr '13

01 Apr '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2999 -gerrit commit 9e4bc8f6b65e81d0f77c66c224317e1cd9944e26 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Apr 1 13:45:44 2013 +0200 Minor Kconfig help text fix I did not check what was once after the 'and'. Change-Id: I9f3f725bec281a94abdb2eeb692a96fecdebcc0c Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- src/cpu/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6177285..ed7d6ab 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -87,7 +87,7 @@ config CPU_MICROCODE_CBFS_GENERATE building coreboot and included in the final image as a separate CBFS file. Microcode will not be hard-coded into ramstage. - The microcode file and may be removed from the ROM image at a later + The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. If unsure, select this option. @@ -101,7 +101,7 @@ config CPU_MICROCODE_CBFS_EXTERNAL microcode that you have is newer than the microcode shipping with coreboot. - The microcode file and may be removed from the ROM image at a later + The microcode file may be removed from the ROM image at a later time with cbfstool, if desired. If unsure, select "Generate from tree"

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coreboot-gerrit April 2013