coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 09dcbf0 inteltool: Add option to show differences in GPIO setup
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 09dcbf0cdbae2e9a2b26f6753c290d8c70749bba Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Apr 1 15:08:04 2013 +0200 inteltool: Add option to show differences in GPIO setup This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings that differ from platform defaults. For differing registers, the current, the default, and an xor of the default and the current value is printed. A follow-up commit will add defaults for the Cougar/Panther Point platform controller hubs. If you specify both, -g and -G on the command line, all GPIO registers will be printed interleaved with the diff. Here's a preview: $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3000 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Apr 1 22:36:45 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 22:39:04 2013, giving +2 See http://review.coreboot.org/3000 for details. -gerrit

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Patch merged into coreboot/master: d86a3a1 Winbond W83627HF: Rename and move ASL snippet to `acpi/superio.asl`
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit d86a3a17e6fbf25e20e146aefd6925b943957bda Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 28 13:46:16 2013 +0100 Winbond W83627HF: Rename and move ASL snippet to `acpi/superio.asl` Put the ASL snippet for inclusion in the DSDT under the `acpi/` folder as it is done for the other Super I/O devices. $ find src/superio/ -name *asl src/superio/ite/it8772f/acpi/superio.asl src/superio/smsc/mec1308/acpi/superio.asl src/superio/smsc/sio1007/acpi/superio.asl src/superio/winbond/w83627hf/devtree.asl As there are no users of this file yet, no other adaptations need to be made. Change-Id: Id10cd8897592b780c9fd3bd6b45ada4cf1fcf33e Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Thu Mar 28 23:42:06 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 21:09:23 2013, giving +2 See http://review.coreboot.org/2937 for details. -gerrit

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Patch merged into coreboot/master: 6758c68 ASRock E350M1: mptable.c: Remove unused variable `dev`
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 6758c6887ec7daea9d14229ae674d899ba219166 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 20:37:42 2013 +0100 ASRock E350M1: mptable.c: Remove unused variable `dev` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mptable.ramstage.o src/mainboard/asrock/e350m1/mptable.c:64:12: warning: unused variable 'dev' [-Wunused-variable] […] Removing the variable `dev` addresses the warning. The same change was done in the following commit for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I83f4630cb6ab1e4c95d04b4e8423850ed1858e45 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2965 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 21:24:46 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 21:07:46 2013, giving +2 See http://review.coreboot.org/2965 for details. -gerrit

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Patch merged into coreboot/master: cd966dd ASRock E350M1: mptable.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit cd966dd075c5dbe5987bf8618d0ebe430cc331ac Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 20:20:56 2013 +0100 ASRock E350M1: mptable.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mptable.ramstage.o src/mainboard/asrock/e350m1/mptable.c: In function 'smp_write_config_table': src/mainboard/asrock/e350m1/mptable.c:58:3: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration] […] Including the header file `cpu/amd/amdfam14.h` declaring the function addresses this warning. The same change was done in the following commit for the AMD Persimmon board. commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 Reviewed-on: http://review.coreboot.org/137 Change-Id: I7912571fa57f6512b10fc9b5845427fcb6eb50c0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2966 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 21:37:57 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 21:07:30 2013, giving +2 See http://review.coreboot.org/2966 for details. -gerrit

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Patch merged into coreboot/master: 22bbb69 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 22bbb6942181771381081ef88089552a0408754a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 29 15:39:54 2013 +0100 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite` When building the ASRock E350M1, the following warning is shown. $ make # on Jenkins (build server) […] CC mainboard/asrock/e350m1/mainboard.ramstage.o src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable': src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration] […] This warning was introduced by moving the initialization of the ASF registers using `pm_iowrite` to `mainboard.c` in commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Thu Mar 21 22:21:28 2013 +0100 Asrock E350M1: Use SPD read code from F14 wrapper Reviewed-on: http://review.coreboot.org/2875 and is fixed by including `southbridge/amd/cimx/cimx_util.h` declaring `pm_iowrite`. Note, that the other AMD SB800 based boards seem to use the header file `southbridge/amd/sb800/sb800.h`, so no warning is shown for those. But since the CIMx SB800 code is used, the routines from the CIMx directory are more appropriate to declare these functions. So delete the commented out include line for this header too. Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2957 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 30 15:25:18 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 21:06:39 2013, giving +2 See http://review.coreboot.org/2957 for details. -gerrit

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Patch merged into coreboot/master: 5ed986b inteltool: Support PM registers on Cougar/Panther Point
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 5ed986b8ab6bbcf1dfcb7d43ab9d9c8c4bf2f60f Author: Nico Huber <nico.h(a)gmx.de> Date: Fri Mar 29 19:00:37 2013 +0100 inteltool: Support PM registers on Cougar/Panther Point This adds the power management register definitions for Intel's Cougar Point and Panther Point platform controller hubs (PCH). The definitions are actually a subset of the older ICH10R registers: I've added just those that are mentioned in the public specifications in [1] and [2]. I've tested dumping with an H77 PCH. NM70 is missing in [1]. Therefore, I didn't add it here. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/2985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 30 18:35:49 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 21:00:16 2013, giving +2 See http://review.coreboot.org/2985 for details. -gerrit

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Patch merged into coreboot/master: 82d2d442 wtm2: select write-combining memory for graphics
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 82d2d442c05255b073c97f78810de17101299602 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 16:37:18 2013 -0500 wtm2: select write-combining memory for graphics Auto-select marking the graphics memory as write-combining. Change-Id: Icf61c5cbd129a97a106f0aaeca4e010d4799b4b8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2981 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 30 02:32:24 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 20:57:22 2013, giving +2 See http://review.coreboot.org/2981 for details. -gerrit

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Patch merged into coreboot/master: 13a97f5 link: select write-combining memory for graphics
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 13a97f5f4112c93878d483b61e2827adf7e0b44a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 29 16:38:01 2013 -0500 link: select write-combining memory for graphics Auto-select marking the graphics memory as write-combining. Change-Id: I0b913f0b318bf57275643d3cfb5bc54ca8a005f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2982 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Sat Mar 30 02:46:53 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 20:57:03 2013, giving +2 See http://review.coreboot.org/2982 for details. -gerrit

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Patch merged into coreboot/master: ce872cb pci: don't load vga option rom before S3 check
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit ce872cb9afd55bc7bee8ebf08319e1400c860e71 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 28 15:59:19 2013 -0500 pci: don't load vga option rom before S3 check The pci device code was probing and loading the option rom before it did the S3 resume check for VGA option roms. Instead move this check before probing and loading so that we don't unnecessarily do work. Change-Id: If2e62d0c0e4b34b4f1bcd56ebcb9d3f54c6d0d24 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2979 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Mar 30 01:45:31 2013, giving +1 See http://review.coreboot.org/2979 for details. -gerrit

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Patch merged into coreboot/master: 8b5b764 console: Make use of CONFIG_USE_OPTION_TABLE
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 8b5b764af6562235823f03c04e8184f048ab6320 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Feb 13 11:07:38 2013 +0100 console: Make use of CONFIG_USE_OPTION_TABLE It makes much more sense to use CONFIG_USE_OPTION_TABLE instead of CONFIG_HAVE_CMOS_DEFAULT. As we want to read the used debug_level from our CMOS. This change makes it possible to change log_debug via nvramtool and make use of the new value after a reboot/poweroff. CONFIG_HAVE_CMOS_DEFAULT does have an other meaning Change-Id: I438dd01a2b4171dba2b73f2001511c71f4317725 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Reviewed-on: http://review.coreboot.org/2381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 23 06:37:49 2013, giving +2 Build-Tested: build bot (Jenkins) at Sat Mar 23 00:05:59 2013, giving +1 See http://review.coreboot.org/2381 for details. -gerrit

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coreboot-gerrit April 2013