Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3008
-gerrit
commit bfef102d7ae59bc29b6edd631ea6deef1602438c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Apr 1 16:49:31 2013 -0500
haswell: keep ROM cache enabled
The MP code on haswell was mirroring the BSPs MTRRs. In addition it
was cleaning up the ROM cache so that the MTRR register values were
the same once the OS was booted. Since the hyperthread sibling of
the BSP was going through this path the ROM cache was getting torn
down once the hyperthread was brought up.
That said, there was no differnce in observed boot time keeping the
ROM cache enabled.
Change-Id: I2a59988fcfeea9291202c961636ea761c2538837
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/cpu/intel/haswell/mp_init.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c
index cc13892..ddcff6c 100644
--- a/src/cpu/intel/haswell/mp_init.c
+++ b/src/cpu/intel/haswell/mp_init.c
@@ -181,8 +181,12 @@ ap_init(unsigned int cpu, void *microcode_ptr)
/* After SMM relocation a 2nd microcode load is required. */
intel_microcode_load_unlocked(microcode_ptr);
- /* Cleanup ROM caching. */
- cleanup_rom_caching();
+ /* The MTRR resources are core scoped. Therefore, there is no need
+ * to do the same work twice. Additionally, this check keeps the
+ * ROM cache enabled on the BSP since its hyperthread sibling won't
+ * call cleanup_rom_caching(). */
+ if ((lapicid() & 1) == 0)
+ cleanup_rom_caching();
/* FIXME(adurbin): park CPUs properly -- preferably somewhere in a
* reserved part of memory that the OS cannot get to. */
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3007
-gerrit
commit 8b70577af53153e19e40164f74aa56ce8ceff4cc
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Apr 1 15:40:45 2013 -0500
haswell: use new interface to disable rom caching
The haswell code was using the old assumption of which MTRR
was used for the ROM cache. Now that there is an API for doing
this use it as the old assumption is no longer valid.
Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/cpu/intel/haswell/mp_init.c | 23 +----------------------
1 file changed, 1 insertion(+), 22 deletions(-)
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c
index c8bd5c2..cc13892 100644
--- a/src/cpu/intel/haswell/mp_init.c
+++ b/src/cpu/intel/haswell/mp_init.c
@@ -145,28 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel)
* ensure the caching is disabled for tha APs before going to sleep. */
static void cleanup_rom_caching(void)
{
-#if CONFIG_CACHE_ROM
- msr_t msr;
- unsigned int last_var_mtrr;
-
- msr = rdmsr(MTRRcap_MSR);
- last_var_mtrr = (msr.lo & 0xff) - 1;
-
- /* Check if the MTRR is valid. */
- msr = rdmsr(MTRRphysMask_MSR(last_var_mtrr));
- if ((msr.lo & MTRRphysMaskValid) == 0)
- return;
- msr = rdmsr(MTRRphysBase_MSR(last_var_mtrr));
- /* Assum that if the MTRR is of write protected type, the MTRR is used
- * to cache the ROM. */
- if ((msr.lo & MTRR_NUM_TYPES) == MTRR_TYPE_WRPROT) {
- msr.lo = msr.hi = 0;
- disable_cache();
- wrmsr(MTRRphysMask_MSR(last_var_mtrr), msr);
- wrmsr(MTRRphysBase_MSR(last_var_mtrr), msr);
- enable_cache();
- }
-#endif
+ x86_mtrr_disable_rom_caching();
}
/* By the time APs call ap_init() caching has been setup, and microcode has
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3004
-gerrit
commit fe9606cf3c184ad7fbaee518c51d622e43819e38
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Apr 1 15:33:02 2013 -0500
x86: add AUTO_CACHE_ROM_BSP option
When the AUTO_CACHE_ROM_BSP option is selected the ROM cache
is automatically enabled for the BSP. That way, there doesn't
need to be any other callers of x86_mtrr_enable_rom_caching()
throughout the code base.
Change-Id: If236870ff7c3fd0cb317cbb80ee58cc9a266eeb0
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/cpu/x86/Kconfig | 7 +++++++
src/cpu/x86/mtrr/mtrr.c | 4 ++++
2 files changed, 11 insertions(+)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 4c5176b..80bd2d7 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -62,6 +62,13 @@ config CACHE_ROM
When selected a variable range MTRR is allocated for coreboot and
the bootloader enables caching of the system ROM for faster access.
+config AUTO_CACHE_ROM_BSP
+ bool
+ default n
+ depends on CACHE_ROM
+ help
+ Automatically enable ROM caching for the BSP.
+
config SMM_TSEG
bool
default n
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 6089127..c205da3 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -792,6 +792,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
commit_var_mtrrs(addr_space, mtrr_default_type, !!above4gb,
address_bits);
enable_var_mtrr(mtrr_default_type);
+#if CONFIG_AUTO_CACHE_ROM_BSP
+ if (boot_cpu())
+ x86_mtrr_enable_rom_caching();
+#endif
enable_cache();
}
the following patch was just integrated into master:
commit 9c07c8f53db10e1c93f41e37a9ba8a246fa0336e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Mar 22 11:08:39 2013 -0700
lynxpoint: Move ACPI NVS into separate CBMEM table
The ACPI NVS region was setup in place and there was a CBMEM
table that pointed to it. In order to be able to use NVS
earlier the CBMEM region is allocated for NVS itself during
the LPC device init and the ACPI tables point to it in CBMEM.
The current cbmem region is renamed to ACPI_GNVS_PTR to
indicate that it is really a pointer to the GNVS and does
not actually contain the GNVS.
Change-Id: I31ace432411c7f825d86ca75c63dd79cd658e891
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Build-Tested: build bot (Jenkins) at Fri Mar 29 23:21:45 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:35:47 2013, giving +2
See http://review.coreboot.org/2970 for details.
-gerrit
the following patch was just integrated into master:
commit ebf142a12ce4911b766bd618483434519efba0d5
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Mar 29 16:23:23 2013 -0500
boot: add disable_cache_rom() function
On certain architectures such as x86 the bootstrap processor
does most of the work. When CACHE_ROM is employed it's appropriate
to ensure that the caching enablement of the ROM is disabled so that
the caching settings are symmetric before booting the payload or OS.
Tested this on an x86 machine that turned on ROM caching. Linux did not
complain about asymmetric MTRR settings nor did the ROM show up as
cached in the MTRR settings.
Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/2980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Sat Mar 30 02:18:43 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 23:29:11 2013, giving +2
See http://review.coreboot.org/2980 for details.
-gerrit