coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: b39ba2e lynxpoint: Basic configuration of SerialIO devices
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit b39ba2efcfb0da48c8e7719d1c8db037b567a8bc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:21:14 2013 -0700 lynxpoint: Basic configuration of SerialIO devices This adds configuration of SerialIO devices in the Lynxpoint-LP chipset. This includes DMA, I2C, SPI, UART, and SDIO controllers. There is assorted magic setup necessary for the devices and while it is similar for each device there are subtle differences in some register settings. These devices must be put into "ACPI Mode" in order to take advantage of S0ix. When in ACPI mode the allocated PCI BARs must be passed to ACPI so it can be relayed to the OS. When the devices are in ACPI mode BAR0+BAR1 is saved into ACPI NVS and then updated and returned when the OS calls _CRS. Note that is is not entirely complete yet. We need to update the IASL compiler in our build environment to support ACPI 5.0 in order to be able to pass the FixedDMA entries to the kernel. There are also no ACPI methods defined yet to do D0->D3->D0 transitions for actually entering/exiting S0ix states. This is hard to test right now because our kernel does not support any of these devices in ACPI mode. I was able to build and test the upstream bleeding-edge branch of the linux-pm git tree. With that tree I was able to enumerate and load the driver for the DesignWare I2C driver and attempt to probe the I2C bus -- although there are no devices attatched. I am also able to see the resources from ACPI in /proc/iomem get reserved properly in the kernel. Change-Id: Ie311addd6a25f3b7edf3388fe68c1cd691a0a500 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 23:36:18 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:28:51 2013, giving +2 See http://review.coreboot.org/2971 for details. -gerrit

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Patch merged into coreboot/master: 9591210 wtm2: Enable SerialIO devices in ACPI mode
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 9591210d2caaa356bce63528f48e3cb02f787136 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:22:24 2013 -0700 wtm2: Enable SerialIO devices in ACPI mode This enables all of the SerialIO devices and sets the flag to put them in ACPI mode. Change-Id: I7436c47d26028e95bbefafc320854c7cc34a4d44 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2972 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 29 23:50:17 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:27:55 2013, giving +2 See http://review.coreboot.org/2972 for details. -gerrit

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Patch merged into coreboot/master: a2d6a40 lynxpoint: Fix LP clock gating setup for LPC
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit a2d6a40480c97043e9126c0fbc9e1a79db22d408 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:24:45 2013 -0700 lynxpoint: Fix LP clock gating setup for LPC This bit offset is incorrect and should only be set based on another bit in a different register. Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2973 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 30 00:04:51 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:27:21 2013, giving +2 See http://review.coreboot.org/2973 for details. -gerrit

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Patch merged into coreboot/master: 0ce2b43 Minor Kconfig help text fix
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 0ce2b4368286df8267bfb290b206671825981248 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Mon Apr 1 13:45:44 2013 +0200 Minor Kconfig help text fix I did not check what was once after the 'and'. Change-Id: I9f3f725bec281a94abdb2eeb692a96fecdebcc0c Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/2999 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Apr 1 22:58:47 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 23:27:07 2013, giving +2 See http://review.coreboot.org/2999 for details. -gerrit

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Patch merged into coreboot/master: 0703ec4 chromeos: honor MOCK_TPM=1
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 0703ec4fb2f0342e88fa50dfae21710019774ad1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 00:16:11 2013 -0500 chromeos: honor MOCK_TPM=1 The TPM code wasn't previously honoring MOCK_TPM=1. Because of this, boards with TPMs that didn't handle S3 resume properly would cause a hard reset. Allow one to build with MOCK_TPM=1 on the command line so that S3 can still work. Change-Id: I9adf06647de285c0b0a3203d8897be90d7783a1e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2976 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 30 00:48:19 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:26:17 2013, giving +2 See http://review.coreboot.org/2976 for details. -gerrit

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Patch merged into coreboot/master: d6d6db3 lynxpoint: fix enable_pm1() function
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit d6d6db3717d09f2b6a4590eec6016ca7d417c2f9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 21:13:02 2013 -0500 lynxpoint: fix enable_pm1() function The new enable_pm1() function was doing 2 things wrong: 1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register. The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode. Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2978 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 30 02:02:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:25:20 2013, giving +2 See http://review.coreboot.org/2978 for details. -gerrit

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Patch merged into coreboot/master: bab0a0b PDCurses: pdcscrn.c: Use `#ifdef` instead of `#if CONFIG_SPEAKER`
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit bab0a0b577ba8cc28aa1e2b2e9ec65fb98edced1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Mar 27 09:50:30 2013 +0100 PDCurses: pdcscrn.c: Use `#ifdef` instead of `#if CONFIG_SPEAKER` Building libpayload with the PDCurses backend the following warning is shown. /src/coreboot/payloads/libpayload(master) $ make clean /src/coreboot/payloads/libpayload(master) $ make […] CC curses/pdcurses-backend/pdcscrn.libcurses.o curses/pdcurses-backend/pdcscrn.c: In function 'PDC_scr_open': curses/pdcurses-backend/pdcscrn.c:75:5: warning: "CONFIG_SPEAKER" is not defined [-Wundef] […] The GCC documentation states [1] In some contexts this shortcut is undesirable. The -Wundef option causes GCC to warn whenever it encounters an identifier which is not a macro in an ‘#if’. and therefore use `#ifdef` [2] to silence this warning. No functional change is done, as `CONFIG_SPEAKER` is assigned the value `Y` when defined. There was some discussion going on the list [3], but my points in there turned out to be incorrect. [1] http://gcc.gnu.org/onlinedocs/cpp/If.html [2] http://gcc.gnu.org/onlinedocs/cpp/Ifdef.html [3] http://www.coreboot.org/pipermail/coreboot/2013-March/075561.html Change-Id: I8e9c9b5d01985b21ad05018986d614cf9bf2b439 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2934 Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Apr 1 23:21:22 2013, giving +1 See http://review.coreboot.org/2934 for details. -gerrit

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Patch merged into coreboot/master: af3158c lynxpoint: split clearing and enabling of smm
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit af3158c0cfd6034bbdc42a0488382c4be1a7a388 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 27 20:57:28 2013 -0500 lynxpoint: split clearing and enabling of smm Previously southbridge_smm_init() was provided that did both the clearing of the SMM state and enabling SMIs. This is troublesome in how haswell machines bring up the APs. The BSP enters SMM once to determine if parallel SMM relocation is possible. If it is possible the BSP releases the APs to do SMM relocation. Normally, after the APs complete the SMM relocation, the BSP would then re-enter the relocation handler to relocate its own SMM space. However, because SMIs were previously enabled it is possible for an SMI event to occur before the APs are complete or have entered the relocation handler. This is bad because the BSP will turn off parallel SMM save state. Additionally, this is a problem because the relocation handler is not written to handle regular SMIs which can cause an SMI storm which effectively looks like a hung machine. Correct these issues by turning on SMIs after all the SMM relocation has occurred. Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2977 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 30 01:02:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 1 23:24:31 2013, giving +2 See http://review.coreboot.org/2977 for details. -gerrit

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Patch merged into coreboot/master: 9ebd8ea inteltool: Allow to override Makefile variables
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 9ebd8ea7cfd379cca56a2c48324bdfbe52ff6bab Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 31 22:15:43 2013 +0200 inteltool: Allow to override Makefile variables Allow to override the variables `CC`, `INSTALL`, `PREFIX`, `CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`. This way for example a different compiler can easily be used. CC=clang make As a side note, Clang in contrast to GCC does *not* issue the following warnings. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] These are only shown under 32-bit and not 64-bit $ uname -m i686 and are going to be fixed in a separate patch. Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Apr 1 21:50:59 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 22:40:44 2013, giving +2 See http://review.coreboot.org/2996 for details. -gerrit

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Patch merged into coreboot/master: 42c5501 inteltool: Add Cougar/Panther Point GPIO defaults
by gerrit＠coreboot.org 01 Apr '13

01 Apr '13

the following patch was just integrated into master: commit 42c5501c3941ce0ddfc14bcd5b9d02d73d4f4e30 Author: Nico Huber <nico.h(a)gmx.de> Date: Mon Apr 1 15:38:44 2013 +0200 inteltool: Add Cougar/Panther Point GPIO defaults This adds default values for the GPIO setup on Intel's Cougar Point and Panther Point platform controller hubs (PCH). Values are taken from [1] and [2], respectively. I've tested this with an H77 PCH. See below for the output. [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet Document-Number: 324645-006 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) - Datasheet Document-Number: 326776-003 $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/3001 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Apr 1 22:15:36 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 1 22:39:30 2013, giving +2 See http://review.coreboot.org/3001 for details. -gerrit

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coreboot-gerrit April 2013