coreboot-gerrit April 2013

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New patch to review for coreboot: 16e21e7 Persimmon/Fam14/SB800 DSDT: Split into common areas
by Mike Loptien 09 Apr '13

09 Apr '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3048 -gerrit commit 16e21e7fa56c8a1745c5c0004df4771d0e360250 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Mon Mar 18 11:19:26 2013 -0600 Persimmon/Fam14/SB800 DSDT: Split into common areas Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/cpu/amd/agesa/family14/acpi/cpu.asl | 41 + src/mainboard/amd/persimmon/acpi/gpe.asl | 83 + src/mainboard/amd/persimmon/acpi/mainboard.asl | 68 + src/mainboard/amd/persimmon/acpi/routing.asl | 89 +- src/mainboard/amd/persimmon/acpi/sleep.asl | 121 ++ src/mainboard/amd/persimmon/acpi/superio.asl | 18 + src/mainboard/amd/persimmon/acpi/thermal.asl | 21 + src/mainboard/amd/persimmon/acpi/usb.asl | 161 -- src/mainboard/amd/persimmon/acpi/usb_oc.asl | 174 ++ src/mainboard/amd/persimmon/dsdt.asl | 1819 +------------------- .../amd/agesa/family14/acpi/northbridge.asl | 130 ++ src/southbridge/amd/cimx/sb800/acpi/audio.asl | 47 + src/southbridge/amd/cimx/sb800/acpi/fch.asl | 371 ++++ src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 85 + src/southbridge/amd/cimx/sb800/acpi/pcie.asl | 521 ++++++ .../amd/cimx/sb800/acpi/sleepstates.asl | 37 + src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 114 ++ src/southbridge/amd/cimx/sb800/acpi/usb.asl | 56 + 18 files changed, 1920 insertions(+), 2036 deletions(-) diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl new file mode 100644 index 0000000..79a3c83 --- /dev/null +++ b/src/cpu/amd/agesa/family14/acpi/cpu.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ + Processor( + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + C001, /* name space name */ + 1, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } +} /* End _PR scope */ + diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl new file mode 100644 index 0000000..6ad1ad4 --- /dev/null +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ + +/* Contains the GPEs for USB overcurrent */ +#include "usb_oc.asl" + diff --git a/src/mainboard/amd/persimmon/acpi/mainboard.asl b/src/mainboard/amd/persimmon/acpi/mainboard.asl new file mode 100644 index 0000000..49ea44f --- /dev/null +++ b/src/mainboard/amd/persimmon/acpi/mainboard.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Data to be patched by the BIOS during POST */ +/* FIXME the patching is not done yet! */ +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +Scope(\_SB) { + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } +} + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ + diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index 7a871da..e98047c 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -64,37 +64,17 @@ Scope(\_SB) { Package(){0x0007FFFF, 2, INTB, 0 }, Package(){0x0007FFFF, 3, INTC, 0 }, - Package(){0x0009FFFF, 0, INTB, 0 }, - Package(){0x0009FFFF, 1, INTC, 0 }, - Package(){0x0009FFFF, 2, INTD, 0 }, - Package(){0x0009FFFF, 3, INTA, 0 }, - - Package(){0x000AFFFF, 0, INTC, 0 }, - Package(){0x000AFFFF, 1, INTD, 0 }, - Package(){0x000AFFFF, 2, INTA, 0 }, - Package(){0x000AFFFF, 3, INTB, 0 }, - - Package(){0x000BFFFF, 0, INTD, 0 }, - Package(){0x000BFFFF, 1, INTA, 0 }, - Package(){0x000BFFFF, 2, INTB, 0 }, - Package(){0x000BFFFF, 3, INTC, 0 }, - - Package(){0x000CFFFF, 0, INTA, 0 }, - Package(){0x000CFFFF, 1, INTB, 0 }, - Package(){0x000CFFFF, 2, INTC, 0 }, - Package(){0x000CFFFF, 3, INTD, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ + /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */ + Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */ Package(){0x0013FFFF, 0, INTC, 0 }, Package(){0x0013FFFF, 1, INTB, 0 }, @@ -102,9 +82,7 @@ Scope(\_SB) { Package(){0x0016FFFF, 0, INTC, 0 }, Package(){0x0016FFFF, 1, INTB, 0 }, - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ - - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, @@ -160,34 +138,19 @@ Scope(\_SB) { Package(){0x0007FFFF, 2, 0, 17 }, Package(){0x0007FFFF, 3, 0, 18 }, - /* Bus 0, Dev 9 - PCIe Bridge for network card */ - Package(){0x0009FFFF, 0, 0, 17 }, - Package(){0x0009FFFF, 1, 0, 16 }, - Package(){0x0009FFFF, 2, 0, 17 }, - Package(){0x0009FFFF, 3, 0, 18 }, - /* Bus 0, Dev A - PCIe Bridge for network card */ - Package(){0x000AFFFF, 0, 0, 18 }, - Package(){0x000AFFFF, 1, 0, 16 }, - Package(){0x000AFFFF, 2, 0, 17 }, - Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ + /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, - /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; - * EHCI, dev 18, 19 func 2 */ + /* OHCI, dev 18, 19, 22 func 0 + * EHCI, dev 18, 19, 22 func 2 */ Package(){0x0012FFFF, 0, 0, 18 }, Package(){0x0012FFFF, 1, 0, 17 }, - /* Package(){0x0012FFFF, 2, 0, 18 }, */ Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 17 }, - /* Package(){0x0013FFFF, 2, 0, 16 }, */ - - /* Package(){0x00140000, 0, 0, 16 }, */ Package(){0x0016FFFF, 0, 0, 18 }, Package(){0x0016FFFF, 1, 0, 17 }, @@ -299,36 +262,6 @@ Scope(\_SB) { Package(){0x0000FFFF, 3, 0, 18 }, }) - Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - Name(PE0, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, INTA, 0 }, @@ -390,7 +323,7 @@ Scope(\_SB) { }) Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */ Package(){0x0003FFFF, 0, 0, 0x14 }, Package(){0x0003FFFF, 1, 0, 0x15 }, Package(){0x0003FFFF, 2, 0, 0x16 }, diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl new file mode 100644 index 0000000..a109151 --- /dev/null +++ b/src/mainboard/amd/persimmon/acpi/sleep.asl @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) +} /* End Method(\_WAK) */ + diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl new file mode 100644 index 0000000..b12cca6 --- /dev/null +++ b/src/mainboard/amd/persimmon/acpi/superio.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No SuperIO device or functionality yet */ diff --git a/src/mainboard/amd/persimmon/acpi/thermal.asl b/src/mainboard/amd/persimmon/acpi/thermal.asl new file mode 100644 index 0000000..2f50475 --- /dev/null +++ b/src/mainboard/amd/persimmon/acpi/thermal.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Thermal Zones have been #if 0 for a long time. + * Removing it for now because it doesn't seem to + * do anything when enabled anyway. + */ diff --git a/src/mainboard/amd/persimmon/acpi/usb.asl b/src/mainboard/amd/persimmon/acpi/usb.asl deleted file mode 100644 index 2822ffd..0000000 --- a/src/mainboard/amd/persimmon/acpi/usb.asl +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* simple name description */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl new file mode 100644 index 0000000..ee00fbd --- /dev/null +++ b/src/mainboard/amd/persimmon/acpi/usb_oc.asl @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index acc85c6..1288929 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -19,1820 +19,45 @@ /* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ - - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ - - /* - * Processor Object - * - */ - Scope (\_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C002, /* name space name */ - 2, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C003, /* name space name */ - 3, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + #include <cpu/amd/agesa/family14/acpi/cpu.asl> #include "acpi/routing.asl" Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> - Method(CkOT, 0){ - - if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ - - if(CondRefOf(\_OSI,Local1)) - { - Store(1, OSTP) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSTP) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSTP) /* Linux */ - } Else { - Store(4, OSTP) /* Gotta be WinCE */ - } - } - Return(OSTP) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PIRA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PIRB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PIRC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIRD) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRD) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PIRE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PIRF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PIRG) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRG) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PIRH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIRH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - - /* Supported sleep states: */ - Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - - If (LAnd(SSFG, 0x01)) { - Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ - } - If (LAnd(SSFG, 0x02)) { - Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ - } - If (LAnd(SSFG, 0x04)) { - Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ - } - If (LAnd(SSFG, 0x08)) { - Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ - } - - Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ - - Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ - Name(CSMS, 0) /* Current System State */ - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, PWST) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" - - /* South Bridge */ - Scope(\_SB) { /* Start \_SB scope */ - #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - - /* Operating System Capabilities Method */ - Method(_OSC,4) - { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - } - - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - - Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ - - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ - Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } - } - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#if 0 - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ -#endif - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ - - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ -#if 0 - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) -#endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ -#if 0 - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } -#endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - CkOT() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ } - } /* End Scope SI */ -#if 0 - /* SMBUS Support */ - Mutex (SBX0, 0x00) - OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) - Field (SMB0, ByteAcc, NoLock, Preserve) { - HSTS, 8, /* SMBUS status */ - SSTS, 8, /* SMBUS slave status */ - HCNT, 8, /* SMBUS control */ - HCMD, 8, /* SMBUS host cmd */ - HADD, 8, /* SMBUS address */ - DAT0, 8, /* SMBUS data0 */ - DAT1, 8, /* SMBUS data1 */ - BLKD, 8, /* SMBUS block data */ - SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ - SEVT, 8, /* SMBUS slave event */ - SDAT, 8 /* SMBUS slave data */ - } - - Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ - Store (0x1E, HSTS) - Store (0xFA, Local0) - While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { - Stall (0x64) - Decrement (Local0) - } - - Return (Local0) - } - - Method (SWTC, 1, NotSerialized) { - Store (Arg0, Local0) - Store (0x07, Local2) - Store (One, Local1) - While (LEqual (Local1, One)) { - Store (And (HSTS, 0x1E), Local3) - If (LNotEqual (Local3, Zero)) { /* read sucess */ - If (LEqual (Local3, 0x02)) { - Store (Zero, Local2) - } - - Store (Zero, Local1) - } - Else { - If (LLess (Local0, 0x0A)) { /* read failure */ - Store (0x10, Local2) - Store (Zero, Local1) - } - Else { - Sleep (0x0A) /* 10 ms, try again */ - Subtract (Local0, 0x0A, Local0) - } - } - } - - Return (Local2) - } - - Method (SMBR, 3, NotSerialized) { - Store (0x07, Local0) - If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { - Store (WCLR (), Local0) /* clear SMBUS status register before read data */ - If (LEqual (Local0, Zero)) { - Release (SBX0) - Return (0x0) - } - - Store (0x1F, HSTS) - Store (Or (ShiftLeft (Arg1, One), One), HADD) - Store (Arg2, HCMD) - If (LEqual (Arg0, 0x07)) { - Store (0x48, HCNT) /* read byte */ - } - - Store (SWTC (0x03E8), Local1) /* 1000 ms */ - If (LEqual (Local1, Zero)) { - If (LEqual (Arg0, 0x07)) { - Store (DAT0, Local0) - } - } - Else { - Store (Local1, Local0) - } - - Release (SBX0) - } - - /* DBGO("the value of SMBusData0 register ") */ - /* DBGO(Arg2) */ - /* DBGO(" is ") */ - /* DBGO(Local0) */ - /* DBGO("\n") */ - - Return (Local0) - } - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } + } /* End Scope(_SB) */ - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } -#endif + #include "acpi/gpe.asl" + #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> + #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl new file mode 100644 index 0000000..2441706 --- /dev/null +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* The internal GFX bridge */ +Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APR1) } /* APIC mode */ + Return (PR1) /* PIC Mode */ + } +} /* end AGPB */ + +/* The internal GFX bridge */ +Device(HDMI) { + Name(_ADR, 0x00010001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APR1) } /* APIC mode */ + Return (PR1) /* PIC Mode */ + } +} /* end HDMI */ + +/* Dev 2 & 3 are external GFX bridges, not used in Family14 */ + +/* Dev4 GPP0 Root Port Bridge */ +Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Dev5 GPP1 Root Port Bridge */ +Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Dev6 GPP2 Root Port Bridge */ +Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* The onboard EtherNet chip */ +Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +Device(PE20) { + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ +} /* end PE20 */ + +Device(PE21) { + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ +} /* end PE21 */ + +Device(PE22) { + Name(_ADR, 0x00150002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ +} /* end PE22 */ + +Device(PE23) { + Name(_ADR, 0x00150003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ +} /* end PE23 */ + + diff --git a/src/southbridge/amd/cimx/sb800/acpi/audio.asl b/src/southbridge/amd/cimx/sb800/acpi/audio.asl new file mode 100644 index 0000000..a780752 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/audio.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } +} /* end AZHD */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl new file mode 100644 index 0000000..1a7f633 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -0,0 +1,371 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* South Bridge */ +/* _SB.PCI0 */ + +/* Operating System Capabilities Method */ +Method(_OSC,4) +{ /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } +} + +Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) +} +Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ +} /* end _PRT */ + +/* Describe the Southbridge devices */ + +#include "pcie.asl" + +/* PCI slot 1, 2, 3 */ +Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } +} + +Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" +} /* end STCR */ + +#include "usb.asl" + +Device(SBUS) { + Name(_ADR, 0x00140000) +} /* end SBUS */ + +/* Primary (and only) IDE channel */ +Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" +} /* end IDEC */ + +#include "audio.asl" + +#include "lpc.asl" + +Device(HPBR) { + Name(_ADR, 0x00140004) +} /* end HostPciBr */ + +Device(ACAD) { + Name(_ADR, 0x00140005) +} /* end Ac97audio */ + +Device(ACMD) { + Name(_ADR, 0x00140006) +} /* end Ac97modem */ + +Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) +}) /* End Name(_SB.PCI0.CRES) */ + +Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ +} /* end of Method(_SB.PCI0._CRS) */ + +/* +* +* FIRST METHOD CALLED UPON BOOT +* +* 1. If debugging, print current OS and ACPI interpreter. +* 2. Get PCI Interrupt routing from ACPI VSM, this +* value is based on user choice in BIOS setup. +*/ +Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ +} /* End Method(_SB._INI) */ + +Scope(\){ + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } +} + +Scope(\_SB) { + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } +} /* End Scope(_SB) */ + diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl new file mode 100644 index 0000000..62eb903 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + #include "acpi/superio.asl" +} /* end LIBR */ + diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl new file mode 100644 index 0000000..435bcb5 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -0,0 +1,521 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\) { + /* PCI IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } +} + +Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* SATA reg 24h Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* OHCI0 reg 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* SMBUS reg 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* SMBUS reg 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* SMBUS reg 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* SMBUS reg 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PIRA) + Store(0, PIRB) + Store(0, PIRC) + Store(0, PIRD) + Store(0, PIRE) + Store(0, PIRF) + Store(0, PIRG) + Store(0, PIRH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PIRA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_SRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PIRB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PIRC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIRD) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PIRE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PIRF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PIRG) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PIRH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + diff --git a/src/southbridge/amd/cimx/sb800/acpi/sleepstates.asl b/src/southbridge/amd/cimx/sb800/acpi/sleepstates.asl new file mode 100644 index 0000000..889c499 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/sleepstates.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Supported sleep states: */ +Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + +If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ +} +If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ +} +If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ +} + +Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + +Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ +Name(CSMS, 0) /* Current System State */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl new file mode 100644 index 0000000..19ae92b --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* SMBUS Support */ +Mutex (SBX0, 0x00) +OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ +} + +Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) +} + +Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) +} + +Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) +} + diff --git a/src/southbridge/amd/cimx/sb800/acpi/usb.asl b/src/southbridge/amd/cimx/sb800/acpi/usb.asl new file mode 100644 index 0000000..84f7cd2 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/usb.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH1 */ + +Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH2 */ + +Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH3 */ + +Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH4 */ + +Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) +} /* end UEH1 */ +

1 0

Patch set updated for coreboot: 9a1eb3e armv7: replace read/write macros with inlines
by David Hendricks 09 Apr '13

09 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3045 -gerrit commit 9a1eb3e7d0a86fd98b5df29602a319bcd586b6d7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Apr 8 20:01:18 2013 -0700 armv7: replace read/write macros with inlines This enables type checking for safety as to help prevent errors like http://review.coreboot.org/#/c/3038/ . Now compilation fails if the wrong type is passed into readb/readw/readl/writeb/writew/writel or other macros in io.h. This also deprecates readw/writew. The previous definition was 16-bits which is incorrect since wordsize on ARMv7 is 32-bits and there was only 1 instance of writew (#if 0'd anyway). Going forward we should always use read{8,16,32} and write{8,16,32} where N specifies the exact length rather than relying on ambiguous definition of wordsize. Since many macros relied on __raw_*, which were basically the same (minus data memory barrier instructions), this patch also gets rid of __raw_*. There were parts of the code which ended up using these macros consecutively, for example: setbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); In such cases the safe versions of readl() and writel() should be used anyway. Note: This also fixes two dubious casts as to avoid breaking compilation. Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 222 ++++++++---------------------- src/cpu/samsung/exynos5-common/cpu_info.c | 2 +- src/cpu/samsung/exynos5250/clock.c | 6 +- src/cpu/samsung/exynos5250/uart.c | 2 +- 4 files changed, 66 insertions(+), 166 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index b99e014..e62d579 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -1,6 +1,8 @@ /* - * linux/include/asm-arm/io.h + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. * + * Copyright (C) 2013 Google Inc. * Copyright (C) 1996-2000 Russell King * * This program is free software; you can redistribute it and/or modify @@ -8,6 +10,7 @@ * published by the Free Software Foundation. * * Modifications: + * 08-Apr-2013 G Replaced several macros with inlines for type safety. * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both * constant addresses and variable addresses. * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture @@ -24,102 +27,53 @@ #include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> -static inline void sync(void) +static inline uint8_t read8(const void *addr) { + uint8_t v = *(volatile uint8_t *)addr; + dmb(); + return v; } -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#if 0 -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) +static inline uint16_t read16(const void *addr) { - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - __arch_putb(*buf++, addr); + uint16_t v = *(volatile uint16_t *)addr; + dmb(); + return v; } -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +static inline uint32_t read32(const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - __arch_putw(*buf++, addr); + uint32_t v = *(volatile uint32_t *)addr; + dmb(); + return v; } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +static inline void write8(uint8_t val, const void *addr) { - uint32_t *buf = (uint32_t *)data; - while(longlen--) - __arch_putl(*buf++, addr); + dmb(); + *(volatile uint8_t *)addr = val; } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +static inline void write16(uint16_t val, const void *addr) { - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - *buf++ = __arch_getb(addr); + dmb(); + *(volatile uint16_t *)addr = val; } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +static inline void write32(uint32_t val, const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - *buf++ = __arch_getw(addr); + dmb(); + *(volatile uint32_t *)addr = val; } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) -{ - uint32_t *buf = (uint32_t *)data; - while(longlen--) - *buf++ = __arch_getl(addr); -} -#endif - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define __iormb() dmb() -#define __iowmb() dmb() - -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) - -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) - /* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) + * FIXME: These are to avoid breaking existing ARM code. We should eventually + * re-factor all code to specify the data length intended. + */ +#define readb(a) read8(a) +#define writeb(v,a) write8(v,a) +#define readl(a) read32(a) +#define writel(v,a) write32(v,a) /* * Clear and set bits in one shot. These macros can be used to clear and @@ -129,8 +83,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * in the 'set' parameter. */ -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) +#define out_arch(type,endian,a,v) write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(read##type(a)) #define out_le32(a,v) out_arch(l,le32,a,v) #define out_le16(a,v) out_arch(w,le16,a,v) @@ -144,8 +98,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) +#define out_8(a,v) writeb(v,a) +#define in_8(a) readb(a) #define clrbits(type, addr, clear) \ out_##type((addr), in_##type(addr) & ~(clear)) @@ -177,13 +131,6 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) /* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* * IO port access primitives * ------------------------- * @@ -202,27 +149,26 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * address to a memory address. * * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. + * by introducing sequence points into the in*() definitions. * * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. */ #ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) +#define outb(v,p) writeb(v,__io(p)) +#define outw(v,p) writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) writel(cpu_to_le32(v),__io(p)) -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) +#define inb(p) ({ unsigned int __v = readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(readl(__io(p))); __v; }) -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) +#define outsb(p,d,l) writesb(__io(p),d,l) +#define outsw(p,d,l) writesw(__io(p),d,l) +#define outsl(p,d,l) writesl(__io(p),d,l) -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#define insb(p,d,l) readsb(__io(p),d,l) +#define insw(p,d,l) readsw(__io(p),d,l) +#define insl(p,d,l) readsl(__io(p),d,l) #endif #define outb_p(val,port) outb((val),(port)) @@ -285,13 +231,13 @@ extern void __readwrite_bug(const char *fn); */ #ifdef __mem_pci -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) +#define readb(c) ({ unsigned int __v = readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(readl(__mem_pci(c))); __v; }) -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) +#define writeb(v,c) writeb(v,__mem_pci(c)) +#define writew(v,c) writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) writel(cpu_to_le32(v),__mem_pci(c)) #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) @@ -316,66 +262,20 @@ check_signature(unsigned long io_addr, const unsigned char *signature, out: return retval; } - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - #endif /* __mem_pci */ -/* FIXME(dhendrix): added to make uart8250_mem code happy. Note: lL */ -static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) -{ - return readb(addr); -} - -static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) -{ - return readw(addr); -} - -static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) -{ - return readl(addr); -} - -static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) -{ - writeb(value, addr); -} - -static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) -{ - writew(value, addr); -} - -static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) -{ - writel(value, addr); -} - - /* * If this architecture has ISA IO, then define the isa_read/isa_write * macros. */ #ifdef __mem_isa -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_readb(addr) readb(__mem_isa(addr)) +#define isa_readw(addr) readw(__mem_isa(addr)) +#define isa_readl(addr) readl(__mem_isa(addr)) +#define isa_writeb(val,addr) writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) writel(val,__mem_isa(addr)) #define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) #define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) #define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) diff --git a/src/cpu/samsung/exynos5-common/cpu_info.c b/src/cpu/samsung/exynos5-common/cpu_info.c index dec3c77..6b75473 100644 --- a/src/cpu/samsung/exynos5-common/cpu_info.c +++ b/src/cpu/samsung/exynos5-common/cpu_info.c @@ -65,7 +65,7 @@ int s5p_get_cpu_rev(void) void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS_PRO_ID); + s5p_cpu_id = readl((void *)EXYNOS_PRO_ID); s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); /* diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 6b79272..3622e28 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -379,7 +379,7 @@ void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = samsung_get_base_clock(); - unsigned int addr; + unsigned int *addr; unsigned int val; /* @@ -389,9 +389,9 @@ void set_mmc_clk(int dev_index, unsigned int div) * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] */ if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; + addr = &clk->div_fsys1; } else { - addr = (unsigned int)&clk->div_fsys2; + addr = &clk->div_fsys2; dev_index -= 2; } diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 75c5763..34d8e08 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -106,7 +106,7 @@ static void serial_setbrg_dev(void) */ #if 0 if (s5p_uart_divslot()) - writew(udivslot[val % 16], &uart->rest.slot); + writel(udivslot[val % 16], &uart->rest.slot); else writeb(val % 16, &uart->rest.value); #endif

1 0

Patch set updated for coreboot: 63f74ab armv7: replace read/write macros with inlines
by David Hendricks 09 Apr '13

09 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3045 -gerrit commit 63f74abee8713140ab7a6ed1a24b98c00eb10b70 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Apr 8 20:01:18 2013 -0700 armv7: replace read/write macros with inlines This enables type checking for safety as to help prevent errors like http://review.coreboot.org/#/c/3038/ . Now compilation fails if the wrong type is passed into readb/readw/readl/writeb/writew/writel or other macros in io.h. This also deprecates readw/writew. The previous definition was 16-bits which is incorrect since wordsize on ARM is 32-bits and there was only 1 instance of writew (#if 0'd anyway). Going forward we should always use read{8,16,32} and write{8,16,32} where N specifies the exact length rather than relying on ambiguous definitions of wordsize. Since many macros relied on __raw_*, which were basically the same (minus data memory barrier instructions), this patch also gets rid of __raw_*. There were parts of the code which ended up using these macros consecutively, for example: setbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); In such cases the safe versions of readl() and writel() should be used anyway. Note: This also fixes two dubious casts as to avoid breaking compilation. Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 222 ++++++++---------------------- src/cpu/samsung/exynos5-common/cpu_info.c | 2 +- src/cpu/samsung/exynos5250/clock.c | 6 +- src/cpu/samsung/exynos5250/uart.c | 2 +- 4 files changed, 66 insertions(+), 166 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index b99e014..e62d579 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -1,6 +1,8 @@ /* - * linux/include/asm-arm/io.h + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. * + * Copyright (C) 2013 Google Inc. * Copyright (C) 1996-2000 Russell King * * This program is free software; you can redistribute it and/or modify @@ -8,6 +10,7 @@ * published by the Free Software Foundation. * * Modifications: + * 08-Apr-2013 G Replaced several macros with inlines for type safety. * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both * constant addresses and variable addresses. * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture @@ -24,102 +27,53 @@ #include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> -static inline void sync(void) +static inline uint8_t read8(const void *addr) { + uint8_t v = *(volatile uint8_t *)addr; + dmb(); + return v; } -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#if 0 -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) +static inline uint16_t read16(const void *addr) { - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - __arch_putb(*buf++, addr); + uint16_t v = *(volatile uint16_t *)addr; + dmb(); + return v; } -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +static inline uint32_t read32(const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - __arch_putw(*buf++, addr); + uint32_t v = *(volatile uint32_t *)addr; + dmb(); + return v; } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +static inline void write8(uint8_t val, const void *addr) { - uint32_t *buf = (uint32_t *)data; - while(longlen--) - __arch_putl(*buf++, addr); + dmb(); + *(volatile uint8_t *)addr = val; } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +static inline void write16(uint16_t val, const void *addr) { - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - *buf++ = __arch_getb(addr); + dmb(); + *(volatile uint16_t *)addr = val; } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +static inline void write32(uint32_t val, const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - *buf++ = __arch_getw(addr); + dmb(); + *(volatile uint32_t *)addr = val; } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) -{ - uint32_t *buf = (uint32_t *)data; - while(longlen--) - *buf++ = __arch_getl(addr); -} -#endif - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define __iormb() dmb() -#define __iowmb() dmb() - -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) - -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) - /* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) + * FIXME: These are to avoid breaking existing ARM code. We should eventually + * re-factor all code to specify the data length intended. + */ +#define readb(a) read8(a) +#define writeb(v,a) write8(v,a) +#define readl(a) read32(a) +#define writel(v,a) write32(v,a) /* * Clear and set bits in one shot. These macros can be used to clear and @@ -129,8 +83,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * in the 'set' parameter. */ -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) +#define out_arch(type,endian,a,v) write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(read##type(a)) #define out_le32(a,v) out_arch(l,le32,a,v) #define out_le16(a,v) out_arch(w,le16,a,v) @@ -144,8 +98,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) +#define out_8(a,v) writeb(v,a) +#define in_8(a) readb(a) #define clrbits(type, addr, clear) \ out_##type((addr), in_##type(addr) & ~(clear)) @@ -177,13 +131,6 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) /* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* * IO port access primitives * ------------------------- * @@ -202,27 +149,26 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * address to a memory address. * * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. + * by introducing sequence points into the in*() definitions. * * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. */ #ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) +#define outb(v,p) writeb(v,__io(p)) +#define outw(v,p) writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) writel(cpu_to_le32(v),__io(p)) -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) +#define inb(p) ({ unsigned int __v = readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(readl(__io(p))); __v; }) -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) +#define outsb(p,d,l) writesb(__io(p),d,l) +#define outsw(p,d,l) writesw(__io(p),d,l) +#define outsl(p,d,l) writesl(__io(p),d,l) -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#define insb(p,d,l) readsb(__io(p),d,l) +#define insw(p,d,l) readsw(__io(p),d,l) +#define insl(p,d,l) readsl(__io(p),d,l) #endif #define outb_p(val,port) outb((val),(port)) @@ -285,13 +231,13 @@ extern void __readwrite_bug(const char *fn); */ #ifdef __mem_pci -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) +#define readb(c) ({ unsigned int __v = readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(readl(__mem_pci(c))); __v; }) -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) +#define writeb(v,c) writeb(v,__mem_pci(c)) +#define writew(v,c) writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) writel(cpu_to_le32(v),__mem_pci(c)) #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) @@ -316,66 +262,20 @@ check_signature(unsigned long io_addr, const unsigned char *signature, out: return retval; } - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - #endif /* __mem_pci */ -/* FIXME(dhendrix): added to make uart8250_mem code happy. Note: lL */ -static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) -{ - return readb(addr); -} - -static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) -{ - return readw(addr); -} - -static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) -{ - return readl(addr); -} - -static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) -{ - writeb(value, addr); -} - -static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) -{ - writew(value, addr); -} - -static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) -{ - writel(value, addr); -} - - /* * If this architecture has ISA IO, then define the isa_read/isa_write * macros. */ #ifdef __mem_isa -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_readb(addr) readb(__mem_isa(addr)) +#define isa_readw(addr) readw(__mem_isa(addr)) +#define isa_readl(addr) readl(__mem_isa(addr)) +#define isa_writeb(val,addr) writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) writel(val,__mem_isa(addr)) #define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) #define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) #define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) diff --git a/src/cpu/samsung/exynos5-common/cpu_info.c b/src/cpu/samsung/exynos5-common/cpu_info.c index dec3c77..6b75473 100644 --- a/src/cpu/samsung/exynos5-common/cpu_info.c +++ b/src/cpu/samsung/exynos5-common/cpu_info.c @@ -65,7 +65,7 @@ int s5p_get_cpu_rev(void) void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS_PRO_ID); + s5p_cpu_id = readl((void *)EXYNOS_PRO_ID); s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); /* diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 6b79272..3622e28 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -379,7 +379,7 @@ void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = samsung_get_base_clock(); - unsigned int addr; + unsigned int *addr; unsigned int val; /* @@ -389,9 +389,9 @@ void set_mmc_clk(int dev_index, unsigned int div) * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] */ if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; + addr = &clk->div_fsys1; } else { - addr = (unsigned int)&clk->div_fsys2; + addr = &clk->div_fsys2; dev_index -= 2; } diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 75c5763..34d8e08 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -106,7 +106,7 @@ static void serial_setbrg_dev(void) */ #if 0 if (s5p_uart_divslot()) - writew(udivslot[val % 16], &uart->rest.slot); + writel(udivslot[val % 16], &uart->rest.slot); else writeb(val % 16, &uart->rest.value); #endif

1 0

New patch to review for coreboot: 5d8295d siemens/sitemp_g1p1: Make ACPI report the right mmconf region
by Nico Huber 09 Apr '13

09 Apr '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3047 -gerrit commit 5d8295db3d966a7120b4589eb5e5e86e373610db Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Apr 9 15:41:23 2013 +0200 siemens/sitemp_g1p1: Make ACPI report the right mmconf region ACPI reported the entire space between top-of-memory and some (relatively) arbitrary limit as useful for MMIO. Unfortunately the HyperTransport configuration disagreed. Make them match up. Other boards are not affected since they don't report any region for that purpose at all (it seems). Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/include/cpu/amd/amdk8_sysconf.h | 2 ++ src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 10 +++++----- src/northbridge/amd/amdk8/acpi.c | 4 ++++ src/northbridge/amd/amdk8/northbridge.c | 3 +++ 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h index 3ae35fd..b367ac0 100644 --- a/src/include/cpu/amd/amdk8_sysconf.h +++ b/src/include/cpu/amd/amdk8_sysconf.h @@ -21,6 +21,8 @@ struct amdk8_sysconf_t { void *mb; // pointer for mb releated struct + unsigned mmconf_start; + unsigned mmconf_end; }; extern struct amdk8_sysconf_t sysconf; diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 9d64e89..a48a6de 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -255,8 +255,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) MPEN, 8 } - Name (IOLM,0xe0000000) - #include "acpi/platform.asl" Scope(\_SB) { @@ -385,6 +383,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) External (MMIO) External (TOM1) External (TOM2) + External (MMCB) /* MMConf Begin */ + External (MMCE) /* MMConf End */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ @@ -1186,9 +1186,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) CreateDWordField(CRES, ^EMM2._MAX, EM2E) CreateDWordField(CRES, ^EMM2._LEN, EM2L) - Store(TOM1, EM2B) - Subtract(IOLM, 1, EM2E) - Subtract(IOLM, TOM1, EM2L) + Store(MMCB, EM2B) + Subtract(MMCE, 1, EM2E) + Subtract(MMCE, MMCB, EM2L) If(LGreater(LOMH, 0xC0000)){ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 2eb39c0..0a6fbba 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -280,6 +280,10 @@ int k8acpi_write_vars(void) */ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + /* MMConf area for PCI0, begin and end */ + lens += acpigen_write_name_dword("MMCB", sysconf.mmconf_start); + lens += acpigen_write_name_dword("MMCE", sysconf.mmconf_end); + lens += k8acpi_write_HT(); //minus opcode acpigen_patch_len(lens - 1); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index eaf3a40..0e7df25 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -625,6 +625,9 @@ static void amdk8_set_resources(device_t dev) amdk8_set_resource(dev, mem_highest, nodeid); } + sysconf.mmconf_start = mem_lowest_start; + sysconf.mmconf_end = mem_highest_end; + compact_resources(dev); for(bus = dev->link_list; bus; bus = bus->next) {

1 0

Patch set updated for coreboot: 3fe47a1 amdk8: Increase limits for MMIO
by Nico Huber 09 Apr '13

09 Apr '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2662 -gerrit commit 3fe47a16f7e080596bfb936dce6bbb8ceafe5bd7 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Apr 9 15:29:42 2013 +0200 amdk8: Increase limits for MMIO The chipset requires configuration of the MMIO region on the HyperTransport layer, so requests are forwarded appropriately. Until now, we configured exactly the region used by our device allocator, which is a problem if the operating system requires more space for its own allocation (eg. for hot-plug devices). This change expands the HT-configured MMIO region to cover the whole space it uses itself (as it used to) plus the neighboring unused address space. ACPI still registers a way too large area, which can confuse the OS, since it assigns legal addresses which are then not forwarded to the device, but that's for a separate change. Tests were done on a siemens/sitemp_g1p1. Change-Id: Ib63c05484739d84198a9f10352be2055c6f14385 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/northbridge/amd/amdk8/northbridge.c | 64 +++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5c1d97a..eaf3a40 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -525,12 +525,48 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) IORESOURCE_ASSIGNED; } +/* + * Sets /start/ to the nearest resource end below /start/ + * and /end/ to the nearest resource base above /end/. + */ +static void amdk8_find_wider_pcimem_limits(resource_t *const start, + resource_t *const end) +{ + const uint32_t topmem = (uint32_t)bsp_topmem(); + const resource_t limit_4g = 0x100000000ULL; + + resource_t highest_below = topmem, lowest_above = limit_4g; + + struct device *dev; + struct resource *res; + + for (dev = all_devices; dev; dev = dev->next) { + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_MEM) || !res->size) + continue; + const resource_t res_end = resource_end(res); + if (highest_below < res_end && res_end <= *start) + highest_below = res_end; + if (*end <= res->base && res->base < lowest_above) + lowest_above = res->base; + } + } + *start = highest_below; + *end = lowest_above; +} + static void amdk8_set_resources(device_t dev) { unsigned nodeid; struct bus *bus; struct resource *res; + const uint32_t topmem = (uint32_t)bsp_topmem(); + const resource_t limit_4g = 0x100000000ULL; + + resource_t mem_lowest_start = limit_4g, mem_highest_end = topmem; + struct resource *mem_lowest = NULL, *mem_highest = NULL; + /* Find the nodeid */ nodeid = amdk8_nodeid(dev); @@ -559,6 +595,34 @@ static void amdk8_set_resources(device_t dev) res->index = index; amdk8_set_resource(dev, res, nodeid); + + if (IOINDEX_LINK(res->index) == 0 && + res->flags & IORESOURCE_MEM) { + if (topmem <= res->base && + res->base < mem_lowest_start) { + mem_lowest = res; + mem_lowest_start = res->base; + } + const resource_t res_end = res->base + res->size; + if (mem_highest_end < res_end && res_end <= limit_4g) { + mem_highest = res; + mem_highest_end = res_end; + } + } + } + + amdk8_find_wider_pcimem_limits(&mem_lowest_start, &mem_highest_end); + if (mem_lowest && mem_lowest_start < mem_lowest->base) { + mem_lowest->size += mem_lowest->base - mem_lowest_start; + mem_lowest->base = mem_lowest_start; + mem_lowest->flags &= ~IORESOURCE_STORED; + amdk8_set_resource(dev, mem_lowest, nodeid); + } + if (mem_highest && (mem_highest->base + mem_highest->size) + < mem_highest_end) { + mem_highest->size = mem_highest_end - mem_highest->base; + mem_highest->flags &= ~IORESOURCE_STORED; + amdk8_set_resource(dev, mem_highest, nodeid); } compact_resources(dev);

1 0

New patch to review for coreboot: 19b3818 FrontRunner/Toucan-AF: boards will be renamed to fit ADLINK scheme
by Jens Rottmann 09 Apr '13

09 Apr '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3046 -gerrit commit 19b381873cd84da097d1a7b90d505f2314bf3cdd Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Apr 9 09:57:27 2013 +0200 FrontRunner/Toucan-AF: boards will be renamed to fit ADLINK scheme Originally developed by LiPPERT and after the acquisition marketed as 'LiPPERT by ADLINK', the plan is now to streamline both boards into the ADLINK naming scheme. But AFAIK a few have already been sold and as of this writing the website still advertises the old names. And in any case the veteran LX products will continue to be sold by ADLINK under their original names. So create CONFIG_VENDOR_ADLINK, currently only telling users to look under LiPPERT (however any future boards will be added here). Further add an explanation to CONFIG_VENDOR_LIPPERT, and in the Mainboard model selection show both names. Change-Id: Iaafa88533ef4cce33243293c3d55754e7e93d003 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/Kconfig | 7 +++++-- src/mainboard/adlink/Kconfig | 10 ++++++++++ src/mainboard/lippert/Kconfig | 8 +++++--- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 66168ea..3ca21ff 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -8,8 +8,10 @@ config VENDOR_AAEON bool "Aaeon" config VENDOR_ABIT bool "Abit" +config VENDOR_ADLINK + bool "ADLINK" config VENDOR_ADVANSUS - bool "Advansus" + bool "Advansus" config VENDOR_ADVANTECH bool "Advantech" config VENDOR_AMD @@ -83,7 +85,7 @@ config VENDOR_LANNER config VENDOR_LENOVO bool "Lenovo" config VENDOR_LIPPERT - bool "Lippert" + bool "LiPPERT" config VENDOR_MITAC bool "Mitac" config VENDOR_MSI @@ -136,6 +138,7 @@ endchoice source "src/mainboard/a-trend/Kconfig" source "src/mainboard/aaeon/Kconfig" source "src/mainboard/abit/Kconfig" +source "src/mainboard/adlink/Kconfig" source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig new file mode 100644 index 0000000..f71d6a9 --- /dev/null +++ b/src/mainboard/adlink/Kconfig @@ -0,0 +1,10 @@ +if VENDOR_ADLINK + +comment "see under vendor LiPPERT" +# any further boards will then be ADLINK + +config MAINBOARD_VENDOR + string + default "ADLINK" + +endif # VENDOR_ADLINK diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 1765460..5d69aae 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -1,12 +1,14 @@ if VENDOR_LIPPERT +comment "was acquired by ADLINK" + choice prompt "Mainboard model" config BOARD_LIPPERT_FRONTRUNNER bool "Cool FrontRunner" config BOARD_LIPPERT_FRONTRUNNER_AF - bool "Cool FrontRunner-AF" + bool "FrontRunner-AF aka ADLINK CoreModule2-GF" config BOARD_LIPPERT_HURRICANE_LX bool "Hurricane-LX" config BOARD_LIPPERT_LITERUNNER_LX @@ -16,7 +18,7 @@ config BOARD_LIPPERT_ROADRUNNER_LX config BOARD_LIPPERT_SPACERUNNER_LX bool "Cool SpaceRunner-LX" config BOARD_LIPPERT_TOUCAN_AF - bool "Toucan-AF (+W83627DHG SIO)" + bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)" endchoice @@ -30,6 +32,6 @@ source "src/mainboard/lippert/toucan-af/Kconfig" config MAINBOARD_VENDOR string - default "Lippert" + default "LiPPERT" endif # VENDOR_LIPPERT

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Patch set updated for coreboot: dcc1b89 armv7: replace read/write macros with inlines
by David Hendricks 09 Apr '13

09 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3045 -gerrit commit dcc1b89abb9e4481352d0c1acd79c5f776ac93c7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Apr 8 20:01:18 2013 -0700 armv7: replace read/write macros with inlines This enables type checking for safety as to help prevent errors like http://review.coreboot.org/#/c/3038/ . Now compilation fails if the wrong type is passed into readb/readw/readl/writeb/writew/writel or other macros in io.h. Since many macros relied on __raw_*, which were basically the same (minus data memory barrier instructions), this patch also gets rid of __raw_*. There were parts of the code which ended up using these macros consecutively, for example: setbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); In such cases the safe versions of readl() and writel() should be used anyway. Note: This also fixes two dubious casts as to avoid breaking compilation. Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 197 +++++++++--------------------- src/cpu/samsung/exynos5-common/cpu_info.c | 2 +- src/cpu/samsung/exynos5250/clock.c | 6 +- 3 files changed, 64 insertions(+), 141 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index b99e014..c8567bd 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -1,6 +1,8 @@ /* - * linux/include/asm-arm/io.h + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. * + * Copyright (C) 2013 Google Inc. * Copyright (C) 1996-2000 Russell King * * This program is free software; you can redistribute it and/or modify @@ -8,6 +10,7 @@ * published by the Free Software Foundation. * * Modifications: + * 08-Apr-2013 G Replaced several macros with inlines for type safety. * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both * constant addresses and variable addresses. * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture @@ -24,102 +27,44 @@ #include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> -static inline void sync(void) +static inline unsigned char readb(const void *addr) { + unsigned char v = *(volatile unsigned char *)addr; + dmb(); + return v; } -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#if 0 -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) -{ - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - __arch_putb(*buf++, addr); -} - -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +static inline unsigned short readw(const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - __arch_putw(*buf++, addr); + unsigned short v = *(volatile unsigned short *)addr; + dmb(); + return v; } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +static inline unsigned int readl(const void *addr) { - uint32_t *buf = (uint32_t *)data; - while(longlen--) - __arch_putl(*buf++, addr); + unsigned int v = *(volatile unsigned int *)addr; + dmb(); + return v; } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +static inline void writeb(unsigned char val, const void *addr) { - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - *buf++ = __arch_getb(addr); + dmb(); + *(volatile unsigned char *)addr = val; } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +static inline void writew(unsigned short val, const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - *buf++ = __arch_getw(addr); + dmb(); + *(volatile unsigned short *)addr = val; } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) +static inline void writel(unsigned int val, const void *addr) { - uint32_t *buf = (uint32_t *)data; - while(longlen--) - *buf++ = __arch_getl(addr); + dmb(); + *(volatile unsigned int*)addr = val; } -#endif - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define __iormb() dmb() -#define __iowmb() dmb() - -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) - -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) /* * Clear and set bits in one shot. These macros can be used to clear and @@ -129,8 +74,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * in the 'set' parameter. */ -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) +#define out_arch(type,endian,a,v) write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(read##type(a)) #define out_le32(a,v) out_arch(l,le32,a,v) #define out_le16(a,v) out_arch(w,le16,a,v) @@ -144,8 +89,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) +#define out_8(a,v) writeb(v,a) +#define in_8(a) readb(a) #define clrbits(type, addr, clear) \ out_##type((addr), in_##type(addr) & ~(clear)) @@ -177,13 +122,6 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) /* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* * IO port access primitives * ------------------------- * @@ -202,27 +140,26 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * address to a memory address. * * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. + * by introducing sequence points into the in*() definitions. * * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. */ #ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) +#define outb(v,p) writeb(v,__io(p)) +#define outw(v,p) writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) writel(cpu_to_le32(v),__io(p)) -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) +#define inb(p) ({ unsigned int __v = readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(readl(__io(p))); __v; }) -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) +#define outsb(p,d,l) writesb(__io(p),d,l) +#define outsw(p,d,l) writesw(__io(p),d,l) +#define outsl(p,d,l) writesl(__io(p),d,l) -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#define insb(p,d,l) readsb(__io(p),d,l) +#define insw(p,d,l) readsw(__io(p),d,l) +#define insl(p,d,l) readsl(__io(p),d,l) #endif #define outb_p(val,port) outb((val),(port)) @@ -285,13 +222,13 @@ extern void __readwrite_bug(const char *fn); */ #ifdef __mem_pci -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) +#define readb(c) ({ unsigned int __v = readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(readl(__mem_pci(c))); __v; }) -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) +#define writeb(v,c) writeb(v,__mem_pci(c)) +#define writew(v,c) writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) writel(cpu_to_le32(v),__mem_pci(c)) #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) @@ -316,49 +253,35 @@ check_signature(unsigned long io_addr, const unsigned char *signature, out: return retval; } - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - #endif /* __mem_pci */ /* FIXME(dhendrix): added to make uart8250_mem code happy. Note: lL */ static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) { - return readb(addr); + return readb((unsigned char *)addr); } static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) { - return readw(addr); + return readw((unsigned short *)addr); } static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) { - return readl(addr); + return readl((unsigned int *)addr); } -static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) +static inline __attribute__((always_inline)) void write8(unsigned long *addr, uint8_t value) { writeb(value, addr); } -static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) +static inline __attribute__((always_inline)) void write16(unsigned long *addr, uint16_t value) { writew(value, addr); } -static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) +static inline __attribute__((always_inline)) void write32(unsigned long *addr, uint32_t value) { writel(value, addr); } @@ -370,12 +293,12 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui */ #ifdef __mem_isa -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_readb(addr) readb(__mem_isa(addr)) +#define isa_readw(addr) readw(__mem_isa(addr)) +#define isa_readl(addr) readl(__mem_isa(addr)) +#define isa_writeb(val,addr) writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) writel(val,__mem_isa(addr)) #define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) #define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) #define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) diff --git a/src/cpu/samsung/exynos5-common/cpu_info.c b/src/cpu/samsung/exynos5-common/cpu_info.c index dec3c77..6b75473 100644 --- a/src/cpu/samsung/exynos5-common/cpu_info.c +++ b/src/cpu/samsung/exynos5-common/cpu_info.c @@ -65,7 +65,7 @@ int s5p_get_cpu_rev(void) void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS_PRO_ID); + s5p_cpu_id = readl((void *)EXYNOS_PRO_ID); s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); /* diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 6b79272..3622e28 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -379,7 +379,7 @@ void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = samsung_get_base_clock(); - unsigned int addr; + unsigned int *addr; unsigned int val; /* @@ -389,9 +389,9 @@ void set_mmc_clk(int dev_index, unsigned int div) * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] */ if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; + addr = &clk->div_fsys1; } else { - addr = (unsigned int)&clk->div_fsys2; + addr = &clk->div_fsys2; dev_index -= 2; }

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New patch to review for coreboot: 20ffca9 armv7: replace read/write macros with inlines
by David Hendricks 09 Apr '13

09 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3045 -gerrit commit 20ffca9c24a5d9a4e4908607a4a7088e1afe2c53 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Apr 8 20:01:18 2013 -0700 armv7: replace read/write macros with inlines This enables type checking for safety as to help prevent errors like http://review.coreboot.org/#/c/3038/ . Now compilation fails if the wrong type is passed into readb/readw/readl/writeb/writew/writel or other macros in io.h. Since many macros relied on __raw_*, which were basically the same (minus data memory barrier instructions), this patch also gets rid of __raw_*. There were parts of the code which ended up using these macros consecutively, for example: setbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); In such cases the safe versions of readl() and writel() should be used anyway. Note: This also fixes two dubious casts as to avoid breaking compilation. Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 194 +++++++++--------------------- src/cpu/samsung/exynos5-common/cpu_info.c | 2 +- src/cpu/samsung/exynos5250/clock.c | 6 +- 3 files changed, 63 insertions(+), 139 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index b99e014..e6e235f 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -1,6 +1,8 @@ /* - * linux/include/asm-arm/io.h + * Originally imported from linux/include/asm-arm/io.h. This file has changed + * substantially since then. * + * Copyright (C) 2013 Google Inc. * Copyright (C) 1996-2000 Russell King * * This program is free software; you can redistribute it and/or modify @@ -8,6 +10,7 @@ * published by the Free Software Foundation. * * Modifications: + * 08-Apr-2013 G Replaced several macros with inlines for type safety. * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both * constant addresses and variable addresses. * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture @@ -24,102 +27,44 @@ #include <arch/cache.h> /* for dmb() */ #include <arch/byteorder.h> -static inline void sync(void) +static inline unsigned char readb(const void *addr) { + unsigned char v = *(volatile unsigned char *)addr; + dmb(); + return v; } -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#if 0 -extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) -{ - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - __arch_putb(*buf++, addr); -} - -extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +static inline unsigned short readw(const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - __arch_putw(*buf++, addr); + unsigned short v = *(volatile unsigned short *)addr; + dmb(); + return v; } -extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +static inline unsigned int readl(const void *addr) { - uint32_t *buf = (uint32_t *)data; - while(longlen--) - __arch_putl(*buf++, addr); + unsigned int v = *(volatile unsigned int *)addr; + dmb(); + return v; } -extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +static inline void writeb(unsigned char val, const void *addr) { - uint8_t *buf = (uint8_t *)data; - while(bytelen--) - *buf++ = __arch_getb(addr); + dmb(); + *(volatile unsigned char *)addr = val; } -extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +static inline void writew(unsigned short val, const void *addr) { - uint16_t *buf = (uint16_t *)data; - while(wordlen--) - *buf++ = __arch_getw(addr); + dmb(); + *(volatile unsigned short *)addr = val; } -extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) +static inline void writel(unsigned int val, const void *addr) { - uint32_t *buf = (uint32_t *)data; - while(longlen--) - *buf++ = __arch_getl(addr); + dmb(); + *(volatile unsigned int*)addr = val; } -#endif - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define __iormb() dmb() -#define __iowmb() dmb() - -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) - -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) /* * Clear and set bits in one shot. These macros can be used to clear and @@ -129,8 +74,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * in the 'set' parameter. */ -#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) -#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) +#define out_arch(type,endian,a,v) write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(read##type(a)) #define out_le32(a,v) out_arch(l,le32,a,v) #define out_le16(a,v) out_arch(w,le16,a,v) @@ -144,8 +89,8 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) -#define out_8(a,v) __raw_writeb(v,a) -#define in_8(a) __raw_readb(a) +#define out_8(a,v) writeb(v,a) +#define in_8(a) readb(a) #define clrbits(type, addr, clear) \ out_##type((addr), in_##type(addr) & ~(clear)) @@ -177,13 +122,6 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) /* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* * IO port access primitives * ------------------------- * @@ -208,21 +146,21 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. */ #ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) +#define outb(v,p) writeb(v,__io(p)) +#define outw(v,p) writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) writel(cpu_to_le32(v),__io(p)) -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) +#define inb(p) ({ unsigned int __v = readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(readl(__io(p))); __v; }) -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) +#define outsb(p,d,l) writesb(__io(p),d,l) +#define outsw(p,d,l) writesw(__io(p),d,l) +#define outsl(p,d,l) writesl(__io(p),d,l) -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#define insb(p,d,l) readsb(__io(p),d,l) +#define insw(p,d,l) readsw(__io(p),d,l) +#define insl(p,d,l) readsl(__io(p),d,l) #endif #define outb_p(val,port) outb((val),(port)) @@ -285,13 +223,13 @@ extern void __readwrite_bug(const char *fn); */ #ifdef __mem_pci -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) +#define readb(c) ({ unsigned int __v = readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(readl(__mem_pci(c))); __v; }) -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) +#define writeb(v,c) writeb(v,__mem_pci(c)) +#define writew(v,c) writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) writel(cpu_to_le32(v),__mem_pci(c)) #define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) #define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) @@ -316,49 +254,35 @@ check_signature(unsigned long io_addr, const unsigned char *signature, out: return retval; } - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - #endif /* __mem_pci */ /* FIXME(dhendrix): added to make uart8250_mem code happy. Note: lL */ static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr) { - return readb(addr); + return readb((unsigned char *)addr); } static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr) { - return readw(addr); + return readw((unsigned short *)addr); } static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr) { - return readl(addr); + return readl((unsigned int *)addr); } -static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value) +static inline __attribute__((always_inline)) void write8(unsigned long *addr, uint8_t value) { writeb(value, addr); } -static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value) +static inline __attribute__((always_inline)) void write16(unsigned long *addr, uint16_t value) { writew(value, addr); } -static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value) +static inline __attribute__((always_inline)) void write32(unsigned long *addr, uint32_t value) { writel(value, addr); } @@ -370,12 +294,12 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui */ #ifdef __mem_isa -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_readb(addr) readb(__mem_isa(addr)) +#define isa_readw(addr) readw(__mem_isa(addr)) +#define isa_readl(addr) readl(__mem_isa(addr)) +#define isa_writeb(val,addr) writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) writel(val,__mem_isa(addr)) #define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) #define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) #define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) diff --git a/src/cpu/samsung/exynos5-common/cpu_info.c b/src/cpu/samsung/exynos5-common/cpu_info.c index dec3c77..6b75473 100644 --- a/src/cpu/samsung/exynos5-common/cpu_info.c +++ b/src/cpu/samsung/exynos5-common/cpu_info.c @@ -65,7 +65,7 @@ int s5p_get_cpu_rev(void) void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS_PRO_ID); + s5p_cpu_id = readl((void *)EXYNOS_PRO_ID); s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); /* diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 6b79272..3622e28 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -379,7 +379,7 @@ void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = samsung_get_base_clock(); - unsigned int addr; + unsigned int *addr; unsigned int val; /* @@ -389,9 +389,9 @@ void set_mmc_clk(int dev_index, unsigned int div) * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] */ if (dev_index < 2) { - addr = (unsigned int)&clk->div_fsys1; + addr = &clk->div_fsys1; } else { - addr = (unsigned int)&clk->div_fsys2; + addr = &clk->div_fsys2; dev_index -= 2; }

1 0

New patch to review for coreboot: acfa209 exynos5: Re-factor I2C code
by David Hendricks 09 Apr '13

09 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3044 -gerrit commit acfa2093c0920d6d06155d9da5ced7c769e97d3a Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 5 16:11:12 2013 -0700 exynos5: Re-factor I2C code This re-factors the Exynos5 I2C code to be simpler and use the new API, and updates users accordingly. - i2c_read() and i2c_write() functions updated to take bus number as an argument. - Get rid of the EEPROM_ADDR_OVERFLOW stuff in i2c_read() and i2c_write(). If a chip needs special handling we should take care of it elsewhere, not in every low-level i2c driver. - All the confusing bus config functions eliminated. No more i2c_set_early_config() or i2c_set_bus() or i2c_get_bus(). All this is handled automatically when the caller does a transaction and specifies the desired bus number. - i2c_probe() eliminated. We're not a command-line utility. - Let the compiler place static variables automatically. We don't need any of this fancy manual data placement. - Remove dead code while we're at it. This stuff was ported early on and much of it was left commented out in case we needed it. Some also includes nested macros which caused gcc to complain. - Clean up #includes (no more common.h, woohoo!), replace debug() with printk(). Change-Id: I8e1f974ea4c6c7db9f33b77bbc4fb16008ed0d2a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 2 +- src/cpu/samsung/exynos5-common/i2c.c | 354 +++++++---------------------- src/cpu/samsung/exynos5-common/i2c.h | 8 +- src/drivers/maxim/max77686/max77686.c | 53 ++--- src/drivers/maxim/max77686/max77686.h | 13 +- src/include/device/i2c-old.h | 281 ----------------------- src/mainboard/google/snow/bootblock.c | 2 - src/mainboard/google/snow/romstage.c | 26 ++- 8 files changed, 126 insertions(+), 613 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index d3710a3..30d0767 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -33,7 +33,7 @@ #include <cpu/samsung/exynos5250/sysreg.h> #include <drivers/maxim/max77686/max77686.h> -#include "device/i2c-old.h" +#include "device/i2c.h" #include "cpu/samsung/exynos5-common/i2c.h" #include "cpu/samsung/exynos5250/dsim.h" #include "cpu/samsung/exynos5250/fimd.h" diff --git a/src/cpu/samsung/exynos5-common/i2c.c b/src/cpu/samsung/exynos5-common/i2c.c index c531530..30fabe1 100644 --- a/src/cpu/samsung/exynos5-common/i2c.c +++ b/src/cpu/samsung/exynos5-common/i2c.c @@ -26,19 +26,14 @@ * The different address mapping is handled by the s3c24xx.h files below. */ -#include <common.h> +#include <delay.h> #include <arch/io.h> -#include "clk.h" +#include <console/console.h> +#include <device/i2c.h> #include "cpu/samsung/exynos5-common/clk.h" -#include "cpu/samsung/exynos5250/cpu.h" -#include "gpio.h" -#include "cpu/samsung/exynos5250/gpio.h" +#include "cpu/samsung/exynos5-common/i2c.h" #include "cpu/samsung/exynos5250/pinmux.h" -//#include <fdtdec.h> -#include "device/i2c-old.h" -#include "i2c.h" - #define I2C_WRITE 0 #define I2C_READ 1 @@ -65,54 +60,49 @@ enum { I2C_STOP_TIMEOUT_US = 200, /* waiting for stop events */ }; -/* We should not rely on any particular ordering of these IDs */ -#if 0 -#ifndef CONFIG_OF_CONTROL -static enum periph_id periph_for_dev[EXYNOS_I2C_MAX_CONTROLLERS] = { - PERIPH_ID_I2C0, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, +static struct s3c24x0_i2c_bus i2c_buses[] = { + /* FIXME: exynos5250-specific? */ + { + .bus_num = 0, + .regs = (struct s3c24x0_i2c *)0x12c60000, + .periph_id = PERIPH_ID_I2C0, + }, + { + .bus_num = 1, + .regs = (struct s3c24x0_i2c *)0x12c70000, + .periph_id = PERIPH_ID_I2C1, + }, + { + .bus_num = 2, + .regs = (struct s3c24x0_i2c *)0x12c80000, + .periph_id = PERIPH_ID_I2C2, + }, + { + .bus_num = 3, + .regs = (struct s3c24x0_i2c *)0x12c90000, + .periph_id = PERIPH_ID_I2C3, + }, + { + .bus_num = 4, + .regs = (struct s3c24x0_i2c *)0x12ca0000, + .periph_id = PERIPH_ID_I2C4, + }, + { + .bus_num = 5, + .regs = (struct s3c24x0_i2c *)0x12cb0000, + .periph_id = PERIPH_ID_I2C5, + }, + { + .bus_num = 6, + .regs = (struct s3c24x0_i2c *)0x12cc0000, + .periph_id = PERIPH_ID_I2C6, + }, + { + .bus_num = 7, + .regs = (struct s3c24x0_i2c *)0x12cd0000, + .periph_id = PERIPH_ID_I2C7, + }, }; -#endif -#endif - -static unsigned int g_current_bus __attribute__((section(".data"))); -static struct s3c24x0_i2c *g_early_i2c_config __attribute__((section(".data"))); - -static struct s3c24x0_i2c_bus i2c_bus[EXYNOS_I2C_MAX_CONTROLLERS] - __attribute__((section(".data"))); -static int i2c_busses __attribute__((section(".data"))); - -void i2c_set_early_reg(unsigned int base) -{ - g_early_i2c_config = (struct s3c24x0_i2c *)base; -} - -static struct s3c24x0_i2c_bus *get_bus(int bus_idx) -{ - /* If an early i2c config exists we just use that */ - if (g_early_i2c_config) { - /* FIXME: value not retained from i2c_set_early_reg()? (but then, how - * did if (!i2c) check pass earlier on? Corrupt value? */ - i2c_bus[0].regs = g_early_i2c_config; - return &i2c_bus[0]; - } - - if (bus_idx < i2c_busses) - return &i2c_bus[bus_idx]; - debug("Undefined bus: %d\n", bus_idx); - return NULL; -} - -static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void) -{ - return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE); -} static int WaitForXfer(struct s3c24x0_i2c *i2c) { @@ -121,7 +111,7 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c) i = I2C_XFER_TIMEOUT_MS * 20; while (!(readl(&i2c->iiccon) & I2CCON_IRPND)) { if (i == 0) { - debug("%s: i2c xfer timeout\n", __func__); + printk(BIOS_ERR, "%s: i2c xfer timeout\n", __func__); return I2C_NOK_TOUT; } udelay(50); @@ -142,15 +132,14 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c) x = readl(&i2c->iiccon); writel(x & ~I2CCON_IRPND, &i2c->iiccon); - /* FIXME(dhendrix): cannot use nested macro (compilation failure) */ -// writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } -static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) +static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) { unsigned long freq, pres = 16, div; + unsigned long val; - freq = clock_get_periph_rate(PERIPH_ID_I2C0); + freq = clock_get_periph_rate(bus->periph_id); /* calculate prescaler and divisor values */ if ((freq / pres / (16 + 1)) > speed) /* set prescaler to 512 */ @@ -162,136 +151,25 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) div++; /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); + val = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); + writel(val, &bus->regs->iiccon); - /* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->iicstat); - writel(slaveadd, &i2c->iicadd); + /* init to SLAVE RECEIVE mode and clear I2CADDn */ + writel(0, &bus->regs->iicstat); + writel(slaveadd, &bus->regs->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); -} - -/* TODO: determine if this is necessary to init board using FDT-provided info */ -#if 0 -void board_i2c_init(const void *blob) -{ - /* - * Turn off the early i2c configuration and init the i2c properly, - * this is done here to enable the use of i2c configs from FDT. - */ - i2c_set_early_reg(0); - -#ifdef CONFIG_OF_CONTROL - int node_list[EXYNOS_I2C_MAX_CONTROLLERS]; - int i, count; - - count = fdtdec_find_aliases_for_id(blob, "i2c", - COMPAT_SAMSUNG_S3C2440_I2C, node_list, - EXYNOS_I2C_MAX_CONTROLLERS); - - for (i = 0; i < count; i++) { - struct s3c24x0_i2c_bus *bus; - int node = node_list[i]; - - if (node < 0) - continue; - bus = &i2c_bus[i2c_busses]; - bus->regs = (struct s3c24x0_i2c *) - fdtdec_get_addr(blob, node, "reg"); - bus->id = (enum periph_id) - fdtdec_get_int(blob, node, "samsung,periph-id", -1); - bus->node = node; - bus->bus_num = i2c_busses++; - } -#else - int i; - - for (i = 0; i < EXYNOS_I2C_MAX_CONTROLLERS; i++) { - unsigned intptr_t reg_addr = samsung_get_base_i2c() + - EXYNOS_I2C_SPACING * i; - - i2c_bus[i].regs = (struct s3c24x0_i2c_bus *)reg_addr; - i2c_bus[i].id = periph_for_dev[i]; - } - i2c_busses = EXYNOS_I2C_MAX_CONTROLLERS; -#endif + writel(I2C_MODE_MT | I2C_TXRX_ENA, &bus->regs->iicstat); } -#endif /* * MULTI BUS I2C support */ -static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) -{ - exynos_pinmux_config(i2c->id, 0); - i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -} - -#ifdef CONFIG_I2C_MULTI_BUS -int i2c_set_bus_num(unsigned int bus) +static void i2c_bus_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) { - struct s3c24x0_i2c_bus *i2c; - - i2c = get_bus(bus); - if (!i2c) - return -1; - g_current_bus = bus; - i2c_bus_init(i2c, g_current_bus); - - return 0; + exynos_pinmux_config(bus->periph_id, 0); + i2c_ch_init(bus, speed, slaveadd); } -unsigned int i2c_get_bus_num(void) -{ - return g_current_bus; -} -#endif - -#ifdef CONFIG_OF_CONTROL -int i2c_get_bus_num_fdt(const void *blob, int node) -{ - enum fdt_compat_id compat; - fdt_addr_t reg; - int i; - - compat = fdtdec_lookup(blob, node); - if (compat != COMPAT_SAMSUNG_S3C2440_I2C) { - debug("%s: Not a supported I2C node\n", __func__); - return -1; - } - - reg = fdtdec_get_addr(blob, node, "reg"); - for (i = 0; i < i2c_busses; i++) - if (reg == (fdt_addr_t)(unsigned intptr_t)i2c_bus[i].regs) - return i; - - debug("%s: Can't find any matched I2C bus\n", __func__); - return -1; -} - -int i2c_reset_port_fdt(const void *blob, int node) -{ - struct s3c24x0_i2c_bus *i2c; - - int bus; - - bus = i2c_get_bus_num_fdt(blob, node); - if (bus < 0) { - printf("could not get bus for node %d\n", node); - return -1; - } - i2c = get_bus(bus); - if (!i2c) { - printf("get_bus() failed for node node %d\n", node); - return -1; - } - - i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - return 0; -} -#endif - /* * Verify the whether I2C ACK was received or not * @@ -321,21 +199,13 @@ static int i2c_send_verify(struct s3c24x0_i2c *i2c, unsigned char buf[], return result; } -void i2c_init(int speed, int slaveadd) +void i2c_init(unsigned bus_num, int speed, int slaveadd) { struct s3c24x0_i2c_bus *i2c; - struct exynos5_gpio_part1 *gpio; int i; - uint32_t x; - - /* By default i2c channel 0 is the current bus */ - g_current_bus = 0; - i2c = get_bus(g_current_bus); - if (!i2c) - return; - - i2c_bus_init(i2c, g_current_bus); + i2c = &i2c_buses[bus_num]; + i2c_bus_init(i2c, speed, slaveadd); /* wait for some time to give previous transfer a chance to finish */ i = I2C_INIT_TIMEOUT_MS * 20; @@ -344,13 +214,7 @@ void i2c_init(int speed, int slaveadd) i--; } - gpio = exynos_get_base_gpio1(); - /* FIXME(dhendrix): cannot use nested macro (compilation failure) */ -// writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con); - x = readl(&gpio->b3.con); - writel((x & ~0x00FF) | 0x0022, &gpio->b3.con); - - i2c_ch_init(i2c->regs, speed, slaveadd); + i2c_ch_init(i2c, speed, slaveadd); } /* @@ -397,7 +261,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, if (data == 0 || data_len == 0) { /* Don't support data transfer of no length or to address 0 */ - debug("i2c_transfer: bad call\n"); + printk(BIOS_ERR, "i2c_transfer: bad call\n"); return I2C_NOK; } @@ -409,12 +273,10 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, } if (readl(&i2c->iicstat) & I2CSTAT_BSY) { - debug("%s: bus busy\n", __func__); + printk(BIOS_ERR, "%s: bus busy\n", __func__); return I2C_NOK_TOUT; } - /* FIXME(dhendrix): cannot use nested macro (compilation failure) */ - //writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); x = readl(&i2c->iiccon); writel(x | I2CCON_ACKGEN, &i2c->iiccon); @@ -465,12 +327,6 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) { - /* FIXME(dhendrix): nested macro */ -#if 0 - writel(readl(&i2c->iiccon) & - ~I2CCON_ACKGEN, - &i2c->iiccon); -#endif x = readl(&i2c->iiccon) & ~I2CCON_ACKGEN; writel(x, &i2c->iiccon); } @@ -488,7 +344,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, } default: - debug("i2c_transfer: bad call\n"); + printk(BIOS_ERR, "i2c_transfer: bad call\n"); result = stop_bit_result = I2C_NOK; break; } @@ -501,35 +357,15 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, return (result == I2C_OK) ? stop_bit_result : result; } -int i2c_probe(unsigned char chip) -{ - struct s3c24x0_i2c_bus *i2c; - unsigned char buf[1]; - int ret; - - i2c = get_bus(g_current_bus); - if (!i2c) - return -1; - buf[0] = 0; - - /* - * What is needed is to send the chip address and verify that the - * address was <ACK>ed (i.e. there was a chip at that address which - * drove the data line low). - */ - ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, 0, 0, buf, 1); - - return ret != I2C_OK; -} - -int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len) +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, unsigned char *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; int ret; if (alen > 4) { - debug("I2C read: addr len %d not supported\n", alen); + printk(BIOS_ERR, "I2C read: addr len %d not supported\n", alen); return 1; } @@ -540,42 +376,26 @@ int i2c_read(unsigned char chip, unsigned int addr, int alen, unsigned char *buf xaddr[3] = addr & 0xFF; } -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - i2c = get_bus(g_current_bus); - if (!i2c) - return -1; + i2c = &i2c_buses[bus]; ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], - alen, buffer, len); + alen, buf, len); if (ret) { - debug("I2c read: failed %d\n", ret); + printk(BIOS_ERR, "I2c read: failed %d\n", ret); return 1; } return 0; } -int i2c_write(unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len) +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, unsigned char *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; int ret; if (alen > 4) { - debug("I2C write: addr len %d not supported\n", alen); + printk(BIOS_ERR, "I2C write: addr len %d not supported\n", + alen); return 1; } @@ -585,28 +405,10 @@ int i2c_write(unsigned char chip, unsigned int addr, int alen, unsigned char *bu xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; } -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - i2c = get_bus(g_current_bus); - if (!i2c) - return -1; + i2c = &i2c_buses[bus]; ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], - alen, buffer, len); + alen, buf, len); return ret != 0; } diff --git a/src/cpu/samsung/exynos5-common/i2c.h b/src/cpu/samsung/exynos5-common/i2c.h index eb68af7..0bfee34 100644 --- a/src/cpu/samsung/exynos5-common/i2c.h +++ b/src/cpu/samsung/exynos5-common/i2c.h @@ -35,9 +35,11 @@ struct s3c24x0_i2c { }; struct s3c24x0_i2c_bus { - int node; /* device tree node */ - int bus_num; /* i2c bus number */ + int bus_num; struct s3c24x0_i2c *regs; - enum periph_id id; + enum periph_id periph_id; }; + +void i2c_init(unsigned bus, int speed, int slaveadd); + #endif /* _S3C24X0_I2C_H */ diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index 2cac4df..5760d42 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -23,8 +23,7 @@ #include <arch/io.h> #include <common.h> -//#include <smbus.h> -#include <device/i2c-old.h> +#include <device/i2c.h> #include "max77686.h" @@ -91,10 +90,10 @@ struct max77686_para max77686_param[] = {/*{vol_addr, vol_bitpos, * @param val value to be written * */ -static inline int max77686_i2c_write(unsigned char chip_addr, +static inline int max77686_i2c_write(unsigned int bus, unsigned char chip_addr, unsigned int reg, unsigned char val) { - return i2c_write(chip_addr, reg, 1, &val, 1); + return i2c_write(bus, chip_addr, reg, 1, &val, 1); } /* @@ -105,10 +104,10 @@ static inline int max77686_i2c_write(unsigned char chip_addr, * @param val value to be written * */ -static inline int max77686_i2c_read(unsigned char chip_addr, +static inline int max77686_i2c_read(unsigned int bus, unsigned char chip_addr, unsigned int reg, unsigned char *val) { - return i2c_read(chip_addr, reg, 1, val, 1); + return i2c_read(bus, chip_addr, reg, 1, val, 1); } /* @@ -121,7 +120,7 @@ static inline int max77686_i2c_read(unsigned char chip_addr, needed to set the buck/ldo enable bit OFF * @return Return 0 if ok, else -1 */ -static int max77686_enablereg(enum max77686_regnum reg, int enable) +static int max77686_enablereg(unsigned int bus, enum max77686_regnum reg, int enable) { struct max77686_para *pmic; unsigned char read_data; @@ -129,7 +128,7 @@ static int max77686_enablereg(enum max77686_regnum reg, int enable) pmic = &max77686_param[reg]; - ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->reg_enaddr, + ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, pmic->reg_enaddr, &read_data); if (ret != 0) { debug("max77686 i2c read failed.\n"); @@ -145,7 +144,7 @@ static int max77686_enablereg(enum max77686_regnum reg, int enable) pmic->reg_enbiton << pmic->reg_enbitpos); } - ret = max77686_i2c_write(MAX77686_I2C_ADDR, + ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, pmic->reg_enaddr, read_data); if (ret != 0) { debug("max77686 i2c write failed.\n"); @@ -155,8 +154,8 @@ static int max77686_enablereg(enum max77686_regnum reg, int enable) return 0; } -static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units) +int max77686_volsetting(unsigned int bus, enum max77686_regnum reg, + unsigned int volt, int enable, int volt_units) { struct max77686_para *pmic; unsigned char read_data; @@ -170,7 +169,7 @@ static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, return -1; } - ret = max77686_i2c_read(MAX77686_I2C_ADDR, pmic->vol_addr, &read_data); + ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, pmic->vol_addr, &read_data); if (ret != 0) { debug("max77686 i2c read failed.\n"); return -1; @@ -190,13 +189,13 @@ static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, clrsetbits_8(&read_data, pmic->vol_bitmask << pmic->vol_bitpos, vol_level << pmic->vol_bitpos); - ret = max77686_i2c_write(MAX77686_I2C_ADDR, pmic->vol_addr, read_data); + ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, pmic->vol_addr, read_data); if (ret != 0) { debug("max77686 i2c write failed.\n"); return -1; } - ret = max77686_enablereg(reg, enable); + ret = max77686_enablereg(bus, reg, enable); if (ret != 0) { debug("Failed to enable buck/ldo.\n"); return -1; @@ -204,31 +203,17 @@ static int max77686_do_volsetting(enum max77686_regnum reg, unsigned int volt, return 0; } -int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units) +int max77686_enable_32khz_cp(unsigned int bus) { - int old_bus = i2c_get_bus_num(); - int ret; - - i2c_set_bus_num(0); - ret = max77686_do_volsetting(reg, volt, enable, volt_units); - i2c_set_bus_num(old_bus); - return ret; -} - -int max77686_enable_32khz_cp(void) -{ - i2c_set_bus_num(0); - return max77686_enablereg(PMIC_EN32KHZ_CP, REG_ENABLE); + return max77686_enablereg(bus, PMIC_EN32KHZ_CP, REG_ENABLE); } -int max77686_disable_backup_batt(void) +int max77686_disable_backup_batt(unsigned int bus) { unsigned char val; int ret; - i2c_set_bus_num(0); - ret = max77686_i2c_read(MAX77686_I2C_ADDR, REG_BBAT, &val); + ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, REG_BBAT, &val); if (ret) { debug("max77686 i2c read failed\n"); return ret; @@ -241,7 +226,7 @@ int max77686_disable_backup_batt(void) /* First disable charging */ val &= ~BBAT_BBCHOSTEN_MASK; - ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); + ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, REG_BBAT, val); if (ret) { debug("max77686 i2c write failed\n"); return -1; @@ -249,7 +234,7 @@ int max77686_disable_backup_batt(void) /* Finally select 3.5V to minimize power consumption */ val |= BBAT_BBCVS_MASK; - ret = max77686_i2c_write(MAX77686_I2C_ADDR, REG_BBAT, val); + ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, REG_BBAT, val); if (ret) { debug("max77686 i2c write failed\n"); return -1; diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index ee53e27..cebd2d9 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -105,13 +105,16 @@ enum { /** * This function enables the 32KHz coprocessor clock. * + * @param bus i2c bus + * * Return 0 if ok, else -1 */ -int max77686_enable_32khz_cp(void); +int max77686_enable_32khz_cp(unsigned int bus); /** * Set the required voltage level of pmic * + * @param bus i2c bus * @param reg register number of buck/ldo to be set * @param volt voltage level to be set * @param enable enable or disable bit @@ -120,14 +123,16 @@ int max77686_enable_32khz_cp(void); * * @return Return 0 if ok, else -1 */ -int max77686_volsetting(enum max77686_regnum reg, unsigned int volt, - int enable, int volt_units); +int max77686_volsetting(unsigned int bus, enum max77686_regnum reg, + unsigned int volt, int enable, int volt_units); /** * Disable charging of the RTC backup battery * + * @param bus i2c bus + * * @return Return 0 if ok, else -1 */ -int max77686_disable_backup_batt(void); +int max77686_disable_backup_batt(unsigned int bus); #endif /* __MAX77686_PMIC_H_ */ diff --git a/src/include/device/i2c-old.h b/src/include/device/i2c-old.h deleted file mode 100644 index bd6dd0c..0000000 --- a/src/include/device/i2c-old.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * The original I2C interface was - * (C) 2000 by Paolo Scaffardi (arsenio(a)tin.it) - * AIRVENT SAM s.p.a - RIMINI(ITALY) - * but has been changed substantially. - */ - -#ifndef _I2C_H_ -#define _I2C_H_ - -/* - * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING - * - * The implementation MUST NOT use static or global variables if the - * I2C routines are used to read SDRAM configuration information - * because this is done before the memories are initialized. Limited - * use of stack-based variables are OK (the initial stack size is - * limited). - * - * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING - */ - -/* - * Configuration items. - */ -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - -#ifdef CONFIG_I2C_MULTI_BUS -#define MAX_I2C_BUS 2 -#define I2C_MULTI_BUS 1 -#else -#define MAX_I2C_BUS 1 -#define I2C_MULTI_BUS 0 -#endif - -#if !defined(CONFIG_SYS_MAX_I2C_BUS) -#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS -#endif - -/* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CONFIG_SYS_RTC_BUS_NUM) -#define CONFIG_SYS_RTC_BUS_NUM 0 -#endif -#if !defined(CONFIG_SYS_DTT_BUS_NUM) -#define CONFIG_SYS_DTT_BUS_NUM 0 -#endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif - -#ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - -# elif (defined(CONFIG_AT91RM9200) || \ - defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) -# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; -# else -# define I2C_SOFT_DECLARATIONS -# endif -#endif - -#ifdef CONFIG_8xx -/* Set default value for the I2C bus speed on 8xx. In the - * future, we'll define these in all 8xx board config files. - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif -#endif - -/* - * Many boards/controllers/drivers don't support an I2C slave interface so - * provide a default slave address for them for use in common code. A real - * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does - * support a slave interface. - */ -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr); -void i2c_init_board(void); -#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT -void i2c_board_late_init(void); -#endif - -#if defined(CONFIG_I2C_MUX) - -typedef struct _mux { - unsigned char chip; - unsigned char channel; - char *name; - struct _mux *next; -} I2C_MUX; - -typedef struct _mux_device { - int busid; - I2C_MUX *mux; /* List of muxes, to reach the device */ - struct _mux_device *next; -} I2C_MUX_DEVICE; - -I2C_MUX_DEVICE *i2c_mux_search_device(int id); -I2C_MUX_DEVICE *i2c_mux_ident_muxstring (unsigned char *buf); -int i2x_mux_select_mux(int bus); -int i2c_mux_ident_muxstring_f (unsigned char *buf); -#endif - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(unsigned char chip); - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_read(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); -int i2c_write(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); - -/* - * Utility routines to read/write registers. - */ -static inline u8 i2c_reg_read(u8 addr, u8 reg) -{ - u8 buf; - -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - -#ifdef DEBUG - printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); -#endif - - i2c_read(addr, reg, 1, &buf, 1); - - return buf; -} - -static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) -{ -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - -#ifdef DEBUG - printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", - __func__, addr, reg, val); -#endif - - i2c_write(addr, reg, 1, &val, 1); -} - -/* - * Functions for setting the current I2C bus and its speed - */ - -/* - * i2c_set_bus_num: - * - * Change the active I2C bus. Subsequent read/write calls will - * go to this one. - * - * bus - bus index, zero based - * - * Returns: 0 on success, not 0 on failure - * - */ -int i2c_set_bus_num(unsigned int bus); - -/* - * i2c_get_bus_num: - * - * Returns index of currently active I2C bus. Zero-based. - */ - -unsigned int i2c_get_bus_num(void); - -/* - * i2c_set_bus_speed: - * - * Change the speed of the active I2C bus - * - * speed - bus speed in Hz - * - * Returns: 0 on success, not 0 on failure - * - */ -int i2c_set_bus_speed(unsigned int); - -/* - * i2c_get_bus_speed: - * - * Returns speed of currently active I2C bus in Hz - */ - -unsigned int i2c_get_bus_speed(void); - -/* NOTE: These two functions MUST be always_inline to avoid code growth! */ -static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); -static inline unsigned int I2C_GET_BUS(void) -{ - return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; -} - -static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); -static inline void I2C_SET_BUS(unsigned int bus) -{ - if (I2C_MULTI_BUS) - i2c_set_bus_num(bus); -} - -/* - * Set an early register base for a given i2c peripheral. - * This is used to access a single i2c bus early on in the boot sequence. - * - * @param base: The base address of the i2c peripheral's register map - */ -void i2c_set_early_reg(unsigned int base); - -/** - * Find the I2C bus number by given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * @return the number of I2C bus (zero based), or -1 on error - */ -int i2c_get_bus_num_fdt(const void *blob, int node); - -/** - * Reset the I2C bus represented by the given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * @return 0 if port was reset, -1 if not found - */ -int i2c_reset_port_fdt(const void *blob, int node); - -#endif /* _I2C_H_ */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 17a3267..2df0e4e 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -25,8 +25,6 @@ #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> -#define I2C0_BASE 0x12c60000 - void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 94ca222..d34c379 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -25,6 +25,7 @@ #include <arch/cache.h> #include <arch/gpio.h> +#include <cpu/samsung/exynos5-common/i2c.h> #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/gpio.h> @@ -36,10 +37,11 @@ #include <arch/stages.h> #include <drivers/maxim/max77686/max77686.h> -#include <device/i2c-old.h> +#include <device/i2c.h> #include "mainboard.h" +#define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) #if 0 @@ -69,23 +71,23 @@ static int setup_pmic(void) * * Disable Coin BATT Charging */ - error = max77686_disable_backup_batt(); + error = max77686_disable_backup_batt(PMIC_BUS); - error |= max77686_volsetting(PMIC_BUCK2, CONFIG_VDD_ARM_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, CONFIG_VDD_ARM_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUCK3, CONFIG_VDD_INT_UV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, CONFIG_VDD_INT_UV, REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUCK1, CONFIG_VDD_MIF_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, CONFIG_VDD_MIF_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUCK4, CONFIG_VDD_G3D_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, CONFIG_VDD_G3D_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO2, CONFIG_VDD_LDO2_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, CONFIG_VDD_LDO2_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO3, CONFIG_VDD_LDO3_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, CONFIG_VDD_LDO3_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO5, CONFIG_VDD_LDO5_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, CONFIG_VDD_LDO5_MV, REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_LDO10, CONFIG_VDD_LDO10_MV, + error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, CONFIG_VDD_LDO10_MV, REG_ENABLE, MAX77686_MV); if (error) @@ -133,10 +135,10 @@ void main(void) console_init(); - i2c_set_early_reg(0x12c60000); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00); if (power_init()) power_shutdown(); + printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__); if (setup_pmic()) power_shutdown();

1 0

New patch to review for coreboot: d1abcaf replace device/i2c.h with simpler version
by David Hendricks 09 Apr '13

09 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3043 -gerrit commit d1abcaf4cf804120ae8b54256165c8df1515e83f Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 5 13:42:39 2013 -0700 replace device/i2c.h with simpler version The existing header was imported along with the Exynos code and left mostly unchanged. This is the first patch in a series intended to replace the imported u-boot I2C API with a much simpler and cleaner interface: - We only need to expose i2c_read() and i2c_write() in our public API. Everything else is board/chip-dependent and should remain hidden away. - i2c_read and i2c_write functions will take bus number as an arg and we'll eliminate i2c_get_bus and i2c_set_bus. Those are prone to error and end up cluttering the code since the user needs to save the old bus number, set the new one, do the read/write, and restore the old value (3 added steps to do a simple transaction). - Stop setting default values for board-specific things like SPD and RTC bus numbers (as if we always have an SPD or RTC on I2C). - Death to all the trivial inline wrappers. And in case there was any doubt, we really don't care about the MPC8xx. Though if we did then we would not pollute the public API with its idiosyncrasies. Change-Id: I4410a3c82ed5a6b2e80e3d8c0163464a9ca7c3b0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 2 +- src/cpu/samsung/exynos5-common/i2c.c | 2 +- src/drivers/maxim/max77686/max77686.c | 2 +- src/include/device/i2c-old.h | 281 +++++++++++++++++++++++++++++ src/include/device/i2c.h | 280 ++-------------------------- src/mainboard/google/snow/romstage.c | 2 +- 6 files changed, 299 insertions(+), 270 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 30d0767..d3710a3 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -33,7 +33,7 @@ #include <cpu/samsung/exynos5250/sysreg.h> #include <drivers/maxim/max77686/max77686.h> -#include "device/i2c.h" +#include "device/i2c-old.h" #include "cpu/samsung/exynos5-common/i2c.h" #include "cpu/samsung/exynos5250/dsim.h" #include "cpu/samsung/exynos5250/fimd.h" diff --git a/src/cpu/samsung/exynos5-common/i2c.c b/src/cpu/samsung/exynos5-common/i2c.c index 7384b50..c531530 100644 --- a/src/cpu/samsung/exynos5-common/i2c.c +++ b/src/cpu/samsung/exynos5-common/i2c.c @@ -36,7 +36,7 @@ #include "cpu/samsung/exynos5250/pinmux.h" //#include <fdtdec.h> -#include "device/i2c.h" +#include "device/i2c-old.h" #include "i2c.h" #define I2C_WRITE 0 diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index 16fa7f5..2cac4df 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <common.h> //#include <smbus.h> -#include <device/i2c.h> +#include <device/i2c-old.h> #include "max77686.h" diff --git a/src/include/device/i2c-old.h b/src/include/device/i2c-old.h new file mode 100644 index 0000000..bd6dd0c --- /dev/null +++ b/src/include/device/i2c-old.h @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio(a)tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +/* + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + * + * The implementation MUST NOT use static or global variables if the + * I2C routines are used to read SDRAM configuration information + * because this is done before the memories are initialized. Limited + * use of stack-based variables are OK (the initial stack size is + * limited). + * + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + */ + +/* + * Configuration items. + */ +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +#ifdef CONFIG_I2C_MULTI_BUS +#define MAX_I2C_BUS 2 +#define I2C_MULTI_BUS 1 +#else +#define MAX_I2C_BUS 1 +#define I2C_MULTI_BUS 0 +#endif + +#if !defined(CONFIG_SYS_MAX_I2C_BUS) +#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS +#endif + +/* define the I2C bus number for RTC and DTT if not already done */ +#if !defined(CONFIG_SYS_RTC_BUS_NUM) +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_DTT_BUS_NUM) +#define CONFIG_SYS_DTT_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_SPD_BUS_NUM) +#define CONFIG_SYS_SPD_BUS_NUM 0 +#endif + +#ifndef I2C_SOFT_DECLARATIONS +# if defined(CONFIG_MPC8260) +# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); +# elif defined(CONFIG_8xx) +# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + +# elif (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; +# else +# define I2C_SOFT_DECLARATIONS +# endif +#endif + +#ifdef CONFIG_8xx +/* Set default value for the I2C bus speed on 8xx. In the + * future, we'll define these in all 8xx board config files. + */ +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 +#endif +#endif + +/* + * Many boards/controllers/drivers don't support an I2C slave interface so + * provide a default slave address for them for use in common code. A real + * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does + * support a slave interface. + */ +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xfe +#endif + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr); +void i2c_init_board(void); +#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT +void i2c_board_late_init(void); +#endif + +#if defined(CONFIG_I2C_MUX) + +typedef struct _mux { + unsigned char chip; + unsigned char channel; + char *name; + struct _mux *next; +} I2C_MUX; + +typedef struct _mux_device { + int busid; + I2C_MUX *mux; /* List of muxes, to reach the device */ + struct _mux_device *next; +} I2C_MUX_DEVICE; + +I2C_MUX_DEVICE *i2c_mux_search_device(int id); +I2C_MUX_DEVICE *i2c_mux_ident_muxstring (unsigned char *buf); +int i2x_mux_select_mux(int bus); +int i2c_mux_ident_muxstring_f (unsigned char *buf); +#endif + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(unsigned char chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +int i2c_write(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +static inline u8 i2c_reg_read(u8 addr, u8 reg) +{ + u8 buf; + +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); +#endif + + i2c_read(addr, reg, 1, &buf, 1); + + return buf; +} + +static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) +{ +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", + __func__, addr, reg, val); +#endif + + i2c_write(addr, reg, 1, &val, 1); +} + +/* + * Functions for setting the current I2C bus and its speed + */ + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus); + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void); + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int); + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void); + +/* NOTE: These two functions MUST be always_inline to avoid code growth! */ +static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); +static inline unsigned int I2C_GET_BUS(void) +{ + return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; +} + +static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); +static inline void I2C_SET_BUS(unsigned int bus) +{ + if (I2C_MULTI_BUS) + i2c_set_bus_num(bus); +} + +/* + * Set an early register base for a given i2c peripheral. + * This is used to access a single i2c bus early on in the boot sequence. + * + * @param base: The base address of the i2c peripheral's register map + */ +void i2c_set_early_reg(unsigned int base); + +/** + * Find the I2C bus number by given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return the number of I2C bus (zero based), or -1 on error + */ +int i2c_get_bus_num_fdt(const void *blob, int node); + +/** + * Reset the I2C bus represented by the given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return 0 if port was reset, -1 if not found + */ +int i2c_reset_port_fdt(const void *blob, int node); + +#endif /* _I2C_H_ */ diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index bd6dd0c..d880a7b 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -1,14 +1,11 @@ /* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * This file is part of the coreboot project. * - * See file CREDITS for list of people who contributed to this - * project. + * Copyright (C) 2013 Google, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,265 +14,16 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * The original I2C interface was - * (C) 2000 by Paolo Scaffardi (arsenio(a)tin.it) - * AIRVENT SAM s.p.a - RIMINI(ITALY) - * but has been changed substantially. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ -#ifndef _I2C_H_ -#define _I2C_H_ - -/* - * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING - * - * The implementation MUST NOT use static or global variables if the - * I2C routines are used to read SDRAM configuration information - * because this is done before the memories are initialized. Limited - * use of stack-based variables are OK (the initial stack size is - * limited). - * - * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING - */ - -/* - * Configuration items. - */ -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - -#ifdef CONFIG_I2C_MULTI_BUS -#define MAX_I2C_BUS 2 -#define I2C_MULTI_BUS 1 -#else -#define MAX_I2C_BUS 1 -#define I2C_MULTI_BUS 0 -#endif - -#if !defined(CONFIG_SYS_MAX_I2C_BUS) -#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS -#endif - -/* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CONFIG_SYS_RTC_BUS_NUM) -#define CONFIG_SYS_RTC_BUS_NUM 0 -#endif -#if !defined(CONFIG_SYS_DTT_BUS_NUM) -#define CONFIG_SYS_DTT_BUS_NUM 0 -#endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif - -#ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - -# elif (defined(CONFIG_AT91RM9200) || \ - defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) -# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; -# else -# define I2C_SOFT_DECLARATIONS -# endif -#endif - -#ifdef CONFIG_8xx -/* Set default value for the I2C bus speed on 8xx. In the - * future, we'll define these in all 8xx board config files. - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif -#endif - -/* - * Many boards/controllers/drivers don't support an I2C slave interface so - * provide a default slave address for them for use in common code. A real - * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does - * support a slave interface. - */ -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr); -void i2c_init_board(void); -#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT -void i2c_board_late_init(void); -#endif - -#if defined(CONFIG_I2C_MUX) - -typedef struct _mux { - unsigned char chip; - unsigned char channel; - char *name; - struct _mux *next; -} I2C_MUX; - -typedef struct _mux_device { - int busid; - I2C_MUX *mux; /* List of muxes, to reach the device */ - struct _mux_device *next; -} I2C_MUX_DEVICE; - -I2C_MUX_DEVICE *i2c_mux_search_device(int id); -I2C_MUX_DEVICE *i2c_mux_ident_muxstring (unsigned char *buf); -int i2x_mux_select_mux(int bus); -int i2c_mux_ident_muxstring_f (unsigned char *buf); -#endif - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(unsigned char chip); - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_read(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); -int i2c_write(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); - -/* - * Utility routines to read/write registers. - */ -static inline u8 i2c_reg_read(u8 addr, u8 reg) -{ - u8 buf; - -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - -#ifdef DEBUG - printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); -#endif - - i2c_read(addr, reg, 1, &buf, 1); - - return buf; -} - -static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) -{ -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif +#ifndef _DEVICE_I2C_H_ +#define _DEVICE_I2C_H_ -#ifdef DEBUG - printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", - __func__, addr, reg, val); -#endif - - i2c_write(addr, reg, 1, &val, 1); -} - -/* - * Functions for setting the current I2C bus and its speed - */ - -/* - * i2c_set_bus_num: - * - * Change the active I2C bus. Subsequent read/write calls will - * go to this one. - * - * bus - bus index, zero based - * - * Returns: 0 on success, not 0 on failure - * - */ -int i2c_set_bus_num(unsigned int bus); - -/* - * i2c_get_bus_num: - * - * Returns index of currently active I2C bus. Zero-based. - */ - -unsigned int i2c_get_bus_num(void); - -/* - * i2c_set_bus_speed: - * - * Change the speed of the active I2C bus - * - * speed - bus speed in Hz - * - * Returns: 0 on success, not 0 on failure - * - */ -int i2c_set_bus_speed(unsigned int); - -/* - * i2c_get_bus_speed: - * - * Returns speed of currently active I2C bus in Hz - */ - -unsigned int i2c_get_bus_speed(void); - -/* NOTE: These two functions MUST be always_inline to avoid code growth! */ -static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); -static inline unsigned int I2C_GET_BUS(void) -{ - return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; -} - -static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); -static inline void I2C_SET_BUS(unsigned int bus) -{ - if (I2C_MULTI_BUS) - i2c_set_bus_num(bus); -} - -/* - * Set an early register base for a given i2c peripheral. - * This is used to access a single i2c bus early on in the boot sequence. - * - * @param base: The base address of the i2c peripheral's register map - */ -void i2c_set_early_reg(unsigned int base); - -/** - * Find the I2C bus number by given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * @return the number of I2C bus (zero based), or -1 on error - */ -int i2c_get_bus_num_fdt(const void *blob, int node); - -/** - * Reset the I2C bus represented by the given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * @return 0 if port was reset, -1 if not found - */ -int i2c_reset_port_fdt(const void *blob, int node); +/* note: chip is the 7-bit I2C address */ +int i2c_read(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, unsigned char *buf, unsigned len); +int i2c_write(unsigned bus, unsigned chip, unsigned addr, + unsigned alen, unsigned char *buf, unsigned len); -#endif /* _I2C_H_ */ +#endif /* _DEVICE_I2C_H_ */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ca7ba9c..94ca222 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,7 +36,7 @@ #include <arch/stages.h> #include <drivers/maxim/max77686/max77686.h> -#include <device/i2c.h> +#include <device/i2c-old.h> #include "mainboard.h"

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coreboot-gerrit April 2013