Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: [WIP] mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
[WIP] mb/fujitsu/d3410-b1: Add new mainboard
Seems like something on the board isn't happy about coreboot. This code booted once, but the board usually fails to boot...
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/gpio.c A src/mainboard/fujitsu/d3410-b1/gpio.h A src/mainboard/fujitsu/d3410-b1/ramstage.c A src/mainboard/fujitsu/d3410-b1/romstage.c 16 files changed, 571 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/1
diff --git a/src/mainboard/fujitsu/Kconfig b/src/mainboard/fujitsu/Kconfig new file mode 100644 index 0000000..fb6d31e --- /dev/null +++ b/src/mainboard/fujitsu/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_FUJITSU + +choice + prompt "Mainboard model" + +source "src/mainboard/fujitsu/*/Kconfig.name" + +endchoice + +source "src/mainboard/fujitsu/*/Kconfig" + +config MAINBOARD_VENDOR + default "Fujitsu" + +endif # VENDOR_FUJITSU diff --git a/src/mainboard/fujitsu/Kconfig.name b/src/mainboard/fujitsu/Kconfig.name new file mode 100644 index 0000000..60d1dd9 --- /dev/null +++ b/src/mainboard/fujitsu/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_FUJITSU + bool "Fujitsu" diff --git a/src/mainboard/fujitsu/d3410-b1/Kconfig b/src/mainboard/fujitsu/d3410-b1/Kconfig new file mode 100644 index 0000000..029c24f --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_FUJITSU_D3410_B1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EXCLUDE_NATIVE_SD_INTERFACE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_LIBGFXINIT + #select NO_FADT_8042 + select SOC_INTEL_KABYLAKE + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6791D + select SKYLAKE_SOC_PCH_H + +config MAINBOARD_DIR + string + default "fujitsu/d3410-b1" + +config MAINBOARD_PART_NUMBER + string + default "D3410-B1" + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/fujitsu/d3410-b1/Kconfig.name b/src/mainboard/fujitsu/d3410-b1/Kconfig.name new file mode 100644 index 0000000..3de8ce8 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_FUJITSU_D3410_B1 + bool "D3410-B1" diff --git a/src/mainboard/fujitsu/d3410-b1/Makefile.inc b/src/mainboard/fujitsu/d3410-b1/Makefile.inc new file mode 100644 index 0000000..c75390d --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/fujitsu/d3410-b1/acpi/ec.asl b/src/mainboard/fujitsu/d3410-b1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/acpi/ec.asl diff --git a/src/mainboard/fujitsu/d3410-b1/acpi/superio.asl b/src/mainboard/fujitsu/d3410-b1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/acpi/superio.asl diff --git a/src/mainboard/fujitsu/d3410-b1/board_info.txt b/src/mainboard/fujitsu/d3410-b1/board_info.txt new file mode 100644 index 0000000..b1c4635 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Board name: COMe-bSL6 +Category: misc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/fujitsu/d3410-b1/bootblock.c b/src/mainboard/fujitsu/d3410-b1/bootblock.c new file mode 100644 index 0000000..3224688 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/bootblock.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <bootblock_common.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x31); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x61); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x71); + pnp_write_config(GLOBAL_DEV, 0x24, 0x20); + pnp_write_config(GLOBAL_DEV, 0x27, 0x01); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x00); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/fujitsu/d3410-b1/devicetree.cb b/src/mainboard/fujitsu/d3410-b1/devicetree.cb new file mode 100644 index 0000000..fbf40d2 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/devicetree.cb @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + register "PmConfigPciClockRun" = "1" + register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" + + # Vendor set Psys Pmax to 30W + register "power_limits_config" = "{ + .psys_pmax = 30, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussian Mixture Model + device pci 14.0 on # USB xHCI + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT Redirection + device pci 16.4 off end # MEI #3 + device pci 17.0 on # SATA + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + # SataPortsDevSlp not supported + end + device pci 19.0 off end # UART #2 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (COMe 0) + register "PcieRpEnable[8]" = "1" + end + device pci 1d.1 on # PCI Express Port 10 (COMe 1) + register "PcieRpEnable[9]" = "1" + end + device pci 1d.2 on # PCI Express Port 11 (COMe 2) + register "PcieRpEnable[10]" = "1" + end + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + #register "gen1_dec" = "0x000c0291" + + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/fujitsu/d3410-b1/dsdt.asl b/src/mainboard/fujitsu/d3410-b1/dsdt.asl new file mode 100644 index 0000000..b5e5a68 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + + Device (_SB.PCI0) { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads b/src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads new file mode 100644 index 0000000..0cf02cd --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/fujitsu/d3410-b1/gpio.c b/src/mainboard/fujitsu/d3410-b1/gpio.c new file mode 100644 index 0000000..8498fc5 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/gpio.c @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include "gpio.h" + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_NC(GPP_B2, UP_20K), + _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + //PAD_CFG_GPIO_BIDIRECT(GPP_C11, 0, NONE, PLTRST, OFF, ACPI), + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + //PAD_CFG_GPIO_BIDIRECT(GPP_D5, 0, NONE, PLTRST, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_E ------- */ + _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_NC(GPP_F14, NONE), + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_G ------- */ + _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, DN_20K, PWROK, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_G17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G19, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_G23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Group GPP_H ------- */ + _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, DN_20K, PWROK, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_H2, DN_20K, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + //PAD_CFG_GPIO_BIDIRECT(GPP_H11, 0, NONE, PWROK, LEVEL, ACPI), + _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), + _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_H16, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | (1 << 1) | 1, 0), + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H21, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_NC(GPD7, NONE), + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + PAD_CFG_GPO(GPD10, 0, DEEP), + _PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_BUF(TX_RX_DISABLE) | 1, 0), + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), +}; +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/fujitsu/d3410-b1/gpio.h b/src/mainboard/fujitsu/d3410-b1/gpio.h new file mode 100644 index 0000000..c3ab23c --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +void mainboard_configure_gpios(void); diff --git a/src/mainboard/fujitsu/d3410-b1/ramstage.c b/src/mainboard/fujitsu/d3410-b1/ramstage.c new file mode 100644 index 0000000..8751e53c --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include "gpio.h" + +static void init_mainboard(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/fujitsu/d3410-b1/romstage.c b/src/mainboard/fujitsu/d3410-b1/romstage.c new file mode 100644 index 0000000..8998c17 --- /dev/null +++ b/src/mainboard/fujitsu/d3410-b1/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <spd_bin.h> +#include <soc/romstage.h> +#include <fsp/soc_binding.h> + +/* Rcomp resistors are located on the CPU package */ +static const u16 rcomp_resistors[3] = { 121, 75, 100 }; + +/* Rcomp targets for DDR4 1DPC */ +static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); + + memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + get_spd_smbus(&blk); + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + + memcpy(memory_params->RcompResistor, rcomp_resistors, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, rcomp_targets, + sizeof(memory_params->RcompTarget)); + + memory_params->DqPinsInterleaved = true; +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: [WIP] mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 1:
(39 comments)
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 28: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 53: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 62: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 67: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 68: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 70: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 71: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 75: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 76: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 107: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 108: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 111: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 128: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 129: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 130: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 131: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 149: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 150: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 186: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 216: _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 217: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 230: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 237: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 238: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 239: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 240: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/1/src/mainboard/fujitsu/d3410... PS1, Line 18: FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#2).
Change subject: [WIP] mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
[WIP] mb/fujitsu/d3410-b1: Add new mainboard
Board does not respond to power button presses after booting once.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/gpio.c A src/mainboard/fujitsu/d3410-b1/romstage.c 14 files changed, 508 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: [WIP] mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 2:
(53 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/c7d1ecfe_bc632017 PS2, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e841d1a8_7d864028 PS2, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5f87e854_3545f515 PS2, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/105d838e_a4fcca9d PS2, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5063e3cd_f048fcef PS2, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3ac325fc_29972758 PS2, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ddc0437a_4f791c8c PS2, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2aaa2671_b0ccfa59 PS2, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7902f700_3ec74887 PS2, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8e1a31cb_8a2ed6cd PS2, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/dc022c95_63d16eb1 PS2, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1dcd5eb2_29933494 PS2, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/77024b46_88e41746 PS2, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b418491d_0c3851e1 PS2, Line 26: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5efec02a_672b300c PS2, Line 29: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/96998e46_f01e2c39 PS2, Line 33: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d3894a5b_c144ea5e PS2, Line 34: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3a95dbec_732f4d7e PS2, Line 35: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f45b505e_805bc219 PS2, Line 37: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7051b4df_c21d43b4 PS2, Line 38: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b80d366d_8089cb2c PS2, Line 39: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2bd15b3c_5e38e7e9 PS2, Line 44: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fcb1f958_d157b2d5 PS2, Line 45: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2995db48_862832b8 PS2, Line 46: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fb060a61_8ecd911b PS2, Line 47: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f458a6d7_00d088f4 PS2, Line 48: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fcb21a82_594f88d6 PS2, Line 49: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/689f9543_51a1bc9c PS2, Line 50: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/de7347c7_d6f3a3d0 PS2, Line 51: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8dd8155a_f2821579 PS2, Line 52: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/6bdff048_e9949377 PS2, Line 57: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/6034f0c6_046bf159 PS2, Line 58: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ee351b84_3788ef66 PS2, Line 59: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/01ba2fb7_019f8eb6 PS2, Line 62: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3487374c_c268dc9e PS2, Line 63: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3d594dd4_056b47a6 PS2, Line 64: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c196e1c2_a41e3850 PS2, Line 65: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/453620a2_cbfea579 PS2, Line 66: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/aa581925_f95bf3e1 PS2, Line 69: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fee5a6ff_ce997766 PS2, Line 70: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/915bfdaf_93c512d7 PS2, Line 79: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f3488956_327365c8 PS2, Line 82: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b07b71a1_72f872f3 PS2, Line 105: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/dfca4805_064dc7f8 PS2, Line 106: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/323ad390_5fb3c64c PS2, Line 107: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1b66eadc_ef892a91 PS2, Line 108: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e5d47fc5_633ef071 PS2, Line 109: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4e34876d_16f5ad6f PS2, Line 110: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f2499b13_807d9a06 PS2, Line 111: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1c90bb6b_bcda4f8f PS2, Line 112: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e9c6003c_c400b08d PS2, Line 113: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f5a4c758_9e26fe8e PS2, Line 114: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/f6dca70e_f0352e70 PS2, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#3).
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
mb/fujitsu/d3410-b1: Add new mainboard
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.
Working: - At least one DIMM slot (Micron CT4G4DFS8213.8FA11) - Super I/O serial port and fan tachometer inputs - At least two USB 2.0 ports (below the Ethernet port) - Realtek RTL8111E GbE NIC - Integrated graphics on DVI with libgfxinit - At least one SATA port - Both PCIe x1 slots - Flashing internally with flashrom - S3 suspend/resume - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
TO TEST: - Audio - The other DIMM slot (Hynix HMA851U6AFR6N-UH) - The other USB ports - PEG - VBT - PS/2 - DisplayPork - TPM (probably CRB) - GPIO config needs a clean-up
Not working: - Power LED is not happy and repeatedly blinks twice (BIOS recovery). - VGA on D3463 expansion card: Uses a NXP PTN3355 DP2VGA chip, most likely uses DDI E, and libgfxinit does not support DDI E yet.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/gpio.c A src/mainboard/fujitsu/d3410-b1/romstage.c 14 files changed, 526 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 3:
(53 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/f3f8f2af_33725d45 PS3, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2a36d69f_4b5af004 PS3, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/41c40eb1_3eaba2fc PS3, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/6e74b655_05189ea6 PS3, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8d59946d_c8c32003 PS3, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4d5ed83d_087f4e0a PS3, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ebf008ce_bda6fbe1 PS3, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/bd0e2586_82f8e826 PS3, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/459321c9_94842f0a PS3, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e1533bf6_9a4b7c10 PS3, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c0b41509_dc5f95a1 PS3, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/57d4ee7e_59747aae PS3, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4e221e6f_28d90f75 PS3, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ef7d3960_b4cf510e PS3, Line 26: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1b142c97_9431a070 PS3, Line 29: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f24b9919_d2f4353e PS3, Line 33: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ca76813c_b702b9f6 PS3, Line 34: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4e2413e1_acdb060a PS3, Line 35: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/04e735d4_162b7f9c PS3, Line 37: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/6d1d0981_9cecff24 PS3, Line 38: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/572400a9_afe626af PS3, Line 39: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3fff4c1d_9c3b6019 PS3, Line 44: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/24f8a4a7_080660eb PS3, Line 45: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4f88c13d_81f11102 PS3, Line 46: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/17da92e3_9a3463e6 PS3, Line 47: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1658a149_e9595d9e PS3, Line 48: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8c6c9b2b_c74eb835 PS3, Line 49: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9f9c0c3a_586acfe1 PS3, Line 50: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/398ec401_1e8dbfe6 PS3, Line 51: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4332098f_8e802560 PS3, Line 52: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/92d570d9_49968dad PS3, Line 57: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ee15f856_a96a160d PS3, Line 58: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/776500d6_5a551a66 PS3, Line 59: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/358093ee_911488c0 PS3, Line 62: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b1f03508_2c2ed6ea PS3, Line 63: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/501ee935_d212cd10 PS3, Line 64: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b014481a_365df3a1 PS3, Line 65: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a0101ed3_8341605d PS3, Line 66: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/bafa4672_eff42031 PS3, Line 69: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e8b6783c_e7cfaa5e PS3, Line 70: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8d54e3aa_80114bc4 PS3, Line 79: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/225eafdf_702c8b0a PS3, Line 82: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/0f9a8d50_9dbc14cc PS3, Line 105: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f5aeb04a_af693b61 PS3, Line 106: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ab8c2d05_57f0a7a9 PS3, Line 107: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/77953ff7_426e9a08 PS3, Line 108: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c903600a_e5267e1f PS3, Line 109: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3b72b217_d1d81c0f PS3, Line 110: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7cbf2b83_d1731be8 PS3, Line 111: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8929466c_e29a716f PS3, Line 112: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3e8d2916_fdf4683e PS3, Line 113: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b810119c_5d7cac8a PS3, Line 114: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/0b69a2bf_badf5ee6 PS3, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 4:
(53 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/dc36bda6_c94f44ae PS4, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/28c6267a_d6927372 PS4, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/145b9e43_bb5362ff PS4, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fc5865f3_bb2fc61b PS4, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/bb233958_36112428 PS4, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4546a5b7_9dc60787 PS4, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8bf2090a_62e29a6a PS4, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/22644558_4c64b236 PS4, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b9a3046b_5561b7e8 PS4, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ebd571fe_ba11f9c7 PS4, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/92fc565c_4f1b1b20 PS4, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/aadbb596_e58f981f PS4, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f38e1506_84aec9f5 PS4, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/47d5fed7_8f32d9fa PS4, Line 26: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b6043bdd_1cdc67d6 PS4, Line 29: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e08d1696_8e69dd95 PS4, Line 33: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2c3375ce_d6e3080c PS4, Line 34: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/cf2e2c13_6ec64f67 PS4, Line 35: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d448511d_2b3efb70 PS4, Line 37: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/aec32521_e06f3ae4 PS4, Line 38: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/08f6963a_782df3f5 PS4, Line 39: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/36bf9a0b_c7f383b8 PS4, Line 44: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b2b68f9f_df846394 PS4, Line 45: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/329e4a5a_2391841d PS4, Line 46: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/15eb8ef9_fd15d82d PS4, Line 47: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/40cb2b30_41f015c7 PS4, Line 48: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/cef56cbd_3e70d3df PS4, Line 49: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d04e09dc_90345dd7 PS4, Line 50: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c8d8a948_fd51990c PS4, Line 51: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/01acca99_e02fc673 PS4, Line 52: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/61158f25_1b5a2781 PS4, Line 57: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/36603052_cd140aac PS4, Line 58: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3470a5b7_f5c2764c PS4, Line 59: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ad6dd972_4669b7aa PS4, Line 62: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/03237f68_be31af54 PS4, Line 63: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b2fcd8ab_e3330afa PS4, Line 64: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e54e80d9_9e974edd PS4, Line 65: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/18784edf_49582448 PS4, Line 66: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c963c2f3_20591033 PS4, Line 69: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/db0ed3ea_3f2be92a PS4, Line 70: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1bd62a51_e1b8db4f PS4, Line 79: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1e3d0c85_4ed34e69 PS4, Line 82: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b7994be3_8d583a10 PS4, Line 105: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d4128b5e_33addeca PS4, Line 106: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8879ca73_3d69a6ed PS4, Line 107: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d32ccb4c_793ed3fb PS4, Line 108: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b043ba09_4a9e52c2 PS4, Line 109: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/04cbe0e9_f438f124 PS4, Line 110: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/89347e17_3025aa1c PS4, Line 111: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/071db88e_361ea3c3 PS4, Line 112: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/636a98d8_c9be4fa8 PS4, Line 113: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/558337ed_de44ea9e PS4, Line 114: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/2483018e_f8572220 PS4, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 5:
(53 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/9a768c0e_a32a491f PS5, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/711baa43_fac3bc20 PS5, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c90381ec_e0cfb392 PS5, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fd22007b_966b11ab PS5, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/275f3250_bcd4d337 PS5, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/38d60dd7_ff630400 PS5, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f7649f50_e14b1c9c PS5, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5ef98c1d_c7fedb8a PS5, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c2f35137_25df83ea PS5, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/cffb1131_a3661034 PS5, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8462bffd_2c780a34 PS5, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/16cda2b7_5c1582ef PS5, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ad33a82f_a33518a6 PS5, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/87e4a411_0166d298 PS5, Line 26: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5c5ec385_1125b3e7 PS5, Line 29: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/6085d863_a0dd6849 PS5, Line 33: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/39122824_414070cc PS5, Line 34: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7ff46d14_a7771bd1 PS5, Line 35: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/74be83fc_d3dd11d3 PS5, Line 37: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/dc0ca343_834c1322 PS5, Line 38: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/24fd8629_b2eebce1 PS5, Line 39: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/19316376_f48367cf PS5, Line 44: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/62b05ba5_efde19e3 PS5, Line 45: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/cacaee54_691d0851 PS5, Line 46: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/dba4064d_c370ea8e PS5, Line 47: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7a990e05_74a2dde6 PS5, Line 48: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/80389fe9_df9de9db PS5, Line 49: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/be5d2093_6210d451 PS5, Line 50: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/889020e8_2658daed PS5, Line 51: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fca760e4_770acd0d PS5, Line 52: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b133190f_4bca1d52 PS5, Line 57: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3f54724e_0efa2c2e PS5, Line 58: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/405e6e63_6c698f03 PS5, Line 59: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/60649bf8_66f7bc1a PS5, Line 62: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2e90fb6d_e8908e8b PS5, Line 63: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8a7b1ad3_ee991d13 PS5, Line 64: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7edef6be_84495d86 PS5, Line 65: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1618a5ee_5d5e87cb PS5, Line 66: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e02a64d4_95b6e93f PS5, Line 69: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3870854e_daec3dbe PS5, Line 70: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f2711994_c56ac1b6 PS5, Line 79: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1ebc8b53_f3d101b7 PS5, Line 82: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5cc074ef_9103cfa7 PS5, Line 105: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9d1c4076_39ebdc6a PS5, Line 106: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/92102fb4_bf2eaf24 PS5, Line 107: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/35001f34_fd08e8a6 PS5, Line 108: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5f6ba04c_b726eb30 PS5, Line 109: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/315ef919_7d170957 PS5, Line 110: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/98520b66_611fe7f3 PS5, Line 111: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fc4d09a9_2a6ccbb6 PS5, Line 112: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4cac5f0f_e66085f3 PS5, Line 113: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e31ab441_b63477b6 PS5, Line 114: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/c44c19be_9b72c8ad PS5, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 5:
(4 comments)
File src/mainboard/fujitsu/d3410-b1/Kconfig:
https://review.coreboot.org/c/coreboot/+/48383/comment/d0980ff2_941ca577 PS5, Line 34: config USE_LEGACY_8254_TIMER what for?
File src/mainboard/fujitsu/d3410-b1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48383/comment/4f527f02_e06a282f PS5, Line 77: register "SataTestMode" = "1 this is not something that should be merged
https://review.coreboot.org/c/coreboot/+/48383/comment/4a7cee1e_2d85babc PS5, Line 126: irq 0x70 = 1 : irq 0x72 = 12 why mixing hex with decimal?
https://review.coreboot.org/c/coreboot/+/48383/comment/fda2f084_a93e4b87 PS5, Line 163: io 0x62 = 0 : irq 0x70 = 0 : why mixing hex with decimal?
Attention is currently required from: Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 5:
(4 comments)
File src/mainboard/fujitsu/d3410-b1/Kconfig:
https://review.coreboot.org/c/coreboot/+/48383/comment/d124fc69_0c21de54 PS5, Line 34: config USE_LEGACY_8254_TIMER
what for?
I recall having issues without it, I'll re-check
File src/mainboard/fujitsu/d3410-b1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48383/comment/f5234b40_4d07001a PS5, Line 77: register "SataTestMode" = "1
this is not something that should be merged
Fine, I'll make it a Kconfig option instead.
https://review.coreboot.org/c/coreboot/+/48383/comment/ffdf2efe_8ce8f296 PS5, Line 126: irq 0x70 = 1 : irq 0x72 = 12
why mixing hex with decimal?
IRQ numbers are usually written in decimal, whereas addresses and register offsets are most often hex.
https://review.coreboot.org/c/coreboot/+/48383/comment/33cb3000_888b288e PS5, Line 163: io 0x62 = 0 : irq 0x70 = 0 :
why mixing hex with decimal?
In this case, it's to emphasize that these are disabled.
Attention is currently required from: Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/Kconfig:
https://review.coreboot.org/c/coreboot/+/48383/comment/2bb80630_a86b686b PS5, Line 34: config USE_LEGACY_8254_TIMER
I recall having issues without it, I'll re-check
SeaBIOS hangs without it, but it should be enabled by default in that case.
Attention is currently required from: Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#6).
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
mb/fujitsu/d3410-b1: Add new mainboard
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.
Working: - Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH) - Super I/O serial port and fan tachometer inputs - All USB 2.0 ports and rear USB 3.0 ports - Realtek RTL8111E GbE NIC - Integrated graphics on DP and DVI with libgfxinit - At least one SATA port - PCIe x16 and both PCIe x1 slots - Flashing internally with flashrom - S3 suspend/resume - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
TO TEST: - Audio - Front USB 3.0 ports - VBT - PS/2 - TPM (probably CRB) - GPIO config needs a clean-up
Not working: - Power LED is not happy and repeatedly blinks twice (BIOS recovery). - VGA on D3463 expansion card: Uses a NXP PTN3355 DP2VGA chip, most likely uses DDI E, and libgfxinit does not support DDI E yet.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/gpio.c A src/mainboard/fujitsu/d3410-b1/romstage.c 14 files changed, 520 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/6
Attention is currently required from: Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 6:
(53 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/5711fc4c_75620ce5 PS6, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/96ddd2e5_94091ae9 PS6, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ac08aff2_593a865b PS6, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3fab7540_47e61bbf PS6, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c16e9240_106cc2ba PS6, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/01a44e51_16a05850 PS6, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ecbe55b1_dadb7fc5 PS6, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a254124e_6c5cb799 PS6, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7cea9d67_b245b5dd PS6, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/dc2fdeec_3639c7ba PS6, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/320de2b8_e5fb8050 PS6, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d2078032_aa0a1dc7 PS6, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f63ac438_d84e6175 PS6, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d529f8ef_8f70ae95 PS6, Line 26: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b1ff02e0_ecf45fb5 PS6, Line 29: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5fa914a2_95600e01 PS6, Line 33: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d7cf7150_06e78df7 PS6, Line 34: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e5a442c4_6f320778 PS6, Line 35: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/0822d2de_0d6e0724 PS6, Line 37: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ad422472_a5d78851 PS6, Line 38: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a0133844_465da97b PS6, Line 39: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/bd09bcfa_1fb068e4 PS6, Line 44: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8ca228c9_0e378c54 PS6, Line 45: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/43bf300c_29dabdbb PS6, Line 46: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e9e1db84_bf447222 PS6, Line 47: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1f10f6f8_de6b9af8 PS6, Line 48: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/62639e10_5be11c84 PS6, Line 49: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7bb33726_f7f0c776 PS6, Line 50: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2b4d0a3e_a8767344 PS6, Line 51: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c44bc35e_10663935 PS6, Line 52: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b9c65ad8_75aec499 PS6, Line 57: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b588b47c_85f47873 PS6, Line 58: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/23eca670_1c1900dd PS6, Line 59: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c6e6fa82_010a3560 PS6, Line 62: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5d590158_b46ce40d PS6, Line 63: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9d30b0cf_182d7485 PS6, Line 64: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a6296495_8c80393e PS6, Line 65: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9f34f4f0_c92fc437 PS6, Line 66: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/391a92dd_f7012023 PS6, Line 69: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/90b59170_604d1b7b PS6, Line 70: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/49dbc85c_c40a55f4 PS6, Line 79: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2e9b2cc7_24d6c060 PS6, Line 82: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7d9f2d3d_09f2ac39 PS6, Line 105: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a1c20915_ba54d223 PS6, Line 106: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/98f5744c_7e4d5b67 PS6, Line 107: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d7691467_eb8413ae PS6, Line 108: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a09d904d_36c0d9e6 PS6, Line 109: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ca20a882_99f18e7f PS6, Line 110: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3e54f7e8_fbdeef1d PS6, Line 111: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/258433ac_69f9f27d PS6, Line 112: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/475d44dc_3546d82b PS6, Line 113: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a84a3ac4_09258f7b PS6, Line 114: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/037d132a_c447ed59 PS6, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/fujitsu/d3410-b1/Kconfig:
https://review.coreboot.org/c/coreboot/+/48383/comment/2fc8ec58_9c0e077a PS5, Line 34: config USE_LEGACY_8254_TIMER
SeaBIOS hangs without it, but it should be enabled by default in that case.
Gone
File src/mainboard/fujitsu/d3410-b1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48383/comment/af89a11c_711fb8c2 PS5, Line 77: register "SataTestMode" = "1
Fine, I'll make it a Kconfig option instead.
CB:52099
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/fujitsu/d3410-b1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48383/comment/4d719b5b_7dddee8a PS5, Line 126: irq 0x70 = 1 : irq 0x72 = 12
IRQ numbers are usually written in decimal, whereas addresses and register offsets are most often he […]
Ack
https://review.coreboot.org/c/coreboot/+/48383/comment/85957eaf_4090a69c PS5, Line 163: io 0x62 = 0 : irq 0x70 = 0 :
In this case, it's to emphasize that these are disabled.
Ack
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 7:
(53 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/d9019d3a_89c3f9cf PS7, Line 13: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fe89ca43_6885fd4a PS7, Line 14: _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2d72b4d5_9afd7c01 PS7, Line 15: _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5f19419a_f32ac74c PS7, Line 16: _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/90221c66_fffab098 PS7, Line 17: _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/defe953b_e3bd334d PS7, Line 18: _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1f891b4b_d830eddc PS7, Line 19: _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/435856ba_55da2ca6 PS7, Line 20: _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d23c5297_d4b2c515 PS7, Line 21: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4dd1f745_731359ee PS7, Line 22: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/108f059b_c6abf294 PS7, Line 23: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/15dfd188_b2e2f4c7 PS7, Line 24: _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/55f12419_0948bd15 PS7, Line 25: _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/24f9c141_78c952a0 PS7, Line 26: _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/31c24430_64a109f7 PS7, Line 29: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1c1cc7c7_f9778007 PS7, Line 33: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e4304e39_d8b7d93f PS7, Line 34: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/858d51a3_e7705497 PS7, Line 35: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1932c744_dae18528 PS7, Line 37: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/fc18945e_f1ec4d7d PS7, Line 38: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c9ffeaa3_6404b45e PS7, Line 39: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/0de645d2_b362fda3 PS7, Line 44: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7001e7e3_089bee6a PS7, Line 45: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a4f78559_a8638c3c PS7, Line 46: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9e60849f_4b917e73 PS7, Line 47: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5a92754f_b5a1c18d PS7, Line 48: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/44af547d_413db882 PS7, Line 49: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f20772a5_ad6ef610 PS7, Line 50: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2359d58d_6e04190f PS7, Line 51: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9b0ec18c_0b47000e PS7, Line 52: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ebd4f87a_f4828165 PS7, Line 57: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/021f411e_3659ae78 PS7, Line 58: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/eee69b11_f003955e PS7, Line 59: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c5f56d12_c904367e PS7, Line 62: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/b113171b_63257f7e PS7, Line 63: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f3cfe06f_1ec8744b PS7, Line 64: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/851bb736_630fd89b PS7, Line 65: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f008c28b_30bb8a32 PS7, Line 66: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4e2773ba_f2204365 PS7, Line 69: _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a973c5c1_2623e794 PS7, Line 70: _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/67a4ee66_a5a444ee PS7, Line 79: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/50c9a318_0d5d71e7 PS7, Line 82: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/ab194a8f_133c0200 PS7, Line 105: _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/e2cea184_db60c059 PS7, Line 106: _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/35cfa0b2_35640da3 PS7, Line 107: _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/a825907d_0b4dacdd PS7, Line 108: _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d5913d93_12ae31b5 PS7, Line 109: _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c5b46b46_75d79e7d PS7, Line 110: _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/c75d3c87_91815d2d PS7, Line 111: _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/bd1a199f_1d7406a7 PS7, Line 112: _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7a77aecf_05943f6c PS7, Line 113: _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/f49f5ffe_302d02fe PS7, Line 114: _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/3d6fcf9a_c611b43d PS7, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#8).
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
mb/fujitsu/d3410-b1: Add new mainboard
This is a µATX mainboard with a LGA1151 socket and two DDR4 DIMM slots.
Working: - Both DIMM slots (Micron CT4G4DFS8213.8FA11, Hynix HMA851U6AFR6N-UH) - Super I/O serial port and fan tachometer inputs - All USB 2.0 ports and rear USB 3.0 ports - Realtek RTL8111E GbE NIC - Integrated graphics on DP and DVI with libgfxinit - At least one SATA port - PCIe x16 and both PCIe x1 slots - Flashing internally with flashrom - SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
TO TEST: - Audio - Front USB 3.0 ports - VBT - PS/2 - TPM (probably CRB) - GPIO config needs a clean-up
Not working: - S3 suspend/resume sometimes fails (powers off then back on). - VGA on D3463 expansion card: Uses a NXP PTN3355 DP2VGA chip, most likely uses DDI E, and libgfxinit does not support DDI E yet.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/die.c A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/gpio.c A src/mainboard/fujitsu/d3410-b1/romstage.c 15 files changed, 523 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 8:
(27 comments)
File src/mainboard/fujitsu/d3410-b1/gpio.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/28902632_12b225a3 PS8, Line 12: _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/6fd4dc9f_c8565b8e PS8, Line 15: _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/86859107_444c0349 PS8, Line 16: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9c97b312_53f0db56 PS8, Line 17: _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5fd87857_502cb4cd PS8, Line 19: _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/4ae83277_3926b6fd PS8, Line 20: _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/67fdb117_0353dfa5 PS8, Line 21: _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/276b6adf_e6531da2 PS8, Line 24: _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/1eab4f94_cc2d7b30 PS8, Line 25: _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/7ae5393c_57bd12e3 PS8, Line 26: _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/12e09885_2c5d777c PS8, Line 27: _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/9924e763_d306f165 PS8, Line 28: _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/3ff4479f_eeda1e7c PS8, Line 29: _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/128b6022_56d3ed12 PS8, Line 30: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/d1c8ca03_502d0c03 PS8, Line 31: _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/46befee5_3048e308 PS8, Line 32: _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/5e5625e3_4f49ce29 PS8, Line 37: _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/80c18a1b_e8c79bf2 PS8, Line 38: _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/73f5ea4c_ddce8b24 PS8, Line 39: _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8f44d5cc_bf664395 PS8, Line 42: _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/bed1a2d9_8f8de46a PS8, Line 43: _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/8443ede2_db9f83dc PS8, Line 44: _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/2adf39d3_37465cf6 PS8, Line 45: _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/85b4140a_73e934ae PS8, Line 46: _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/71bfe45c_d1c17a8f PS8, Line 57: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/48383/comment/82ef93c4_f4e9e45b PS8, Line 60: _PAD_CFG_STRUCT(GPP_H12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(DN_20K)), line over 96 characters
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/9b33b2c9_569f373f PS8, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/ad66e49c_ad88db7d PS8, Line 35: * NUC029FAE microcontroller pin mapping: : * Pin 4: Power LED : * Pin 9: HDD LED : * Pin 10: Power button : * Pin 13: Wired to PCH GPP_H15 : move to the board docs?
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 8: Code-Review+1
Attention is currently required from: Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/1646c27c_e66e951a PS8, Line 35: * NUC029FAE microcontroller pin mapping: : * Pin 4: Power LED : * Pin 9: HDD LED : * Pin 10: Power button : * Pin 13: Wired to PCH GPP_H15 :
move to the board docs?
I would have to create a docs page, which would be rather empty ._.
IMHO, the most important part of board docs is "how to flash". However, unlike most people, I never do in-circuit flashing, so I don't know if it works on this board. Still, I'll see what I can do. I need to clean up gpio.c anyway.
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/7c9ecb44_8ab51949 PS8, Line 35: * NUC029FAE microcontroller pin mapping: : * Pin 4: Power LED : * Pin 9: HDD LED : * Pin 10: Power button : * Pin 13: Wired to PCH GPP_H15 :
I would have to create a docs page, which would be rather empty ._. […]
Docs would also contain working/non-working stuff, which is pretty interesting for people looking on the docs site ;)
Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#9).
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
mb/fujitsu/d3410-b1: Add new mainboard
Mainboard information can be found in the included documentation.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A Documentation/mainboard/fujitsu/d3410-b1.md M Documentation/mainboard/index.md A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/data.vbt A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/die.c A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/hda_verb.c A src/mainboard/fujitsu/d3410-b1/romstage.c 18 files changed, 582 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/9
Attention is currently required from: Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/37fa0eee_23bdb70b PS8, Line 35: * NUC029FAE microcontroller pin mapping: : * Pin 4: Power LED : * Pin 9: HDD LED : * Pin 10: Power button : * Pin 13: Wired to PCH GPP_H15 :
Docs would also contain working/non-working stuff, which is pretty interesting for people looking on […]
Done
Attention is currently required from: Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/518c321e_df327463 PS9, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#10).
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
mb/fujitsu/d3410-b1: Add new mainboard
Mainboard information can be found in the included documentation.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A Documentation/mainboard/fujitsu/d3410-b1.md M Documentation/mainboard/index.md A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/data.vbt A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/die.c A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/hda_verb.c A src/mainboard/fujitsu/d3410-b1/romstage.c 18 files changed, 583 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/10
Attention is currently required from: Angel Pons, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/e71f4833_721c19e5 PS10, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48383
to look at the new patch set (#11).
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
mb/fujitsu/d3410-b1: Add new mainboard
Mainboard information can be found in the included documentation.
Change-Id: I1fd843cd783b0324866933b95dd46eaccb634ba8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A Documentation/mainboard/fujitsu/d3410-b1.md M Documentation/mainboard/index.md A src/mainboard/fujitsu/Kconfig A src/mainboard/fujitsu/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Kconfig A src/mainboard/fujitsu/d3410-b1/Kconfig.name A src/mainboard/fujitsu/d3410-b1/Makefile.inc A src/mainboard/fujitsu/d3410-b1/acpi/ec.asl A src/mainboard/fujitsu/d3410-b1/acpi/superio.asl A src/mainboard/fujitsu/d3410-b1/board_info.txt A src/mainboard/fujitsu/d3410-b1/bootblock.c A src/mainboard/fujitsu/d3410-b1/data.vbt A src/mainboard/fujitsu/d3410-b1/devicetree.cb A src/mainboard/fujitsu/d3410-b1/die.c A src/mainboard/fujitsu/d3410-b1/dsdt.asl A src/mainboard/fujitsu/d3410-b1/gma-mainboard.ads A src/mainboard/fujitsu/d3410-b1/hda_verb.c A src/mainboard/fujitsu/d3410-b1/romstage.c 18 files changed, 583 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48383/11
Attention is currently required from: Angel Pons, Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/8eda9ef6_7948a6ff PS11, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Angel Pons, Michael Niewöhner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 11: Code-Review+1
Attention is currently required from: Michael Niewöhner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/fujitsu/d3410-b1/romstage.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/c46bc5d9_29395d5d PS12, Line 18: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV)
Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48383 )
Change subject: mb/fujitsu/d3410-b1: Add new mainboard ......................................................................
Patch Set 12:
(4 comments)
File src/mainboard/fujitsu/d3410-b1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/48383/comment/08192070_919b0bc9 PS12, Line 9: We had a private discussion on this already, so just for the record:
1. IMO all pads should be configured, even if they match the "reset" values, because the GPIO file also serves as sort-of documentation how the pads are configured.
2. Reset values: There is a possibility to change these "reset" values using the FIT tool. On ME-platforms only a few pads can be configured, while on server platforms (SPS) many more pads' reset values/functions can be edited via dropdowns.
That means, the values in the datasheet is the hardware reset value but software (probably ME) can override them and we can't always rely on these values and should instead always configure all pads, so we have a defined, sane state.
https://review.coreboot.org/c/coreboot/+/48383/comment/23e3539a_41f64d1f PS12, Line 11: UP_20K uhm, that is 0b1100, which is only valid in eSPI mode. LPC *must* have `NATIVE` (0b1111) here, according to the pch ds vol2. does that board use eSPI?
https://review.coreboot.org/c/coreboot/+/48383/comment/7875d858_6f296347 PS12, Line 34: DEEP inteltooldump says 0b11 (reserved), just like the GPP_I* below
https://review.coreboot.org/c/coreboot/+/48383/comment/932be254_7983b97c PS12, Line 57: PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I1, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I2, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I3, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I5, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I6, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I7, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I8, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I9, NONE, PWROK, NF1), : PAD_CFG_NF(GPP_I10, NONE, PWROK, NF1), : your inteltool dump says PADRSTCFG=0b11, which is "Reserved"... eds also says reserved... hmm. default for these pads is DEEP, which should be ok
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Michael Niewöhner (Code Review)
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Paul Menzel (Code Review)